luna - luajit/src/lj_asm

   1/*
   2** PPC IR assembler (SSA IR -> machine code).
   3** Copyright (C) 2005-2026 Mike Pall. See Copyright Notice in luajit.h
   4*/
   5
   6/* -- Register allocator extensions --------------------------------------- */
   7
   8/* Allocate a register with a hint. */
   9static Reg ra_hintalloc(ASMState *as, IRRef ref, Reg hint, RegSet allow)
  10{
  11  Reg r = IR(ref)->r;
  12  if (ra_noreg(r)) {
  13    if (!ra_hashint(r) && !iscrossref(as, ref))
  14      ra_sethint(IR(ref)->r, hint);  /* Propagate register hint. */
  15    r = ra_allocref(as, ref, allow);
  16  }
  17  ra_noweak(as, r);
  18  return r;
  19}
  20
  21/* Allocate two source registers for three-operand instructions. */
  22static Reg ra_alloc2(ASMState *as, IRIns *ir, RegSet allow)
  23{
  24  IRIns *irl = IR(ir->op1), *irr = IR(ir->op2);
  25  Reg left = irl->r, right = irr->r;
  26  if (ra_hasreg(left)) {
  27    ra_noweak(as, left);
  28    if (ra_noreg(right))
  29      right = ra_allocref(as, ir->op2, rset_exclude(allow, left));
  30    else
  31      ra_noweak(as, right);
  32  } else if (ra_hasreg(right)) {
  33    ra_noweak(as, right);
  34    left = ra_allocref(as, ir->op1, rset_exclude(allow, right));
  35  } else if (ra_hashint(right)) {
  36    right = ra_allocref(as, ir->op2, allow);
  37    left = ra_alloc1(as, ir->op1, rset_exclude(allow, right));
  38  } else {
  39    left = ra_allocref(as, ir->op1, allow);
  40    right = ra_alloc1(as, ir->op2, rset_exclude(allow, left));
  41  }
  42  return left | (right << 8);
  43}
  44
  45/* -- Guard handling ------------------------------------------------------ */
  46
  47/* Setup exit stubs after the end of each trace. */
  48static void asm_exitstub_setup(ASMState *as, ExitNo nexits)
  49{
  50  ExitNo i;
  51  int ind;
  52  uintptr_t target = (uintptr_t)(void *)lj_vm_exit_handler;
  53  MCode *mxp = as->mctop;
  54  if (mxp - (nexits + 4 + MCLIM_REDZONE) < as->mclim)
  55    asm_mclimit(as);
  56  ind = ((target - (uintptr_t)(mxp - nexits - 2) + 0x02000000u) >> 26) ? 2 : 0;
  57  /* !ind: 1: mflr r0; bl ->vm_exit_handler; li r0, traceno;
  58  **  ind: 1: lwz r0, K32_VXH(jgl); mtctr r0; mflr r0; bctrl; li r0, traceno;
  59  **          bl <1; bl <1; ...
  60  */
  61  for (i = nexits-1; (int32_t)i >= 0; i--)
  62    *--mxp = PPCI_BL | (((-3-ind-i) & 0x00ffffffu) << 2);
  63  as->mcexit = mxp;
  64  *--mxp = PPCI_LI|PPCF_T(RID_TMP)|as->T->traceno;  /* Read by exit handler. */
  65  if (ind) {
  66    *--mxp = PPCI_BCTRL;
  67    *--mxp = PPCI_MFLR | PPCF_T(RID_TMP);
  68    *--mxp = PPCI_MTCTR | PPCF_T(RID_TMP);
  69    *--mxp = PPCI_LWZ | PPCF_T(RID_TMP) | PPCF_A(RID_JGL) |
  70	     jglofs(as, &as->J->k32[LJ_K32_VM_EXIT_HANDLER]);
  71  } else {
  72    mxp--;
  73    *mxp = PPCI_BL | ((target - (uintptr_t)mxp) & 0x03fffffcu);
  74    *--mxp = PPCI_MFLR | PPCF_T(RID_TMP);
  75  }
  76  as->mctop = mxp;
  77}
  78
  79static MCode *asm_exitstub_addr(ASMState *as, ExitNo exitno)
  80{
  81  /* Keep this in-sync with exitstub_trace_addr(). */
  82  return as->mcexit + exitno;
  83}
  84
  85/* Emit conditional branch to exit for guard. */
  86static void asm_guardcc(ASMState *as, PPCCC cc)
  87{
  88  MCode *target = asm_exitstub_addr(as, as->snapno);
  89  MCode *p = as->mcp;
  90  if (LJ_UNLIKELY(p == as->invmcp)) {
  91    as->loopinv = 1;
  92    *p = PPCI_B | (((target-p) & 0x00ffffffu) << 2);
  93    emit_condbranch(as, PPCI_BC, cc^4, p);
  94    return;
  95  }
  96  emit_condbranch(as, PPCI_BC, cc, target);
  97}
  98
  99/* -- Operand fusion ------------------------------------------------------ */
 100
 101/* Limit linear search to this distance. Avoids O(n^2) behavior. */
 102#define CONFLICT_SEARCH_LIM	31
 103
 104/* Check if there's no conflicting instruction between curins and ref. */
 105static int noconflict(ASMState *as, IRRef ref, IROp conflict)
 106{
 107  IRIns *ir = as->ir;
 108  IRRef i = as->curins;
 109  if (i > ref + CONFLICT_SEARCH_LIM)
 110    return 0;  /* Give up, ref is too far away. */
 111  while (--i > ref)
 112    if (ir[i].o == conflict)
 113      return 0;  /* Conflict found. */
 114  return 1;  /* Ok, no conflict. */
 115}
 116
 117/* Fuse the array base of colocated arrays. */
 118static int32_t asm_fuseabase(ASMState *as, IRRef ref)
 119{
 120  IRIns *ir = IR(ref);
 121  if (ir->o == IR_TNEW && ir->op1 <= LJ_MAX_COLOSIZE &&
 122      !neverfuse(as) && noconflict(as, ref, IR_NEWREF))
 123    return (int32_t)sizeof(GCtab);
 124  return 0;
 125}
 126
 127/* Indicates load/store indexed is ok. */
 128#define AHUREF_LSX	((int32_t)0x80000000)
 129
 130/* Fuse array/hash/upvalue reference into register+offset operand. */
 131static Reg asm_fuseahuref(ASMState *as, IRRef ref, int32_t *ofsp, RegSet allow)
 132{
 133  IRIns *ir = IR(ref);
 134  if (ra_noreg(ir->r)) {
 135    if (ir->o == IR_AREF) {
 136      if (mayfuse(as, ref)) {
 137	if (irref_isk(ir->op2)) {
 138	  IRRef tab = IR(ir->op1)->op1;
 139	  int32_t ofs = asm_fuseabase(as, tab);
 140	  IRRef refa = ofs ? tab : ir->op1;
 141	  ofs += 8*IR(ir->op2)->i;
 142	  if (checki16(ofs)) {
 143	    *ofsp = ofs;
 144	    return ra_alloc1(as, refa, allow);
 145	  }
 146	}
 147	if (*ofsp == AHUREF_LSX) {
 148	  Reg base = ra_alloc1(as, ir->op1, allow);
 149	  Reg idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
 150	  return base | (idx << 8);
 151	}
 152      }
 153    } else if (ir->o == IR_HREFK) {
 154      if (mayfuse(as, ref)) {
 155	int32_t ofs = (int32_t)(IR(ir->op2)->op2 * sizeof(Node));
 156	if (checki16(ofs)) {
 157	  *ofsp = ofs;
 158	  return ra_alloc1(as, ir->op1, allow);
 159	}
 160      }
 161    } else if (ir->o == IR_UREFC) {
 162      if (irref_isk(ir->op1)) {
 163	GCfunc *fn = ir_kfunc(IR(ir->op1));
 164	int32_t ofs = i32ptr(&gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.tv);
 165	int32_t jgl = (intptr_t)J2G(as->J);
 166	if ((uint32_t)(ofs-jgl) < 65536) {
 167	  *ofsp = ofs-jgl-32768;
 168	  return RID_JGL;
 169	} else {
 170	  *ofsp = (int16_t)ofs;
 171	  return ra_allock(as, ofs-(int16_t)ofs, allow);
 172	}
 173      }
 174    } else if (ir->o == IR_TMPREF) {
 175      *ofsp = (int32_t)(offsetof(global_State, tmptv)-32768);
 176      return RID_JGL;
 177    }
 178  }
 179  *ofsp = 0;
 180  return ra_alloc1(as, ref, allow);
 181}
 182
 183/* Fuse XLOAD/XSTORE reference into load/store operand. */
 184static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
 185			 RegSet allow, int32_t ofs)
 186{
 187  IRIns *ir = IR(ref);
 188  Reg base;
 189  if (ra_noreg(ir->r) && canfuse(as, ir)) {
 190    if (ir->o == IR_ADD) {
 191      int32_t ofs2;
 192      if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
 193	ofs = ofs2;
 194	ref = ir->op1;
 195      } else if (ofs == 0) {
 196	Reg right, left = ra_alloc2(as, ir, allow);
 197	right = (left >> 8); left &= 255;
 198	emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
 199	return;
 200      }
 201    } else if (ir->o == IR_STRREF) {
 202      lj_assertA(ofs == 0, "bad usage");
 203      ofs = (int32_t)sizeof(GCstr);
 204      if (irref_isk(ir->op2)) {
 205	ofs += IR(ir->op2)->i;
 206	ref = ir->op1;
 207      } else if (irref_isk(ir->op1)) {
 208	ofs += IR(ir->op1)->i;
 209	ref = ir->op2;
 210      } else {
 211	/* NYI: Fuse ADD with constant. */
 212	Reg tmp, right, left = ra_alloc2(as, ir, allow);
 213	right = (left >> 8); left &= 255;
 214	tmp = ra_scratch(as, rset_exclude(rset_exclude(allow, left), right));
 215	emit_fai(as, pi, rt, tmp, ofs);
 216	emit_tab(as, PPCI_ADD, tmp, left, right);
 217	return;
 218      }
 219      if (!checki16(ofs)) {
 220	Reg left = ra_alloc1(as, ref, allow);
 221	Reg right = ra_allock(as, ofs, rset_exclude(allow, left));
 222	emit_fab(as, PPCI_LWZX | ((pi >> 20) & 0x780), rt, left, right);
 223	return;
 224      }
 225    }
 226  }
 227  base = ra_alloc1(as, ref, allow);
 228  emit_fai(as, pi, rt, base, ofs);
 229}
 230
 231/* Fuse XLOAD/XSTORE reference into indexed-only load/store operand. */
 232static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
 233			  RegSet allow)
 234{
 235  IRIns *ira = IR(ref);
 236  Reg right, left;
 237  if (canfuse(as, ira) && ira->o == IR_ADD && ra_noreg(ira->r)) {
 238    left = ra_alloc2(as, ira, allow);
 239    right = (left >> 8); left &= 255;
 240  } else {
 241    right = ra_alloc1(as, ref, allow);
 242    left = RID_R0;
 243  }
 244  emit_tab(as, pi, rt, left, right);
 245}
 246
 247#if !LJ_SOFTFP
 248/* Fuse to multiply-add/sub instruction. */
 249static int asm_fusemadd(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pir)
 250{
 251  IRRef lref = ir->op1, rref = ir->op2;
 252  IRIns *irm;
 253  if ((as->flags & JIT_F_OPT_FMA) &&
 254      lref != rref &&
 255      ((mayfuse(as, lref) && (irm = IR(lref), irm->o == IR_MUL) &&
 256	ra_noreg(irm->r)) ||
 257       (mayfuse(as, rref) && (irm = IR(rref), irm->o == IR_MUL) &&
 258	(rref = lref, pi = pir, ra_noreg(irm->r))))) {
 259    Reg dest = ra_dest(as, ir, RSET_FPR);
 260    Reg add = ra_alloc1(as, rref, RSET_FPR);
 261    Reg right, left = ra_alloc2(as, irm, rset_exclude(RSET_FPR, add));
 262    right = (left >> 8); left &= 255;
 263    emit_facb(as, pi, dest, left, right, add);
 264    return 1;
 265  }
 266  return 0;
 267}
 268#endif
 269
 270/* -- Calls --------------------------------------------------------------- */
 271
 272/* Generate a call to a C function. */
 273static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
 274{
 275  uint32_t n, nargs = CCI_XNARGS(ci);
 276  int32_t ofs = 8;
 277  Reg gpr = REGARG_FIRSTGPR;
 278#if !LJ_SOFTFP
 279  Reg fpr = REGARG_FIRSTFPR;
 280#endif
 281  if ((void *)ci->func)
 282    emit_call(as, (void *)ci->func);
 283  for (n = 0; n < nargs; n++) {  /* Setup args. */
 284    IRRef ref = args[n];
 285    if (ref) {
 286      IRIns *ir = IR(ref);
 287#if !LJ_SOFTFP
 288      if (irt_isfp(ir->t)) {
 289	if (fpr <= REGARG_LASTFPR) {
 290	  lj_assertA(rset_test(as->freeset, fpr),
 291		     "reg %d not free", fpr);  /* Already evicted. */
 292	  ra_leftov(as, fpr, ref);
 293	  fpr++;
 294	} else {
 295	  Reg r = ra_alloc1(as, ref, RSET_FPR);
 296	  if (irt_isnum(ir->t)) ofs = (ofs + 4) & ~4;
 297	  emit_spstore(as, ir, r, ofs);
 298	  ofs += irt_isnum(ir->t) ? 8 : 4;
 299	}
 300      } else
 301#endif
 302      {
 303	if (gpr <= REGARG_LASTGPR) {
 304	  lj_assertA(rset_test(as->freeset, gpr),
 305		     "reg %d not free", gpr);  /* Already evicted. */
 306	  ra_leftov(as, gpr, ref);
 307	  gpr++;
 308	} else {
 309	  Reg r = ra_alloc1(as, ref, RSET_GPR);
 310	  emit_spstore(as, ir, r, ofs);
 311	  ofs += 4;
 312	}
 313      }
 314    } else {
 315      if (gpr <= REGARG_LASTGPR)
 316	gpr++;
 317      else
 318	ofs += 4;
 319    }
 320    checkmclim(as);
 321  }
 322#if !LJ_SOFTFP
 323  if ((ci->flags & CCI_VARARG))  /* Vararg calls need to know about FPR use. */
 324    emit_tab(as, fpr == REGARG_FIRSTFPR ? PPCI_CRXOR : PPCI_CREQV, 6, 6, 6);
 325#endif
 326}
 327
 328/* Setup result reg/sp for call. Evict scratch regs. */
 329static void asm_setupresult(ASMState *as, IRIns *ir, const CCallInfo *ci)
 330{
 331  RegSet drop = RSET_SCRATCH;
 332  int hiop = ((ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t));
 333#if !LJ_SOFTFP
 334  if ((ci->flags & CCI_NOFPRCLOBBER))
 335    drop &= ~RSET_FPR;
 336#endif
 337  if (ra_hasreg(ir->r))
 338    rset_clear(drop, ir->r);  /* Dest reg handled below. */
 339  if (hiop && ra_hasreg((ir+1)->r))
 340    rset_clear(drop, (ir+1)->r);  /* Dest reg handled below. */
 341  ra_evictset(as, drop);  /* Evictions must be performed first. */
 342  if (ra_used(ir)) {
 343    lj_assertA(!irt_ispri(ir->t), "PRI dest");
 344    if (!LJ_SOFTFP && irt_isfp(ir->t)) {
 345      if ((ci->flags & CCI_CASTU64)) {
 346	/* Use spill slot or temp slots. */
 347	int32_t ofs = ir->s ? sps_scale(ir->s) : SPOFS_TMP;
 348	Reg dest = ir->r;
 349	if (ra_hasreg(dest)) {
 350	  ra_free(as, dest);
 351	  ra_modified(as, dest);
 352	  emit_fai(as, PPCI_LFD, dest, RID_SP, ofs);
 353	}
 354	emit_tai(as, PPCI_STW, RID_RETHI, RID_SP, ofs);
 355	emit_tai(as, PPCI_STW, RID_RETLO, RID_SP, ofs+4);
 356      } else {
 357	ra_destreg(as, ir, RID_FPRET);
 358      }
 359    } else if (hiop) {
 360      ra_destpair(as, ir);
 361    } else {
 362      ra_destreg(as, ir, RID_RET);
 363    }
 364  }
 365}
 366
 367static void asm_callx(ASMState *as, IRIns *ir)
 368{
 369  IRRef args[CCI_NARGS_MAX*2];
 370  CCallInfo ci;
 371  IRRef func;
 372  IRIns *irf;
 373  ci.flags = asm_callx_flags(as, ir);
 374  asm_collectargs(as, ir, &ci, args);
 375  asm_setupresult(as, ir, &ci);
 376  func = ir->op2; irf = IR(func);
 377  if (irf->o == IR_CARG) { func = irf->op1; irf = IR(func); }
 378  if (irref_isk(func)) {  /* Call to constant address. */
 379    ci.func = (ASMFunction)(void *)(intptr_t)(irf->i);
 380  } else {  /* Need a non-argument register for indirect calls. */
 381    RegSet allow = RSET_GPR & ~RSET_RANGE(RID_R0, REGARG_LASTGPR+1);
 382    Reg freg = ra_alloc1(as, func, allow);
 383    *--as->mcp = PPCI_BCTRL;
 384    *--as->mcp = PPCI_MTCTR | PPCF_T(freg);
 385    ci.func = (ASMFunction)(void *)0;
 386  }
 387  asm_gencall(as, &ci, args);
 388}
 389
 390/* -- Returns ------------------------------------------------------------- */
 391
 392/* Return to lower frame. Guard that it goes to the right spot. */
 393static void asm_retf(ASMState *as, IRIns *ir)
 394{
 395  Reg base = ra_alloc1(as, REF_BASE, RSET_GPR);
 396  void *pc = ir_kptr(IR(ir->op2));
 397  int32_t delta = 1+LJ_FR2+bc_a(*((const BCIns *)pc - 1));
 398  as->topslot -= (BCReg)delta;
 399  if ((int32_t)as->topslot < 0) as->topslot = 0;
 400  irt_setmark(IR(REF_BASE)->t);  /* Children must not coalesce with BASE reg. */
 401  emit_setgl(as, base, jit_base);
 402  emit_addptr(as, base, -8*delta);
 403  asm_guardcc(as, CC_NE);
 404  emit_ab(as, PPCI_CMPW, RID_TMP,
 405	  ra_allock(as, i32ptr(pc), rset_exclude(RSET_GPR, base)));
 406  emit_tai(as, PPCI_LWZ, RID_TMP, base, -8);
 407}
 408
 409/* -- Buffer operations --------------------------------------------------- */
 410
 411#if LJ_HASBUFFER
 412static void asm_bufhdr_write(ASMState *as, Reg sb)
 413{
 414  Reg tmp = ra_scratch(as, rset_exclude(RSET_GPR, sb));
 415  IRIns irgc;
 416  irgc.ot = IRT(0, IRT_PGC);  /* GC type. */
 417  emit_storeofs(as, &irgc, RID_TMP, sb, offsetof(SBuf, L));
 418  emit_rot(as, PPCI_RLWIMI, RID_TMP, tmp, 0, 31-lj_fls(SBUF_MASK_FLAG), 31);
 419  emit_getgl(as, RID_TMP, cur_L);
 420  emit_loadofs(as, &irgc, tmp, sb, offsetof(SBuf, L));
 421}
 422#endif
 423
 424/* -- Type conversions ---------------------------------------------------- */
 425
 426#if !LJ_SOFTFP
 427static void asm_tointg(ASMState *as, IRIns *ir, Reg left)
 428{
 429  RegSet allow = RSET_FPR;
 430  Reg tmp = ra_scratch(as, rset_clear(allow, left));
 431  Reg fbias = ra_scratch(as, rset_clear(allow, tmp));
 432  Reg dest = ra_dest(as, ir, RSET_GPR);
 433  Reg hibias = ra_allock(as, 0x43300000, rset_exclude(RSET_GPR, dest));
 434  asm_guardcc(as, CC_NE);
 435  emit_fab(as, PPCI_FCMPU, 0, tmp, left);
 436  emit_fab(as, PPCI_FSUB, tmp, tmp, fbias);
 437  emit_fai(as, PPCI_LFD, tmp, RID_SP, SPOFS_TMP);
 438  emit_tai(as, PPCI_STW, RID_TMP, RID_SP, SPOFS_TMPLO);
 439  emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
 440  emit_asi(as, PPCI_XORIS, RID_TMP, dest, 0x8000);
 441  emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
 442  emit_lsptr(as, PPCI_LFS, (fbias & 31),
 443	     (void *)&as->J->k32[LJ_K32_2P52_2P31], RSET_GPR);
 444  emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 445  emit_fb(as, PPCI_FCTIWZ, tmp, left);
 446}
 447
 448static void asm_tobit(ASMState *as, IRIns *ir)
 449{
 450  RegSet allow = RSET_FPR;
 451  Reg dest = ra_dest(as, ir, RSET_GPR);
 452  Reg left = ra_alloc1(as, ir->op1, allow);
 453  Reg right = ra_alloc1(as, ir->op2, rset_clear(allow, left));
 454  Reg tmp = ra_scratch(as, rset_clear(allow, right));
 455  emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
 456  emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 457  emit_fab(as, PPCI_FADD, tmp, left, right);
 458}
 459#endif
 460
 461static void asm_conv(ASMState *as, IRIns *ir)
 462{
 463  IRType st = (IRType)(ir->op2 & IRCONV_SRCMASK);
 464#if !LJ_SOFTFP
 465  int stfp = (st == IRT_NUM || st == IRT_FLOAT);
 466#endif
 467  IRRef lref = ir->op1;
 468  /* 64 bit integer conversions are handled by SPLIT. */
 469  lj_assertA(!(irt_isint64(ir->t) || (st == IRT_I64 || st == IRT_U64)),
 470	     "IR %04d has unsplit 64 bit type",
 471	     (int)(ir - as->ir) - REF_BIAS);
 472#if LJ_SOFTFP
 473  /* FP conversions are handled by SPLIT. */
 474  lj_assertA(!irt_isfp(ir->t) && !(st == IRT_NUM || st == IRT_FLOAT),
 475	     "IR %04d has FP type",
 476	     (int)(ir - as->ir) - REF_BIAS);
 477  /* Can't check for same types: SPLIT uses CONV int.int + BXOR for sfp NEG. */
 478#else
 479  lj_assertA(irt_type(ir->t) != st, "inconsistent types for CONV");
 480  if (irt_isfp(ir->t)) {
 481    Reg dest = ra_dest(as, ir, RSET_FPR);
 482    if (stfp) {  /* FP to FP conversion. */
 483      if (st == IRT_NUM)  /* double -> float conversion. */
 484	emit_fb(as, PPCI_FRSP, dest, ra_alloc1(as, lref, RSET_FPR));
 485      else  /* float -> double conversion is a no-op on PPC. */
 486	ra_leftov(as, dest, lref);  /* Do nothing, but may need to move regs. */
 487    } else {  /* Integer to FP conversion. */
 488      /* IRT_INT: Flip hibit, bias with 2^52, subtract 2^52+2^31. */
 489      /* IRT_U32: Bias with 2^52, subtract 2^52. */
 490      RegSet allow = RSET_GPR;
 491      Reg left = ra_alloc1(as, lref, allow);
 492      Reg hibias = ra_allock(as, 0x43300000, rset_clear(allow, left));
 493      Reg fbias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
 494      if (irt_isfloat(ir->t)) emit_fb(as, PPCI_FRSP, dest, dest);
 495      emit_fab(as, PPCI_FSUB, dest, dest, fbias);
 496      emit_fai(as, PPCI_LFD, dest, RID_SP, SPOFS_TMP);
 497      emit_lsptr(as, PPCI_LFS, (fbias & 31),
 498		 &as->J->k32[st == IRT_U32 ? LJ_K32_2P52 : LJ_K32_2P52_2P31],
 499		 rset_clear(allow, hibias));
 500      emit_tai(as, PPCI_STW, st == IRT_U32 ? left : RID_TMP,
 501	       RID_SP, SPOFS_TMPLO);
 502      emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
 503      if (st != IRT_U32) emit_asi(as, PPCI_XORIS, RID_TMP, left, 0x8000);
 504    }
 505  } else if (stfp) {  /* FP to integer conversion. */
 506    if (irt_isguard(ir->t)) {
 507      /* Checked conversions are only supported from number to int. */
 508      lj_assertA(irt_isint(ir->t) && st == IRT_NUM,
 509		 "bad type for checked CONV");
 510      asm_tointg(as, ir, ra_alloc1(as, lref, RSET_FPR));
 511    } else {
 512      Reg dest = ra_dest(as, ir, RSET_GPR);
 513      Reg left = ra_alloc1(as, lref, RSET_FPR);
 514      Reg tmp = ra_scratch(as, rset_exclude(RSET_FPR, left));
 515      lj_assertA(!irt_isu32(ir->t), "bad CONV u32.fp emitted");
 516      emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
 517      emit_fai(as, PPCI_STFD, tmp, RID_SP, SPOFS_TMP);
 518      emit_fb(as, PPCI_FCTIWZ, tmp, left);
 519    }
 520  } else
 521#endif
 522  {
 523    Reg dest = ra_dest(as, ir, RSET_GPR);
 524    if (st >= IRT_I8 && st <= IRT_U16) {  /* Extend to 32 bit integer. */
 525      Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
 526      lj_assertA(irt_isint(ir->t) || irt_isu32(ir->t), "bad type for CONV EXT");
 527      if ((ir->op2 & IRCONV_SEXT))
 528	emit_as(as, st == IRT_I8 ? PPCI_EXTSB : PPCI_EXTSH, dest, left);
 529      else
 530	emit_rot(as, PPCI_RLWINM, dest, left, 0, st == IRT_U8 ? 24 : 16, 31);
 531    } else {  /* 32/64 bit integer conversions. */
 532      /* Only need to handle 32/32 bit no-op (cast) on 32 bit archs. */
 533      ra_leftov(as, dest, lref);  /* Do nothing, but may need to move regs. */
 534    }
 535  }
 536}
 537
 538static void asm_strto(ASMState *as, IRIns *ir)
 539{
 540  const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_strscan_num];
 541  IRRef args[2];
 542  int32_t ofs = SPOFS_TMP;
 543#if LJ_SOFTFP
 544  ra_evictset(as, RSET_SCRATCH);
 545  if (ra_used(ir)) {
 546    if (ra_hasspill(ir->s) && ra_hasspill((ir+1)->s) &&
 547	(ir->s & 1) == LJ_BE && (ir->s ^ 1) == (ir+1)->s) {
 548      int i;
 549      for (i = 0; i < 2; i++) {
 550	Reg r = (ir+i)->r;
 551	if (ra_hasreg(r)) {
 552	  ra_free(as, r);
 553	  ra_modified(as, r);
 554	  emit_spload(as, ir+i, r, sps_scale((ir+i)->s));
 555	}
 556      }
 557      ofs = sps_scale(ir->s & ~1);
 558    } else {
 559      Reg rhi = ra_dest(as, ir+1, RSET_GPR);
 560      Reg rlo = ra_dest(as, ir, rset_exclude(RSET_GPR, rhi));
 561      emit_tai(as, PPCI_LWZ, rhi, RID_SP, ofs);
 562      emit_tai(as, PPCI_LWZ, rlo, RID_SP, ofs+4);
 563    }
 564  }
 565#else
 566  RegSet drop = RSET_SCRATCH;
 567  if (ra_hasreg(ir->r)) rset_set(drop, ir->r);  /* Spill dest reg (if any). */
 568  ra_evictset(as, drop);
 569  if (ir->s) ofs = sps_scale(ir->s);
 570#endif
 571  asm_guardcc(as, CC_EQ);
 572  emit_ai(as, PPCI_CMPWI, RID_RET, 0);  /* Test return status. */
 573  args[0] = ir->op1;      /* GCstr *str */
 574  args[1] = ASMREF_TMP1;  /* TValue *n  */
 575  asm_gencall(as, ci, args);
 576  /* Store the result to the spill slot or temp slots. */
 577  emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_SP, ofs);
 578}
 579
 580/* -- Memory references --------------------------------------------------- */
 581
 582/* Get pointer to TValue. */
 583static void asm_tvptr(ASMState *as, Reg dest, IRRef ref, MSize mode)
 584{
 585  int32_t tmpofs = (int32_t)(offsetof(global_State, tmptv)-32768);
 586  if ((mode & IRTMPREF_IN1)) {
 587    IRIns *ir = IR(ref);
 588    if (irt_isnum(ir->t)) {
 589      if ((mode & IRTMPREF_OUT1)) {
 590#if LJ_SOFTFP
 591	lj_assertA(irref_isk(ref), "unsplit FP op");
 592	emit_tai(as, PPCI_ADDI, dest, RID_JGL, tmpofs);
 593	emit_setgl(as,
 594		   ra_allock(as, (int32_t)ir_knum(ir)->u32.lo, RSET_GPR),
 595		   tmptv.u32.lo);
 596	emit_setgl(as,
 597		   ra_allock(as, (int32_t)ir_knum(ir)->u32.hi, RSET_GPR),
 598		   tmptv.u32.hi);
 599#else
 600	Reg src = ra_alloc1(as, ref, RSET_FPR);
 601	emit_tai(as, PPCI_ADDI, dest, RID_JGL, tmpofs);
 602	emit_fai(as, PPCI_STFD, src, RID_JGL, tmpofs);
 603#endif
 604      } else if (irref_isk(ref)) {
 605	/* Use the number constant itself as a TValue. */
 606	ra_allockreg(as, i32ptr(ir_knum(ir)), dest);
 607      } else {
 608#if LJ_SOFTFP
 609	lj_assertA(0, "unsplit FP op");
 610#else
 611	/* Otherwise force a spill and use the spill slot. */
 612	emit_tai(as, PPCI_ADDI, dest, RID_SP, ra_spill(as, ir));
 613#endif
 614      }
 615    } else {
 616      /* Otherwise use g->tmptv to hold the TValue. */
 617      Reg type;
 618      emit_tai(as, PPCI_ADDI, dest, RID_JGL, tmpofs);
 619      if (!irt_ispri(ir->t)) {
 620	Reg src = ra_alloc1(as, ref, RSET_GPR);
 621	emit_setgl(as, src, tmptv.gcr);
 622      }
 623      if (LJ_SOFTFP && (ir+1)->o == IR_HIOP && !irt_isnil((ir+1)->t))
 624	type = ra_alloc1(as, ref+1, RSET_GPR);
 625      else
 626	type = ra_allock(as, irt_toitype(ir->t), RSET_GPR);
 627      emit_setgl(as, type, tmptv.it);
 628    }
 629  } else {
 630    emit_tai(as, PPCI_ADDI, dest, RID_JGL, tmpofs);
 631  }
 632}
 633
 634static void asm_aref(ASMState *as, IRIns *ir)
 635{
 636  Reg dest = ra_dest(as, ir, RSET_GPR);
 637  Reg idx, base;
 638  if (irref_isk(ir->op2)) {
 639    IRRef tab = IR(ir->op1)->op1;
 640    int32_t ofs = asm_fuseabase(as, tab);
 641    IRRef refa = ofs ? tab : ir->op1;
 642    ofs += 8*IR(ir->op2)->i;
 643    if (checki16(ofs)) {
 644      base = ra_alloc1(as, refa, RSET_GPR);
 645      emit_tai(as, PPCI_ADDI, dest, base, ofs);
 646      return;
 647    }
 648  }
 649  base = ra_alloc1(as, ir->op1, RSET_GPR);
 650  idx = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, base));
 651  emit_tab(as, PPCI_ADD, dest, RID_TMP, base);
 652  emit_slwi(as, RID_TMP, idx, 3);
 653}
 654
 655/* Inlined hash lookup. Specialized for key type and for const keys.
 656** The equivalent C code is:
 657**   Node *n = hashkey(t, key);
 658**   do {
 659**     if (lj_obj_equal(&n->key, key)) return &n->val;
 660**   } while ((n = nextnode(n)));
 661**   return niltv(L);
 662*/
 663static void asm_href(ASMState *as, IRIns *ir, IROp merge)
 664{
 665  RegSet allow = RSET_GPR;
 666  int destused = ra_used(ir);
 667  Reg dest = ra_dest(as, ir, allow);
 668  Reg tab = ra_alloc1(as, ir->op1, rset_clear(allow, dest));
 669  Reg key = RID_NONE, tmp1 = RID_TMP, tmp2;
 670  Reg tisnum = RID_NONE, tmpnum = RID_NONE;
 671  IRRef refkey = ir->op2;
 672  IRIns *irkey = IR(refkey);
 673  int isk = irref_isk(refkey);
 674  IRType1 kt = irkey->t;
 675  uint32_t khash;
 676  MCLabel l_end, l_loop, l_next;
 677
 678  rset_clear(allow, tab);
 679#if LJ_SOFTFP
 680  if (!isk) {
 681    key = ra_alloc1(as, refkey, allow);
 682    rset_clear(allow, key);
 683    if (irkey[1].o == IR_HIOP) {
 684      if (ra_hasreg((irkey+1)->r)) {
 685	tmpnum = (irkey+1)->r;
 686	ra_noweak(as, tmpnum);
 687      } else {
 688	tmpnum = ra_allocref(as, refkey+1, allow);
 689      }
 690      rset_clear(allow, tmpnum);
 691    }
 692  }
 693#else
 694  if (irt_isnum(kt)) {
 695    key = ra_alloc1(as, refkey, RSET_FPR);
 696    tmpnum = ra_scratch(as, rset_exclude(RSET_FPR, key));
 697    tisnum = ra_allock(as, (int32_t)LJ_TISNUM, allow);
 698    rset_clear(allow, tisnum);
 699  } else if (!irt_ispri(kt)) {
 700    key = ra_alloc1(as, refkey, allow);
 701    rset_clear(allow, key);
 702  }
 703#endif
 704  tmp2 = ra_scratch(as, allow);
 705  rset_clear(allow, tmp2);
 706
 707  /* Key not found in chain: jump to exit (if merged) or load niltv. */
 708  l_end = emit_label(as);
 709  as->invmcp = NULL;
 710  if (merge == IR_NE)
 711    asm_guardcc(as, CC_EQ);
 712  else if (destused)
 713    emit_loada(as, dest, niltvg(J2G(as->J)));
 714
 715  /* Follow hash chain until the end. */
 716  l_loop = --as->mcp;
 717  emit_ai(as, PPCI_CMPWI, dest, 0);
 718  emit_tai(as, PPCI_LWZ, dest, dest, (int32_t)offsetof(Node, next));
 719  l_next = emit_label(as);
 720
 721  /* Type and value comparison. */
 722  if (merge == IR_EQ)
 723    asm_guardcc(as, CC_EQ);
 724  else
 725    emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
 726  if (!LJ_SOFTFP && irt_isnum(kt)) {
 727    emit_fab(as, PPCI_FCMPU, 0, tmpnum, key);
 728    emit_condbranch(as, PPCI_BC, CC_GE, l_next);
 729    emit_ab(as, PPCI_CMPLW, tmp1, tisnum);
 730    emit_fai(as, PPCI_LFD, tmpnum, dest, (int32_t)offsetof(Node, key.n));
 731  } else {
 732    if (!irt_ispri(kt)) {
 733      emit_ab(as, PPCI_CMPW, tmp2, key);
 734      emit_condbranch(as, PPCI_BC, CC_NE, l_next);
 735    }
 736    if (LJ_SOFTFP && ra_hasreg(tmpnum))
 737      emit_ab(as, PPCI_CMPW, tmp1, tmpnum);
 738    else
 739      emit_ai(as, PPCI_CMPWI, tmp1, irt_toitype(irkey->t));
 740    if (!irt_ispri(kt))
 741      emit_tai(as, PPCI_LWZ, tmp2, dest, (int32_t)offsetof(Node, key.gcr));
 742  }
 743  emit_tai(as, PPCI_LWZ, tmp1, dest, (int32_t)offsetof(Node, key.it));
 744  *l_loop = PPCI_BC | PPCF_Y | PPCF_CC(CC_NE) |
 745	    (((char *)as->mcp-(char *)l_loop) & 0xffffu);
 746
 747  /* Load main position relative to tab->node into dest. */
 748  khash = isk ? ir_khash(as, irkey) : 1;
 749  if (khash == 0) {
 750    emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
 751  } else {
 752    Reg tmphash = tmp1;
 753    if (isk)
 754      tmphash = ra_allock(as, khash, allow);
 755    emit_tab(as, PPCI_ADD, dest, dest, tmp1);
 756    emit_tai(as, PPCI_MULLI, tmp1, tmp1, sizeof(Node));
 757    emit_asb(as, PPCI_AND, tmp1, tmp2, tmphash);
 758    emit_tai(as, PPCI_LWZ, dest, tab, (int32_t)offsetof(GCtab, node));
 759    emit_tai(as, PPCI_LWZ, tmp2, tab, (int32_t)offsetof(GCtab, hmask));
 760    if (isk) {
 761      /* Nothing to do. */
 762    } else if (irt_isstr(kt)) {
 763      emit_tai(as, PPCI_LWZ, tmp1, key, (int32_t)offsetof(GCstr, sid));
 764    } else {  /* Must match with hash*() in lj_tab.c. */
 765      emit_tab(as, PPCI_SUBF, tmp1, tmp2, tmp1);
 766      emit_rotlwi(as, tmp2, tmp2, HASH_ROT3);
 767      emit_asb(as, PPCI_XOR, tmp1, tmp1, tmp2);
 768      emit_rotlwi(as, tmp1, tmp1, (HASH_ROT2+HASH_ROT1)&31);
 769      emit_tab(as, PPCI_SUBF, tmp2, dest, tmp2);
 770      if (LJ_SOFTFP ? (irkey[1].o == IR_HIOP) : irt_isnum(kt)) {
 771#if LJ_SOFTFP
 772	emit_asb(as, PPCI_XOR, tmp2, key, tmp1);
 773	emit_rotlwi(as, dest, tmp1, HASH_ROT1);
 774	emit_tab(as, PPCI_ADD, tmp1, tmpnum, tmpnum);
 775#else
 776	int32_t ofs = ra_spill(as, irkey);
 777	emit_asb(as, PPCI_XOR, tmp2, tmp2, tmp1);
 778	emit_rotlwi(as, dest, tmp1, HASH_ROT1);
 779	emit_tab(as, PPCI_ADD, tmp1, tmp1, tmp1);
 780	emit_tai(as, PPCI_LWZ, tmp2, RID_SP, ofs+4);
 781	emit_tai(as, PPCI_LWZ, tmp1, RID_SP, ofs);
 782#endif
 783      } else {
 784	emit_asb(as, PPCI_XOR, tmp2, key, tmp1);
 785	emit_rotlwi(as, dest, tmp1, HASH_ROT1);
 786	emit_tai(as, PPCI_ADDI, tmp1, tmp2, HASH_BIAS);
 787	emit_tai(as, PPCI_ADDIS, tmp2, key, (HASH_BIAS + 32768)>>16);
 788      }
 789    }
 790  }
 791}
 792
 793static void asm_hrefk(ASMState *as, IRIns *ir)
 794{
 795  IRIns *kslot = IR(ir->op2);
 796  IRIns *irkey = IR(kslot->op1);
 797  int32_t ofs = (int32_t)(kslot->op2 * sizeof(Node));
 798  int32_t kofs = ofs + (int32_t)offsetof(Node, key);
 799  Reg dest = (ra_used(ir)||ofs > 32736) ? ra_dest(as, ir, RSET_GPR) : RID_NONE;
 800  Reg node = ra_alloc1(as, ir->op1, RSET_GPR);
 801  Reg key = RID_NONE, type = RID_TMP, idx = node;
 802  RegSet allow = rset_exclude(RSET_GPR, node);
 803  lj_assertA(ofs % sizeof(Node) == 0, "unaligned HREFK slot");
 804  if (ofs > 32736) {
 805    idx = dest;
 806    rset_clear(allow, dest);
 807    kofs = (int32_t)offsetof(Node, key);
 808  } else if (ra_hasreg(dest)) {
 809    emit_tai(as, PPCI_ADDI, dest, node, ofs);
 810  }
 811  asm_guardcc(as, CC_NE);
 812  if (!irt_ispri(irkey->t)) {
 813    key = ra_scratch(as, allow);
 814    rset_clear(allow, key);
 815  }
 816  rset_clear(allow, type);
 817  if (irt_isnum(irkey->t)) {
 818    emit_cmpi(as, key, (int32_t)ir_knum(irkey)->u32.lo);
 819    asm_guardcc(as, CC_NE);
 820    emit_cmpi(as, type, (int32_t)ir_knum(irkey)->u32.hi);
 821  } else {
 822    if (ra_hasreg(key)) {
 823      emit_cmpi(as, key, irkey->i);  /* May use RID_TMP, i.e. type. */
 824      asm_guardcc(as, CC_NE);
 825    }
 826    emit_ai(as, PPCI_CMPWI, type, irt_toitype(irkey->t));
 827  }
 828  if (ra_hasreg(key)) emit_tai(as, PPCI_LWZ, key, idx, kofs+4);
 829  emit_tai(as, PPCI_LWZ, type, idx, kofs);
 830  if (ofs > 32736) {
 831    emit_tai(as, PPCI_ADDIS, dest, dest, (ofs + 32768) >> 16);
 832    emit_tai(as, PPCI_ADDI, dest, node, ofs);
 833  }
 834}
 835
 836static void asm_uref(ASMState *as, IRIns *ir)
 837{
 838  Reg dest = ra_dest(as, ir, RSET_GPR);
 839  int guarded = (irt_t(ir->t) & (IRT_GUARD|IRT_TYPE)) == (IRT_GUARD|IRT_PGC);
 840  if (irref_isk(ir->op1) && !guarded) {
 841    GCfunc *fn = ir_kfunc(IR(ir->op1));
 842    MRef *v = &gcref(fn->l.uvptr[(ir->op2 >> 8)])->uv.v;
 843    emit_lsptr(as, PPCI_LWZ, dest, v, RSET_GPR);
 844  } else {
 845    if (guarded) {
 846      asm_guardcc(as, ir->o == IR_UREFC ? CC_NE : CC_EQ);
 847      emit_ai(as, PPCI_CMPWI, RID_TMP, 1);
 848    }
 849    if (ir->o == IR_UREFC)
 850      emit_tai(as, PPCI_ADDI, dest, dest, (int32_t)offsetof(GCupval, tv));
 851    else
 852      emit_tai(as, PPCI_LWZ, dest, dest, (int32_t)offsetof(GCupval, v));
 853    if (guarded)
 854      emit_tai(as, PPCI_LBZ, RID_TMP, dest, (int32_t)offsetof(GCupval, closed));
 855    if (irref_isk(ir->op1)) {
 856      GCfunc *fn = ir_kfunc(IR(ir->op1));
 857      int32_t k = (int32_t)gcrefu(fn->l.uvptr[(ir->op2 >> 8)]);
 858      emit_loadi(as, dest, k);
 859    } else {
 860      emit_tai(as, PPCI_LWZ, dest, ra_alloc1(as, ir->op1, RSET_GPR),
 861	       (int32_t)offsetof(GCfuncL, uvptr) + 4*(int32_t)(ir->op2 >> 8));
 862    }
 863  }
 864}
 865
 866static void asm_fref(ASMState *as, IRIns *ir)
 867{
 868  UNUSED(as); UNUSED(ir);
 869  lj_assertA(!ra_used(ir), "unfused FREF");
 870}
 871
 872static void asm_strref(ASMState *as, IRIns *ir)
 873{
 874  Reg dest = ra_dest(as, ir, RSET_GPR);
 875  IRRef ref = ir->op2, refk = ir->op1;
 876  int32_t ofs = (int32_t)sizeof(GCstr);
 877  Reg r;
 878  if (irref_isk(ref)) {
 879    IRRef tmp = refk; refk = ref; ref = tmp;
 880  } else if (!irref_isk(refk)) {
 881    Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
 882    IRIns *irr = IR(ir->op2);
 883    if (ra_hasreg(irr->r)) {
 884      ra_noweak(as, irr->r);
 885      right = irr->r;
 886    } else if (mayfuse(as, irr->op2) &&
 887	       irr->o == IR_ADD && irref_isk(irr->op2) &&
 888	       checki16(ofs + IR(irr->op2)->i)) {
 889      ofs += IR(irr->op2)->i;
 890      right = ra_alloc1(as, irr->op1, rset_exclude(RSET_GPR, left));
 891    } else {
 892      right = ra_allocref(as, ir->op2, rset_exclude(RSET_GPR, left));
 893    }
 894    emit_tai(as, PPCI_ADDI, dest, dest, ofs);
 895    emit_tab(as, PPCI_ADD, dest, left, right);
 896    return;
 897  }
 898  r = ra_alloc1(as, ref, RSET_GPR);
 899  ofs += IR(refk)->i;
 900  if (checki16(ofs))
 901    emit_tai(as, PPCI_ADDI, dest, r, ofs);
 902  else
 903    emit_tab(as, PPCI_ADD, dest, r,
 904	     ra_allock(as, ofs, rset_exclude(RSET_GPR, r)));
 905}
 906
 907/* -- Loads and stores ---------------------------------------------------- */
 908
 909static PPCIns asm_fxloadins(ASMState *as, IRIns *ir)
 910{
 911  UNUSED(as);
 912  switch (irt_type(ir->t)) {
 913  case IRT_I8: return PPCI_LBZ;  /* Needs sign-extension. */
 914  case IRT_U8: return PPCI_LBZ;
 915  case IRT_I16: return PPCI_LHA;
 916  case IRT_U16: return PPCI_LHZ;
 917  case IRT_NUM: lj_assertA(!LJ_SOFTFP, "unsplit FP op"); return PPCI_LFD;
 918  case IRT_FLOAT: if (!LJ_SOFTFP) return PPCI_LFS;
 919  default: return PPCI_LWZ;
 920  }
 921}
 922
 923static PPCIns asm_fxstoreins(ASMState *as, IRIns *ir)
 924{
 925  UNUSED(as);
 926  switch (irt_type(ir->t)) {
 927  case IRT_I8: case IRT_U8: return PPCI_STB;
 928  case IRT_I16: case IRT_U16: return PPCI_STH;
 929  case IRT_NUM: lj_assertA(!LJ_SOFTFP, "unsplit FP op"); return PPCI_STFD;
 930  case IRT_FLOAT: if (!LJ_SOFTFP) return PPCI_STFS;
 931  default: return PPCI_STW;
 932  }
 933}
 934
 935static void asm_fload(ASMState *as, IRIns *ir)
 936{
 937  Reg dest = ra_dest(as, ir, RSET_GPR);
 938  PPCIns pi = asm_fxloadins(as, ir);
 939  Reg idx;
 940  int32_t ofs;
 941  if (ir->op1 == REF_NIL) {  /* FLOAD from GG_State with offset. */
 942    idx = RID_JGL;
 943    ofs = (ir->op2 << 2) - 32768 - GG_OFS(g);
 944  } else {
 945    idx = ra_alloc1(as, ir->op1, RSET_GPR);
 946    if (ir->op2 == IRFL_TAB_ARRAY) {
 947      ofs = asm_fuseabase(as, ir->op1);
 948      if (ofs) {  /* Turn the t->array load into an add for colocated arrays. */
 949	emit_tai(as, PPCI_ADDI, dest, idx, ofs);
 950	return;
 951      }
 952    }
 953    ofs = field_ofs[ir->op2];
 954  }
 955  lj_assertA(!irt_isi8(ir->t), "unsupported FLOAD I8");
 956  emit_tai(as, pi, dest, idx, ofs);
 957}
 958
 959static void asm_fstore(ASMState *as, IRIns *ir)
 960{
 961  if (ir->r != RID_SINK) {
 962    Reg src = ra_alloc1(as, ir->op2, RSET_GPR);
 963    IRIns *irf = IR(ir->op1);
 964    Reg idx = ra_alloc1(as, irf->op1, rset_exclude(RSET_GPR, src));
 965    int32_t ofs = field_ofs[irf->op2];
 966    PPCIns pi = asm_fxstoreins(as, ir);
 967    emit_tai(as, pi, src, idx, ofs);
 968  }
 969}
 970
 971static void asm_xload(ASMState *as, IRIns *ir)
 972{
 973  Reg dest = ra_dest(as, ir,
 974    (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
 975  lj_assertA(!(ir->op2 & IRXLOAD_UNALIGNED), "unaligned XLOAD");
 976  if (irt_isi8(ir->t))
 977    emit_as(as, PPCI_EXTSB, dest, dest);
 978  asm_fusexref(as, asm_fxloadins(as, ir), dest, ir->op1, RSET_GPR, 0);
 979}
 980
 981static void asm_xstore_(ASMState *as, IRIns *ir, int32_t ofs)
 982{
 983  IRIns *irb;
 984  if (ir->r == RID_SINK)
 985    return;
 986  if (ofs == 0 && mayfuse(as, ir->op2) && (irb = IR(ir->op2))->o == IR_BSWAP &&
 987      ra_noreg(irb->r) && (irt_isint(ir->t) || irt_isu32(ir->t))) {
 988    /* Fuse BSWAP with XSTORE to stwbrx. */
 989    Reg src = ra_alloc1(as, irb->op1, RSET_GPR);
 990    asm_fusexrefx(as, PPCI_STWBRX, src, ir->op1, rset_exclude(RSET_GPR, src));
 991  } else {
 992    Reg src = ra_alloc1(as, ir->op2,
 993      (!LJ_SOFTFP && irt_isfp(ir->t)) ? RSET_FPR : RSET_GPR);
 994    asm_fusexref(as, asm_fxstoreins(as, ir), src, ir->op1,
 995		 rset_exclude(RSET_GPR, src), ofs);
 996  }
 997}
 998
 999#define asm_xstore(as, ir)	asm_xstore_(as, ir, 0)
1000
1001static void asm_ahuvload(ASMState *as, IRIns *ir)
1002{
1003  IRType1 t = ir->t;
1004  Reg dest = RID_NONE, type = RID_TMP, tmp = RID_TMP, idx;
1005  RegSet allow = RSET_GPR;
1006  int32_t ofs = AHUREF_LSX;
1007  if (LJ_SOFTFP && (ir+1)->o == IR_HIOP) {
1008    t.irt = IRT_NUM;
1009    if (ra_used(ir+1)) {
1010      type = ra_dest(as, ir+1, allow);
1011      rset_clear(allow, type);
1012    }
1013    ofs = 0;
1014  }
1015  if (ra_used(ir)) {
1016    lj_assertA((LJ_SOFTFP ? 0 : irt_isnum(ir->t)) ||
1017	       irt_isint(ir->t) || irt_isaddr(ir->t),
1018	       "bad load type %d", irt_type(ir->t));
1019    if (LJ_SOFTFP || !irt_isnum(t)) ofs = 0;
1020    dest = ra_dest(as, ir, (!LJ_SOFTFP && irt_isnum(t)) ? RSET_FPR : allow);
1021    rset_clear(allow, dest);
1022  }
1023  idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
1024  if (ir->o == IR_VLOAD) {
1025    ofs = ofs != AHUREF_LSX ? ofs + 8 * ir->op2 :
1026	  ir->op2 ? 8 * ir->op2 : AHUREF_LSX;
1027  }
1028  if (irt_isnum(t)) {
1029    Reg tisnum = ra_allock(as, (int32_t)LJ_TISNUM, rset_exclude(allow, idx));
1030    asm_guardcc(as, CC_GE);
1031    emit_ab(as, PPCI_CMPLW, type, tisnum);
1032    if (ra_hasreg(dest)) {
1033      if (!LJ_SOFTFP && ofs == AHUREF_LSX) {
1034	tmp = ra_scratch(as, rset_exclude(rset_exclude(RSET_GPR,
1035						       (idx&255)), (idx>>8)));
1036	emit_fab(as, PPCI_LFDX, dest, (idx&255), tmp);
1037      } else {
1038	emit_fai(as, LJ_SOFTFP ? PPCI_LWZ : PPCI_LFD, dest, idx,
1039		 ofs+4*LJ_SOFTFP);
1040      }
1041    }
1042  } else {
1043    asm_guardcc(as, CC_NE);
1044    emit_ai(as, PPCI_CMPWI, type, irt_toitype(t));
1045    if (ra_hasreg(dest)) emit_tai(as, PPCI_LWZ, dest, idx, ofs+4);
1046  }
1047  if (ofs == AHUREF_LSX) {
1048    emit_tab(as, PPCI_LWZX, type, (idx&255), tmp);
1049    emit_slwi(as, tmp, (idx>>8), 3);
1050  } else {
1051    emit_tai(as, PPCI_LWZ, type, idx, ofs);
1052  }
1053}
1054
1055static void asm_ahustore(ASMState *as, IRIns *ir)
1056{
1057  RegSet allow = RSET_GPR;
1058  Reg idx, src = RID_NONE, type = RID_NONE;
1059  int32_t ofs = AHUREF_LSX;
1060  if (ir->r == RID_SINK)
1061    return;
1062  if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1063    src = ra_alloc1(as, ir->op2, RSET_FPR);
1064  } else {
1065    if (!irt_ispri(ir->t)) {
1066      src = ra_alloc1(as, ir->op2, allow);
1067      rset_clear(allow, src);
1068      ofs = 0;
1069    }
1070    if (LJ_SOFTFP && (ir+1)->o == IR_HIOP)
1071      type = ra_alloc1(as, (ir+1)->op2, allow);
1072    else
1073      type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
1074    rset_clear(allow, type);
1075  }
1076  idx = asm_fuseahuref(as, ir->op1, &ofs, allow);
1077  if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1078    if (ofs == AHUREF_LSX) {
1079      emit_fab(as, PPCI_STFDX, src, (idx&255), RID_TMP);
1080      emit_slwi(as, RID_TMP, (idx>>8), 3);
1081    } else {
1082      emit_fai(as, PPCI_STFD, src, idx, ofs);
1083    }
1084  } else {
1085    if (ra_hasreg(src))
1086      emit_tai(as, PPCI_STW, src, idx, ofs+4);
1087    if (ofs == AHUREF_LSX) {
1088      emit_tab(as, PPCI_STWX, type, (idx&255), RID_TMP);
1089      emit_slwi(as, RID_TMP, (idx>>8), 3);
1090    } else {
1091      emit_tai(as, PPCI_STW, type, idx, ofs);
1092    }
1093  }
1094}
1095
1096static void asm_sload(ASMState *as, IRIns *ir)
1097{
1098  int32_t ofs = 8*((int32_t)ir->op1-1) + ((ir->op2 & IRSLOAD_FRAME) ? 0 : 4);
1099  IRType1 t = ir->t;
1100  Reg dest = RID_NONE, type = RID_NONE, base;
1101  RegSet allow = RSET_GPR;
1102  int hiop = (LJ_SOFTFP && (ir+1)->o == IR_HIOP);
1103  if (hiop)
1104    t.irt = IRT_NUM;
1105  lj_assertA(!(ir->op2 & IRSLOAD_PARENT),
1106	     "bad parent SLOAD");  /* Handled by asm_head_side(). */
1107  lj_assertA(irt_isguard(ir->t) || !(ir->op2 & IRSLOAD_TYPECHECK),
1108	     "inconsistent SLOAD variant");
1109  lj_assertA(LJ_DUALNUM ||
1110	     !irt_isint(t) ||
1111	     (ir->op2 & (IRSLOAD_CONVERT|IRSLOAD_FRAME|IRSLOAD_KEYINDEX)),
1112	     "bad SLOAD type");
1113#if LJ_SOFTFP
1114  lj_assertA(!(ir->op2 & IRSLOAD_CONVERT),
1115	     "unsplit SLOAD convert");  /* Handled by LJ_SOFTFP SPLIT. */
1116  if (hiop && ra_used(ir+1)) {
1117    type = ra_dest(as, ir+1, allow);
1118    rset_clear(allow, type);
1119  }
1120#else
1121  if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t) && irt_isint(t)) {
1122    dest = ra_scratch(as, RSET_FPR);
1123    asm_tointg(as, ir, dest);
1124    t.irt = IRT_NUM;  /* Continue with a regular number type check. */
1125  } else
1126#endif
1127  if (ra_used(ir)) {
1128    lj_assertA(irt_isnum(t) || irt_isint(t) || irt_isaddr(t),
1129	       "bad SLOAD type %d", irt_type(ir->t));
1130    dest = ra_dest(as, ir, (!LJ_SOFTFP && irt_isnum(t)) ? RSET_FPR : allow);
1131    rset_clear(allow, dest);
1132    base = ra_alloc1(as, REF_BASE, allow);
1133    rset_clear(allow, base);
1134    if (!LJ_SOFTFP && (ir->op2 & IRSLOAD_CONVERT)) {
1135      if (irt_isint(t)) {
1136	emit_tai(as, PPCI_LWZ, dest, RID_SP, SPOFS_TMPLO);
1137	dest = ra_scratch(as, RSET_FPR);
1138	emit_fai(as, PPCI_STFD, dest, RID_SP, SPOFS_TMP);
1139	emit_fb(as, PPCI_FCTIWZ, dest, dest);
1140	t.irt = IRT_NUM;  /* Check for original type. */
1141      } else {
1142	Reg tmp = ra_scratch(as, allow);
1143	Reg hibias = ra_allock(as, 0x43300000, rset_clear(allow, tmp));
1144	Reg fbias = ra_scratch(as, rset_exclude(RSET_FPR, dest));
1145	emit_fab(as, PPCI_FSUB, dest, dest, fbias);
1146	emit_fai(as, PPCI_LFD, dest, RID_SP, SPOFS_TMP);
1147	emit_lsptr(as, PPCI_LFS, (fbias & 31),
1148		   (void *)&as->J->k32[LJ_K32_2P52_2P31],
1149		   rset_clear(allow, hibias));
1150	emit_tai(as, PPCI_STW, tmp, RID_SP, SPOFS_TMPLO);
1151	emit_tai(as, PPCI_STW, hibias, RID_SP, SPOFS_TMPHI);
1152	emit_asi(as, PPCI_XORIS, tmp, tmp, 0x8000);
1153	dest = tmp;
1154	t.irt = IRT_INT;  /* Check for original type. */
1155      }
1156    }
1157    goto dotypecheck;
1158  }
1159  base = ra_alloc1(as, REF_BASE, allow);
1160  rset_clear(allow, base);
1161dotypecheck:
1162  if (irt_isnum(t)) {
1163    if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1164      Reg tisnum = ra_allock(as, (int32_t)LJ_TISNUM, allow);
1165      asm_guardcc(as, CC_GE);
1166#if !LJ_SOFTFP
1167      type = RID_TMP;
1168#endif
1169      emit_ab(as, PPCI_CMPLW, type, tisnum);
1170    }
1171    if (ra_hasreg(dest)) emit_fai(as, LJ_SOFTFP ? PPCI_LWZ : PPCI_LFD, dest,
1172				  base, ofs-(LJ_SOFTFP?0:4));
1173  } else {
1174    if ((ir->op2 & IRSLOAD_TYPECHECK)) {
1175      asm_guardcc(as, CC_NE);
1176      if ((ir->op2 & IRSLOAD_KEYINDEX)) {
1177	emit_ai(as, PPCI_CMPWI, RID_TMP, (LJ_KEYINDEX & 0xffff));
1178	emit_asi(as, PPCI_XORIS, RID_TMP, RID_TMP, (LJ_KEYINDEX >> 16));
1179      } else {
1180	emit_ai(as, PPCI_CMPWI, RID_TMP, irt_toitype(t));
1181      }
1182      type = RID_TMP;
1183    }
1184    if (ra_hasreg(dest)) emit_tai(as, PPCI_LWZ, dest, base, ofs);
1185  }
1186  if (ra_hasreg(type)) emit_tai(as, PPCI_LWZ, type, base, ofs-4);
1187}
1188
1189/* -- Allocations --------------------------------------------------------- */
1190
1191#if LJ_HASFFI
1192static void asm_cnew(ASMState *as, IRIns *ir)
1193{
1194  CTState *cts = ctype_ctsG(J2G(as->J));
1195  CTypeID id = (CTypeID)IR(ir->op1)->i;
1196  CTSize sz;
1197  CTInfo info = lj_ctype_info(cts, id, &sz);
1198  const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_mem_newgco];
1199  IRRef args[4];
1200  RegSet drop = RSET_SCRATCH;
1201  lj_assertA(sz != CTSIZE_INVALID || (ir->o == IR_CNEW && ir->op2 != REF_NIL),
1202	     "bad CNEW/CNEWI operands");
1203
1204  as->gcsteps++;
1205  if (ra_hasreg(ir->r))
1206    rset_clear(drop, ir->r);  /* Dest reg handled below. */
1207  ra_evictset(as, drop);
1208  if (ra_used(ir))
1209    ra_destreg(as, ir, RID_RET);  /* GCcdata * */
1210
1211  /* Initialize immutable cdata object. */
1212  if (ir->o == IR_CNEWI) {
1213    RegSet allow = (RSET_GPR & ~RSET_SCRATCH);
1214    int32_t ofs = sizeof(GCcdata);
1215    lj_assertA(sz == 4 || sz == 8, "bad CNEWI size %d", sz);
1216    if (sz == 8) {
1217      ofs += 4;
1218      lj_assertA((ir+1)->o == IR_HIOP, "expected HIOP for CNEWI");
1219    }
1220    for (;;) {
1221      Reg r = ra_alloc1(as, ir->op2, allow);
1222      emit_tai(as, PPCI_STW, r, RID_RET, ofs);
1223      rset_clear(allow, r);
1224      if (ofs == sizeof(GCcdata)) break;
1225      ofs -= 4; ir++;
1226    }
1227  } else if (ir->op2 != REF_NIL) {  /* Create VLA/VLS/aligned cdata. */
1228    ci = &lj_ir_callinfo[IRCALL_lj_cdata_newv];
1229    args[0] = ASMREF_L;     /* lua_State *L */
1230    args[1] = ir->op1;      /* CTypeID id   */
1231    args[2] = ir->op2;      /* CTSize sz    */
1232    args[3] = ASMREF_TMP1;  /* CTSize align */
1233    asm_gencall(as, ci, args);
1234    emit_loadi(as, ra_releasetmp(as, ASMREF_TMP1), (int32_t)ctype_align(info));
1235    return;
1236  }
1237
1238  /* Initialize gct and ctypeid. lj_mem_newgco() already sets marked. */
1239  emit_tai(as, PPCI_STB, RID_RET+1, RID_RET, offsetof(GCcdata, gct));
1240  emit_tai(as, PPCI_STH, RID_TMP, RID_RET, offsetof(GCcdata, ctypeid));
1241  emit_ti(as, PPCI_LI, RID_RET+1, ~LJ_TCDATA);
1242  emit_ti(as, PPCI_LI, RID_TMP, id);  /* Lower 16 bit used. Sign-ext ok. */
1243  args[0] = ASMREF_L;     /* lua_State *L */
1244  args[1] = ASMREF_TMP1;  /* MSize size   */
1245  asm_gencall(as, ci, args);
1246  ra_allockreg(as, (int32_t)(sz+sizeof(GCcdata)),
1247	       ra_releasetmp(as, ASMREF_TMP1));
1248}
1249#endif
1250
1251/* -- Write barriers ------------------------------------------------------ */
1252
1253static void asm_tbar(ASMState *as, IRIns *ir)
1254{
1255  Reg tab = ra_alloc1(as, ir->op1, RSET_GPR);
1256  Reg mark = ra_scratch(as, rset_exclude(RSET_GPR, tab));
1257  Reg link = RID_TMP;
1258  MCLabel l_end = emit_label(as);
1259  emit_tai(as, PPCI_STW, link, tab, (int32_t)offsetof(GCtab, gclist));
1260  emit_tai(as, PPCI_STB, mark, tab, (int32_t)offsetof(GCtab, marked));
1261  emit_setgl(as, tab, gc.grayagain);
1262  lj_assertA(LJ_GC_BLACK == 0x04, "bad LJ_GC_BLACK");
1263  emit_rot(as, PPCI_RLWINM, mark, mark, 0, 30, 28);  /* Clear black bit. */
1264  emit_getgl(as, link, gc.grayagain);
1265  emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
1266  emit_asi(as, PPCI_ANDIDOT, RID_TMP, mark, LJ_GC_BLACK);
1267  emit_tai(as, PPCI_LBZ, mark, tab, (int32_t)offsetof(GCtab, marked));
1268}
1269
1270static void asm_obar(ASMState *as, IRIns *ir)
1271{
1272  const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_barrieruv];
1273  IRRef args[2];
1274  MCLabel l_end;
1275  Reg obj, val, tmp;
1276  /* No need for other object barriers (yet). */
1277  lj_assertA(IR(ir->op1)->o == IR_UREFC, "bad OBAR type");
1278  ra_evictset(as, RSET_SCRATCH);
1279  l_end = emit_label(as);
1280  args[0] = ASMREF_TMP1;  /* global_State *g */
1281  args[1] = ir->op1;      /* TValue *tv      */
1282  asm_gencall(as, ci, args);
1283  emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
1284  obj = IR(ir->op1)->r;
1285  tmp = ra_scratch(as, rset_exclude(RSET_GPR, obj));
1286  emit_condbranch(as, PPCI_BC|PPCF_Y, CC_EQ, l_end);
1287  emit_asi(as, PPCI_ANDIDOT, tmp, tmp, LJ_GC_BLACK);
1288  emit_condbranch(as, PPCI_BC, CC_EQ, l_end);
1289  emit_asi(as, PPCI_ANDIDOT, RID_TMP, RID_TMP, LJ_GC_WHITES);
1290  val = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, obj));
1291  emit_tai(as, PPCI_LBZ, tmp, obj,
1292	   (int32_t)offsetof(GCupval, marked)-(int32_t)offsetof(GCupval, tv));
1293  emit_tai(as, PPCI_LBZ, RID_TMP, val, (int32_t)offsetof(GChead, marked));
1294}
1295
1296/* -- Arithmetic and logic operations ------------------------------------- */
1297
1298#if !LJ_SOFTFP
1299static void asm_fparith(ASMState *as, IRIns *ir, PPCIns pi)
1300{
1301  Reg dest = ra_dest(as, ir, RSET_FPR);
1302  Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1303  right = (left >> 8); left &= 255;
1304  if (pi == PPCI_FMUL)
1305    emit_fac(as, pi, dest, left, right);
1306  else
1307    emit_fab(as, pi, dest, left, right);
1308}
1309
1310static void asm_fpunary(ASMState *as, IRIns *ir, PPCIns pi)
1311{
1312  Reg dest = ra_dest(as, ir, RSET_FPR);
1313  Reg left = ra_hintalloc(as, ir->op1, dest, RSET_FPR);
1314  emit_fb(as, pi, dest, left);
1315}
1316
1317static void asm_fpmath(ASMState *as, IRIns *ir)
1318{
1319  if (ir->op2 == IRFPM_SQRT && (as->flags & JIT_F_SQRT))
1320    asm_fpunary(as, ir, PPCI_FSQRT);
1321  else
1322    asm_callid(as, ir, IRCALL_lj_vm_floor + ir->op2);
1323}
1324#endif
1325
1326static void asm_add(ASMState *as, IRIns *ir)
1327{
1328#if !LJ_SOFTFP
1329  if (irt_isnum(ir->t)) {
1330    if (!asm_fusemadd(as, ir, PPCI_FMADD, PPCI_FMADD))
1331      asm_fparith(as, ir, PPCI_FADD);
1332  } else
1333#endif
1334  {
1335    Reg dest = ra_dest(as, ir, RSET_GPR);
1336    Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1337    PPCIns pi;
1338    if (irref_isk(ir->op2)) {
1339      int32_t k = IR(ir->op2)->i;
1340      if (checki16(k)) {
1341	pi = PPCI_ADDI;
1342	/* May fail due to spills/restores above, but simplifies the logic. */
1343	if (as->flagmcp == as->mcp) {
1344	  as->flagmcp = NULL;
1345	  as->mcp++;
1346	  pi = PPCI_ADDICDOT;
1347	}
1348	emit_tai(as, pi, dest, left, k);
1349	return;
1350      } else if ((k & 0xffff) == 0) {
1351	emit_tai(as, PPCI_ADDIS, dest, left, (k >> 16));
1352	return;
1353      } else if (!as->sectref) {
1354	emit_tai(as, PPCI_ADDIS, dest, dest, (k + 32768) >> 16);
1355	emit_tai(as, PPCI_ADDI, dest, left, k);
1356	return;
1357      }
1358    }
1359    pi = PPCI_ADD;
1360    /* May fail due to spills/restores above, but simplifies the logic. */
1361    if (as->flagmcp == as->mcp) {
1362      as->flagmcp = NULL;
1363      as->mcp++;
1364      pi |= PPCF_DOT;
1365    }
1366    right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1367    emit_tab(as, pi, dest, left, right);
1368  }
1369}
1370
1371static void asm_sub(ASMState *as, IRIns *ir)
1372{
1373#if !LJ_SOFTFP
1374  if (irt_isnum(ir->t)) {
1375    if (!asm_fusemadd(as, ir, PPCI_FMSUB, PPCI_FNMSUB))
1376      asm_fparith(as, ir, PPCI_FSUB);
1377  } else
1378#endif
1379  {
1380    PPCIns pi = PPCI_SUBF;
1381    Reg dest = ra_dest(as, ir, RSET_GPR);
1382    Reg left, right;
1383    if (irref_isk(ir->op1)) {
1384      int32_t k = IR(ir->op1)->i;
1385      if (checki16(k)) {
1386	right = ra_alloc1(as, ir->op2, RSET_GPR);
1387	emit_tai(as, PPCI_SUBFIC, dest, right, k);
1388	return;
1389      }
1390    }
1391    /* May fail due to spills/restores above, but simplifies the logic. */
1392    if (as->flagmcp == as->mcp) {
1393      as->flagmcp = NULL;
1394      as->mcp++;
1395      pi |= PPCF_DOT;
1396    }
1397    left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1398    right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1399    emit_tab(as, pi, dest, right, left);  /* Subtract right _from_ left. */
1400  }
1401}
1402
1403static void asm_mul(ASMState *as, IRIns *ir)
1404{
1405#if !LJ_SOFTFP
1406  if (irt_isnum(ir->t)) {
1407    asm_fparith(as, ir, PPCI_FMUL);
1408  } else
1409#endif
1410  {
1411    PPCIns pi = PPCI_MULLW;
1412    Reg dest = ra_dest(as, ir, RSET_GPR);
1413    Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1414    if (irref_isk(ir->op2)) {
1415      int32_t k = IR(ir->op2)->i;
1416      if (checki16(k)) {
1417	emit_tai(as, PPCI_MULLI, dest, left, k);
1418	return;
1419      }
1420    }
1421    /* May fail due to spills/restores above, but simplifies the logic. */
1422    if (as->flagmcp == as->mcp) {
1423      as->flagmcp = NULL;
1424      as->mcp++;
1425      pi |= PPCF_DOT;
1426    }
1427    right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1428    emit_tab(as, pi, dest, left, right);
1429  }
1430}
1431
1432#define asm_fpdiv(as, ir)	asm_fparith(as, ir, PPCI_FDIV)
1433
1434static void asm_neg(ASMState *as, IRIns *ir)
1435{
1436#if !LJ_SOFTFP
1437  if (irt_isnum(ir->t)) {
1438    asm_fpunary(as, ir, PPCI_FNEG);
1439  } else
1440#endif
1441  {
1442    Reg dest, left;
1443    PPCIns pi = PPCI_NEG;
1444    if (as->flagmcp == as->mcp) {
1445      as->flagmcp = NULL;
1446      as->mcp++;
1447      pi |= PPCF_DOT;
1448    }
1449    dest = ra_dest(as, ir, RSET_GPR);
1450    left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1451    emit_tab(as, pi, dest, left, 0);
1452  }
1453}
1454
1455#define asm_abs(as, ir)		asm_fpunary(as, ir, PPCI_FABS)
1456
1457static void asm_arithov(ASMState *as, IRIns *ir, PPCIns pi)
1458{
1459  Reg dest, left, right;
1460  if (as->flagmcp == as->mcp) {
1461    as->flagmcp = NULL;
1462    as->mcp++;
1463  }
1464  asm_guardcc(as, CC_SO);
1465  dest = ra_dest(as, ir, RSET_GPR);
1466  left = ra_alloc2(as, ir, RSET_GPR);
1467  right = (left >> 8); left &= 255;
1468  if (pi == PPCI_SUBFO) { Reg tmp = left; left = right; right = tmp; }
1469  emit_tab(as, pi|PPCF_DOT, dest, left, right);
1470}
1471
1472#define asm_addov(as, ir)	asm_arithov(as, ir, PPCI_ADDO)
1473#define asm_subov(as, ir)	asm_arithov(as, ir, PPCI_SUBFO)
1474#define asm_mulov(as, ir)	asm_arithov(as, ir, PPCI_MULLWO)
1475
1476#if LJ_HASFFI
1477static void asm_add64(ASMState *as, IRIns *ir)
1478{
1479  Reg dest = ra_dest(as, ir, RSET_GPR);
1480  Reg right, left = ra_alloc1(as, ir->op1, RSET_GPR);
1481  PPCIns pi = PPCI_ADDE;
1482  if (irref_isk(ir->op2)) {
1483    int32_t k = IR(ir->op2)->i;
1484    if (k == 0)
1485      pi = PPCI_ADDZE;
1486    else if (k == -1)
1487      pi = PPCI_ADDME;
1488    else
1489      goto needright;
1490    right = 0;
1491  } else {
1492  needright:
1493    right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1494  }
1495  emit_tab(as, pi, dest, left, right);
1496  ir--;
1497  dest = ra_dest(as, ir, RSET_GPR);
1498  left = ra_alloc1(as, ir->op1, RSET_GPR);
1499  if (irref_isk(ir->op2)) {
1500    int32_t k = IR(ir->op2)->i;
1501    if (checki16(k)) {
1502      emit_tai(as, PPCI_ADDIC, dest, left, k);
1503      return;
1504    }
1505  }
1506  right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1507  emit_tab(as, PPCI_ADDC, dest, left, right);
1508}
1509
1510static void asm_sub64(ASMState *as, IRIns *ir)
1511{
1512  Reg dest = ra_dest(as, ir, RSET_GPR);
1513  Reg left, right = ra_alloc1(as, ir->op2, RSET_GPR);
1514  PPCIns pi = PPCI_SUBFE;
1515  if (irref_isk(ir->op1)) {
1516    int32_t k = IR(ir->op1)->i;
1517    if (k == 0)
1518      pi = PPCI_SUBFZE;
1519    else if (k == -1)
1520      pi = PPCI_SUBFME;
1521    else
1522      goto needleft;
1523    left = 0;
1524  } else {
1525  needleft:
1526    left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, right));
1527  }
1528  emit_tab(as, pi, dest, right, left);  /* Subtract right _from_ left. */
1529  ir--;
1530  dest = ra_dest(as, ir, RSET_GPR);
1531  right = ra_alloc1(as, ir->op2, RSET_GPR);
1532  if (irref_isk(ir->op1)) {
1533    int32_t k = IR(ir->op1)->i;
1534    if (checki16(k)) {
1535      emit_tai(as, PPCI_SUBFIC, dest, right, k);
1536      return;
1537    }
1538  }
1539  left = ra_alloc1(as, ir->op1, rset_exclude(RSET_GPR, right));
1540  emit_tab(as, PPCI_SUBFC, dest, right, left);
1541}
1542
1543static void asm_neg64(ASMState *as, IRIns *ir)
1544{
1545  Reg dest = ra_dest(as, ir, RSET_GPR);
1546  Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1547  emit_tab(as, PPCI_SUBFZE, dest, left, 0);
1548  ir--;
1549  dest = ra_dest(as, ir, RSET_GPR);
1550  left = ra_alloc1(as, ir->op1, RSET_GPR);
1551  emit_tai(as, PPCI_SUBFIC, dest, left, 0);
1552}
1553#endif
1554
1555static void asm_bnot(ASMState *as, IRIns *ir)
1556{
1557  Reg dest, left, right;
1558  PPCIns pi = PPCI_NOR;
1559  if (as->flagmcp == as->mcp) {
1560    as->flagmcp = NULL;
1561    as->mcp++;
1562    pi |= PPCF_DOT;
1563  }
1564  dest = ra_dest(as, ir, RSET_GPR);
1565  if (mayfuse(as, ir->op1)) {
1566    IRIns *irl = IR(ir->op1);
1567    if (irl->o == IR_BAND)
1568      pi ^= (PPCI_NOR ^ PPCI_NAND);
1569    else if (irl->o == IR_BXOR)
1570      pi ^= (PPCI_NOR ^ PPCI_EQV);
1571    else if (irl->o != IR_BOR)
1572      goto nofuse;
1573    left = ra_hintalloc(as, irl->op1, dest, RSET_GPR);
1574    right = ra_alloc1(as, irl->op2, rset_exclude(RSET_GPR, left));
1575  } else {
1576nofuse:
1577    left = right = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1578  }
1579  emit_asb(as, pi, dest, left, right);
1580}
1581
1582static void asm_bswap(ASMState *as, IRIns *ir)
1583{
1584  Reg dest = ra_dest(as, ir, RSET_GPR);
1585  IRIns *irx;
1586  if (mayfuse(as, ir->op1) && (irx = IR(ir->op1))->o == IR_XLOAD &&
1587      ra_noreg(irx->r) && (irt_isint(irx->t) || irt_isu32(irx->t))) {
1588    /* Fuse BSWAP with XLOAD to lwbrx. */
1589    asm_fusexrefx(as, PPCI_LWBRX, dest, irx->op1, RSET_GPR);
1590  } else {
1591    Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
1592    Reg tmp = dest;
1593    if (tmp == left) {
1594      tmp = RID_TMP;
1595      emit_mr(as, dest, RID_TMP);
1596    }
1597    emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 16, 23);
1598    emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 0, 7);
1599    emit_rotlwi(as, tmp, left, 8);
1600  }
1601}
1602
1603/* Fuse BAND with contiguous bitmask and a shift to rlwinm. */
1604static void asm_fuseandsh(ASMState *as, PPCIns pi, int32_t mask, IRRef ref)
1605{
1606  IRIns *ir;
1607  Reg left;
1608  if (mayfuse(as, ref) && (ir = IR(ref), ra_noreg(ir->r)) &&
1609      irref_isk(ir->op2) && ir->o >= IR_BSHL && ir->o <= IR_BROR) {
1610    int32_t sh = (IR(ir->op2)->i & 31);
1611    switch (ir->o) {
1612    case IR_BSHL:
1613      if ((mask & ((1u<<sh)-1))) goto nofuse;
1614      break;
1615    case IR_BSHR:
1616      if ((mask & ~((~0u)>>sh))) goto nofuse;
1617      sh = ((32-sh)&31);
1618      break;
1619    case IR_BROL:
1620      break;
1621    default:
1622      goto nofuse;
1623    }
1624    left = ra_alloc1(as, ir->op1, RSET_GPR);
1625    *--as->mcp = pi | PPCF_T(left) | PPCF_B(sh);
1626    return;
1627  }
1628nofuse:
1629  left = ra_alloc1(as, ref, RSET_GPR);
1630  *--as->mcp = pi | PPCF_T(left);
1631}
1632
1633static void asm_band(ASMState *as, IRIns *ir)
1634{
1635  Reg dest, left, right;
1636  IRRef lref = ir->op1;
1637  PPCIns dot = 0;
1638  IRRef op2;
1639  if (as->flagmcp == as->mcp) {
1640    as->flagmcp = NULL;
1641    as->mcp++;
1642    dot = PPCF_DOT;
1643  }
1644  dest = ra_dest(as, ir, RSET_GPR);
1645  if (irref_isk(ir->op2)) {
1646    int32_t k = IR(ir->op2)->i;
1647    if (k) {
1648      /* First check for a contiguous bitmask as used by rlwinm. */
1649      uint32_t s1 = lj_ffs((uint32_t)k);
1650      uint32_t k1 = ((uint32_t)k >> s1);
1651      if ((k1 & (k1+1)) == 0) {
1652	asm_fuseandsh(as, PPCI_RLWINM|dot | PPCF_A(dest) |
1653			  PPCF_MB(31-lj_fls((uint32_t)k)) | PPCF_ME(31-s1),
1654			  k, lref);
1655	return;
1656      }
1657      if (~(uint32_t)k) {
1658	uint32_t s2 = lj_ffs(~(uint32_t)k);
1659	uint32_t k2 = (~(uint32_t)k >> s2);
1660	if ((k2 & (k2+1)) == 0) {
1661	  asm_fuseandsh(as, PPCI_RLWINM|dot | PPCF_A(dest) |
1662			    PPCF_MB(32-s2) | PPCF_ME(30-lj_fls(~(uint32_t)k)),
1663			    k, lref);
1664	  return;
1665	}
1666      }
1667    }
1668    if (checku16(k)) {
1669      left = ra_alloc1(as, lref, RSET_GPR);
1670      emit_asi(as, PPCI_ANDIDOT, dest, left, k);
1671      return;
1672    } else if ((k & 0xffff) == 0) {
1673      left = ra_alloc1(as, lref, RSET_GPR);
1674      emit_asi(as, PPCI_ANDISDOT, dest, left, (k >> 16));
1675      return;
1676    }
1677  }
1678  op2 = ir->op2;
1679  if (mayfuse(as, op2) && IR(op2)->o == IR_BNOT && ra_noreg(IR(op2)->r)) {
1680    dot ^= (PPCI_AND ^ PPCI_ANDC);
1681    op2 = IR(op2)->op1;
1682  }
1683  left = ra_hintalloc(as, lref, dest, RSET_GPR);
1684  right = ra_alloc1(as, op2, rset_exclude(RSET_GPR, left));
1685  emit_asb(as, PPCI_AND ^ dot, dest, left, right);
1686}
1687
1688static void asm_bitop(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
1689{
1690  Reg dest = ra_dest(as, ir, RSET_GPR);
1691  Reg right, left = ra_hintalloc(as, ir->op1, dest, RSET_GPR);
1692  if (irref_isk(ir->op2)) {
1693    int32_t k = IR(ir->op2)->i;
1694    Reg tmp = left;
1695    if ((checku16(k) || (k & 0xffff) == 0) || (tmp = dest, !as->sectref)) {
1696      if (!checku16(k)) {
1697	emit_asi(as, pik ^ (PPCI_ORI ^ PPCI_ORIS), dest, tmp, (k >> 16));
1698	if ((k & 0xffff) == 0) return;
1699      }
1700      emit_asi(as, pik, dest, left, k);
1701      return;
1702    }
1703  }
1704  /* May fail due to spills/restores above, but simplifies the logic. */
1705  if (as->flagmcp == as->mcp) {
1706    as->flagmcp = NULL;
1707    as->mcp++;
1708    pi |= PPCF_DOT;
1709  }
1710  right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1711  emit_asb(as, pi, dest, left, right);
1712}
1713
1714#define asm_bor(as, ir)		asm_bitop(as, ir, PPCI_OR, PPCI_ORI)
1715#define asm_bxor(as, ir)	asm_bitop(as, ir, PPCI_XOR, PPCI_XORI)
1716
1717static void asm_bitshift(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
1718{
1719  Reg dest, left;
1720  Reg dot = 0;
1721  if (as->flagmcp == as->mcp) {
1722    as->flagmcp = NULL;
1723    as->mcp++;
1724    dot = PPCF_DOT;
1725  }
1726  dest = ra_dest(as, ir, RSET_GPR);
1727  left = ra_alloc1(as, ir->op1, RSET_GPR);
1728  if (irref_isk(ir->op2)) {  /* Constant shifts. */
1729    int32_t shift = (IR(ir->op2)->i & 31);
1730    if (pik == 0)  /* SLWI */
1731      emit_rot(as, PPCI_RLWINM|dot, dest, left, shift, 0, 31-shift);
1732    else if (pik == 1)  /* SRWI */
1733      emit_rot(as, PPCI_RLWINM|dot, dest, left, (32-shift)&31, shift, 31);
1734    else
1735      emit_asb(as, pik|dot, dest, left, shift);
1736  } else {
1737    Reg right = ra_alloc1(as, ir->op2, rset_exclude(RSET_GPR, left));
1738    emit_asb(as, pi|dot, dest, left, right);
1739  }
1740}
1741
1742#define asm_bshl(as, ir)	asm_bitshift(as, ir, PPCI_SLW, 0)
1743#define asm_bshr(as, ir)	asm_bitshift(as, ir, PPCI_SRW, 1)
1744#define asm_bsar(as, ir)	asm_bitshift(as, ir, PPCI_SRAW, PPCI_SRAWI)
1745#define asm_brol(as, ir) \
1746  asm_bitshift(as, ir, PPCI_RLWNM|PPCF_MB(0)|PPCF_ME(31), \
1747		       PPCI_RLWINM|PPCF_MB(0)|PPCF_ME(31))
1748#define asm_bror(as, ir)	lj_assertA(0, "unexpected BROR")
1749
1750#if LJ_SOFTFP
1751static void asm_sfpmin_max(ASMState *as, IRIns *ir)
1752{
1753  CCallInfo ci = lj_ir_callinfo[IRCALL_softfp_cmp];
1754  IRRef args[4];
1755  MCLabel l_right, l_end;
1756  Reg desthi = ra_dest(as, ir, RSET_GPR), destlo = ra_dest(as, ir+1, RSET_GPR);
1757  Reg righthi, lefthi = ra_alloc2(as, ir, RSET_GPR);
1758  Reg rightlo, leftlo = ra_alloc2(as, ir+1, RSET_GPR);
1759  PPCCC cond = (IROp)ir->o == IR_MIN ? CC_EQ : CC_NE;
1760  righthi = (lefthi >> 8); lefthi &= 255;
1761  rightlo = (leftlo >> 8); leftlo &= 255;
1762  args[0^LJ_BE] = ir->op1; args[1^LJ_BE] = (ir+1)->op1;
1763  args[2^LJ_BE] = ir->op2; args[3^LJ_BE] = (ir+1)->op2;
1764  l_end = emit_label(as);
1765  if (desthi != righthi) emit_mr(as, desthi, righthi);
1766  if (destlo != rightlo) emit_mr(as, destlo, rightlo);
1767  l_right = emit_label(as);
1768  if (l_end != l_right) emit_jmp(as, l_end);
1769  if (desthi != lefthi) emit_mr(as, desthi, lefthi);
1770  if (destlo != leftlo) emit_mr(as, destlo, leftlo);
1771  if (l_right == as->mcp+1) {
1772    cond ^= 4; l_right = l_end; ++as->mcp;
1773  }
1774  emit_condbranch(as, PPCI_BC, cond, l_right);
1775  ra_evictset(as, RSET_SCRATCH);
1776  emit_cmpi(as, RID_RET, 1);
1777  asm_gencall(as, &ci, args);
1778}
1779#endif
1780
1781static void asm_min_max(ASMState *as, IRIns *ir, int ismax)
1782{
1783  if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1784    Reg dest = ra_dest(as, ir, RSET_FPR);
1785    Reg tmp = dest;
1786    Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1787    right = (left >> 8); left &= 255;
1788    if (tmp == left || tmp == right)
1789      tmp = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_FPR,
1790					dest), left), right));
1791    emit_facb(as, PPCI_FSEL, dest, tmp, left, right);
1792    emit_fab(as, PPCI_FSUB, tmp, ismax ? left : right, ismax ? right : left);
1793  } else {
1794    Reg dest = ra_dest(as, ir, RSET_GPR);
1795    Reg tmp1 = RID_TMP, tmp2 = dest;
1796    Reg right, left = ra_alloc2(as, ir, RSET_GPR);
1797    right = (left >> 8); left &= 255;
1798    if (tmp2 == left || tmp2 == right)
1799      tmp2 = ra_scratch(as, rset_exclude(rset_exclude(rset_exclude(RSET_GPR,
1800					 dest), left), right));
1801    emit_tab(as, PPCI_ADD, dest, tmp2, right);
1802    emit_asb(as, ismax ? PPCI_ANDC : PPCI_AND, tmp2, tmp2, tmp1);
1803    emit_tab(as, PPCI_SUBFE, tmp1, tmp1, tmp1);
1804    emit_tab(as, PPCI_SUBFC, tmp2, tmp2, tmp1);
1805    emit_asi(as, PPCI_XORIS, tmp2, right, 0x8000);
1806    emit_asi(as, PPCI_XORIS, tmp1, left, 0x8000);
1807  }
1808}
1809
1810#define asm_min(as, ir)		asm_min_max(as, ir, 0)
1811#define asm_max(as, ir)		asm_min_max(as, ir, 1)
1812
1813/* -- Comparisons --------------------------------------------------------- */
1814
1815#define CC_UNSIGNED	0x08	/* Unsigned integer comparison. */
1816#define CC_TWO		0x80	/* Check two flags for FP comparison. */
1817
1818/* Map of comparisons to flags. ORDER IR. */
1819static const uint8_t asm_compmap[IR_ABC+1] = {
1820  /* op     int cc                 FP cc */
1821  /* LT  */ CC_GE               + (CC_GE<<4),
1822  /* GE  */ CC_LT               + (CC_LE<<4) + CC_TWO,
1823  /* LE  */ CC_GT               + (CC_GE<<4) + CC_TWO,
1824  /* GT  */ CC_LE               + (CC_LE<<4),
1825  /* ULT */ CC_GE + CC_UNSIGNED + (CC_GT<<4) + CC_TWO,
1826  /* UGE */ CC_LT + CC_UNSIGNED + (CC_LT<<4),
1827  /* ULE */ CC_GT + CC_UNSIGNED + (CC_GT<<4),
1828  /* UGT */ CC_LE + CC_UNSIGNED + (CC_LT<<4) + CC_TWO,
1829  /* EQ  */ CC_NE               + (CC_NE<<4),
1830  /* NE  */ CC_EQ               + (CC_EQ<<4),
1831  /* ABC */ CC_LE + CC_UNSIGNED + (CC_LT<<4) + CC_TWO  /* Same as UGT. */
1832};
1833
1834static void asm_intcomp_(ASMState *as, IRRef lref, IRRef rref, Reg cr, PPCCC cc)
1835{
1836  Reg right, left = ra_alloc1(as, lref, RSET_GPR);
1837  if (irref_isk(rref)) {
1838    int32_t k = IR(rref)->i;
1839    if ((cc & CC_UNSIGNED) == 0) {  /* Signed comparison with constant. */
1840      if (checki16(k)) {
1841	emit_tai(as, PPCI_CMPWI, cr, left, k);
1842	/* Signed comparison with zero and referencing previous ins? */
1843	if (k == 0 && lref == as->curins-1)
1844	  as->flagmcp = as->mcp;  /* Allow elimination of the compare. */
1845	return;
1846      } else if ((cc & 3) == (CC_EQ & 3)) {  /* Use CMPLWI for EQ or NE. */
1847	if (checku16(k)) {
1848	  emit_tai(as, PPCI_CMPLWI, cr, left, k);
1849	  return;
1850	} else if (!as->sectref && ra_noreg(IR(rref)->r)) {
1851	  emit_tai(as, PPCI_CMPLWI, cr, RID_TMP, k);
1852	  emit_asi(as, PPCI_XORIS, RID_TMP, left, (k >> 16));
1853	  return;
1854	}
1855      }
1856    } else {  /* Unsigned comparison with constant. */
1857      if (checku16(k)) {
1858	emit_tai(as, PPCI_CMPLWI, cr, left, k);
1859	return;
1860      }
1861    }
1862  }
1863  right = ra_alloc1(as, rref, rset_exclude(RSET_GPR, left));
1864  emit_tab(as, (cc & CC_UNSIGNED) ? PPCI_CMPLW : PPCI_CMPW, cr, left, right);
1865}
1866
1867static void asm_comp(ASMState *as, IRIns *ir)
1868{
1869  PPCCC cc = asm_compmap[ir->o];
1870  if (!LJ_SOFTFP && irt_isnum(ir->t)) {
1871    Reg right, left = ra_alloc2(as, ir, RSET_FPR);
1872    right = (left >> 8); left &= 255;
1873    asm_guardcc(as, (cc >> 4));
1874    if ((cc & CC_TWO))
1875      emit_tab(as, PPCI_CROR, ((cc>>4)&3), ((cc>>4)&3), (CC_EQ&3));
1876    emit_fab(as, PPCI_FCMPU, 0, left, right);
1877  } else {
1878    IRRef lref = ir->op1, rref = ir->op2;
1879    if (irref_isk(lref) && !irref_isk(rref)) {
1880      /* Swap constants to the right (only for ABC). */
1881      IRRef tmp = lref; lref = rref; rref = tmp;
1882      if ((cc & 2) == 0) cc ^= 1;  /* LT <-> GT, LE <-> GE */
1883    }
1884    asm_guardcc(as, cc);
1885    asm_intcomp_(as, lref, rref, 0, cc);
1886  }
1887}
1888
1889#define asm_equal(as, ir)	asm_comp(as, ir)
1890
1891#if LJ_SOFTFP
1892/* SFP comparisons. */
1893static void asm_sfpcomp(ASMState *as, IRIns *ir)
1894{
1895  const CCallInfo *ci = &lj_ir_callinfo[IRCALL_softfp_cmp];
1896  RegSet drop = RSET_SCRATCH;
1897  Reg r;
1898  IRRef args[4];
1899  args[0^LJ_BE] = ir->op1; args[1^LJ_BE] = (ir+1)->op1;
1900  args[2^LJ_BE] = ir->op2; args[3^LJ_BE] = (ir+1)->op2;
1901
1902  for (r = REGARG_FIRSTGPR; r <= REGARG_FIRSTGPR+3; r++) {
1903    if (!rset_test(as->freeset, r) &&
1904	regcost_ref(as->cost[r]) == args[r-REGARG_FIRSTGPR])
1905      rset_clear(drop, r);
1906  }
1907  ra_evictset(as, drop);
1908  asm_setupresult(as, ir, ci);
1909  switch ((IROp)ir->o) {
1910  case IR_ULT:
1911    asm_guardcc(as, CC_EQ);
1912    emit_ai(as, PPCI_CMPWI, RID_RET, 0);
1913  case IR_ULE:
1914    asm_guardcc(as, CC_EQ);
1915    emit_ai(as, PPCI_CMPWI, RID_RET, 1);
1916    break;
1917  case IR_GE: case IR_GT:
1918    asm_guardcc(as, CC_EQ);
1919    emit_ai(as, PPCI_CMPWI, RID_RET, 2);
1920  default:
1921    asm_guardcc(as, (asm_compmap[ir->o] & 0xf));
1922    emit_ai(as, PPCI_CMPWI, RID_RET, 0);
1923    break;
1924  }
1925  asm_gencall(as, ci, args);
1926}
1927#endif
1928
1929#if LJ_HASFFI
1930/* 64 bit integer comparisons. */
1931static void asm_comp64(ASMState *as, IRIns *ir)
1932{
1933  PPCCC cc = asm_compmap[(ir-1)->o];
1934  if ((cc&3) == (CC_EQ&3)) {
1935    asm_guardcc(as, cc);
1936    emit_tab(as, (cc&4) ? PPCI_CRAND : PPCI_CROR,
1937	     (CC_EQ&3), (CC_EQ&3), 4+(CC_EQ&3));
1938  } else {
1939    asm_guardcc(as, CC_EQ);
1940    emit_tab(as, PPCI_CROR, (CC_EQ&3), (CC_EQ&3), ((cc^~(cc>>2))&1));
1941    emit_tab(as, (cc&4) ? PPCI_CRAND : PPCI_CRANDC,
1942	     (CC_EQ&3), (CC_EQ&3), 4+(cc&3));
1943  }
1944  /* Loword comparison sets cr1 and is unsigned, except for equality. */
1945  asm_intcomp_(as, (ir-1)->op1, (ir-1)->op2, 4,
1946	       cc | ((cc&3) == (CC_EQ&3) ? 0 : CC_UNSIGNED));
1947  /* Hiword comparison sets cr0. */
1948  asm_intcomp_(as, ir->op1, ir->op2, 0, cc);
1949  as->flagmcp = NULL;  /* Doesn't work here. */
1950}
1951#endif
1952
1953/* -- Split register ops -------------------------------------------------- */
1954
1955/* Hiword op of a split 32/32 bit op. Previous op is be the loword op. */
1956static void asm_hiop(ASMState *as, IRIns *ir)
1957{
1958  /* HIOP is marked as a store because it needs its own DCE logic. */
1959  int uselo = ra_used(ir-1), usehi = ra_used(ir);  /* Loword/hiword used? */
1960  if (LJ_UNLIKELY(!(as->flags & JIT_F_OPT_DCE))) uselo = usehi = 1;
1961#if LJ_HASFFI || LJ_SOFTFP
1962  if ((ir-1)->o == IR_CONV) {  /* Conversions to/from 64 bit. */
1963    as->curins--;  /* Always skip the CONV. */
1964#if LJ_HASFFI && !LJ_SOFTFP
1965    if (usehi || uselo)
1966      asm_conv64(as, ir);
1967    return;
1968#endif
1969  } else if ((ir-1)->o <= IR_NE) {  /* 64 bit integer comparisons. ORDER IR. */
1970    as->curins--;  /* Always skip the loword comparison. */
1971#if LJ_SOFTFP
1972    if (!irt_isint(ir->t)) {
1973      asm_sfpcomp(as, ir-1);
1974      return;
1975    }
1976#endif
1977#if LJ_HASFFI
1978    asm_comp64(as, ir);
1979#endif
1980    return;
1981#if LJ_SOFTFP
1982  } else if ((ir-1)->o == IR_MIN || (ir-1)->o == IR_MAX) {
1983      as->curins--;  /* Always skip the loword min/max. */
1984    if (uselo || usehi)
1985      asm_sfpmin_max(as, ir-1);
1986    return;
1987#endif
1988  } else if ((ir-1)->o == IR_XSTORE) {
1989    as->curins--;  /* Handle both stores here. */
1990    if ((ir-1)->r != RID_SINK) {
1991      asm_xstore_(as, ir, 0);
1992      asm_xstore_(as, ir-1, 4);
1993    }
1994    return;
1995  }
1996#endif
1997  if (!usehi) return;  /* Skip unused hiword op for all remaining ops. */
1998  switch ((ir-1)->o) {
1999#if LJ_HASFFI
2000  case IR_ADD: as->curins--; asm_add64(as, ir); break;
2001  case IR_SUB: as->curins--; asm_sub64(as, ir); break;
2002  case IR_NEG: as->curins--; asm_neg64(as, ir); break;
2003  case IR_CNEWI:
2004    /* Nothing to do here. Handled by lo op itself. */
2005    break;
2006#endif
2007#if LJ_SOFTFP
2008  case IR_SLOAD: case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
2009  case IR_STRTO:
2010    if (!uselo)
2011      ra_allocref(as, ir->op1, RSET_GPR);  /* Mark lo op as used. */
2012    break;
2013  case IR_ASTORE: case IR_HSTORE: case IR_USTORE: case IR_TOSTR: case IR_TMPREF:
2014    /* Nothing to do here. Handled by lo op itself. */
2015    break;
2016#endif
2017  case IR_CALLN: case IR_CALLL: case IR_CALLS: case IR_CALLXS:
2018    if (!uselo)
2019      ra_allocref(as, ir->op1, RID2RSET(RID_RETLO));  /* Mark lo op as used. */
2020    break;
2021  default: lj_assertA(0, "bad HIOP for op %d", (ir-1)->o); break;
2022  }
2023}
2024
2025/* -- Profiling ----------------------------------------------------------- */
2026
2027static void asm_prof(ASMState *as, IRIns *ir)
2028{
2029  UNUSED(ir);
2030  asm_guardcc(as, CC_NE);
2031  emit_asi(as, PPCI_ANDIDOT, RID_TMP, RID_TMP, HOOK_PROFILE);
2032  emit_lsglptr(as, PPCI_LBZ, RID_TMP,
2033	       (int32_t)offsetof(global_State, hookmask));
2034}
2035
2036/* -- Stack handling ------------------------------------------------------ */
2037
2038/* Check Lua stack size for overflow. Use exit handler as fallback. */
2039static void asm_stack_check(ASMState *as, BCReg topslot,
2040			    IRIns *irp, RegSet allow, ExitNo exitno)
2041{
2042  /* Try to get an unused temp. register, otherwise spill/restore RID_RET*. */
2043  Reg tmp, pbase = irp ? (ra_hasreg(irp->r) ? irp->r : RID_TMP) : RID_BASE;
2044  rset_clear(allow, pbase);
2045  tmp = allow ? rset_pickbot(allow) :
2046		(pbase == RID_RETHI ? RID_RETLO : RID_RETHI);
2047  emit_condbranch(as, PPCI_BC, CC_LT, asm_exitstub_addr(as, exitno));
2048  if (allow == RSET_EMPTY)  /* Restore temp. register. */
2049    emit_tai(as, PPCI_LWZ, tmp, RID_SP, SPOFS_TMPW);
2050  else
2051    ra_modified(as, tmp);
2052  emit_ai(as, PPCI_CMPLWI, RID_TMP, (int32_t)(8*topslot));
2053  emit_tab(as, PPCI_SUBF, RID_TMP, pbase, tmp);
2054  emit_tai(as, PPCI_LWZ, tmp, tmp, offsetof(lua_State, maxstack));
2055  if (pbase == RID_TMP)
2056    emit_getgl(as, RID_TMP, jit_base);
2057  emit_getgl(as, tmp, cur_L);
2058  if (allow == RSET_EMPTY)  /* Spill temp. register. */
2059    emit_tai(as, PPCI_STW, tmp, RID_SP, SPOFS_TMPW);
2060}
2061
2062/* Restore Lua stack from on-trace state. */
2063static void asm_stack_restore(ASMState *as, SnapShot *snap)
2064{
2065  SnapEntry *map = &as->T->snapmap[snap->mapofs];
2066  SnapEntry *flinks = &as->T->snapmap[snap_nextofs(as->T, snap)-1];
2067  MSize n, nent = snap->nent;
2068  /* Store the value of all modified slots to the Lua stack. */
2069  for (n = 0; n < nent; n++) {
2070    SnapEntry sn = map[n];
2071    BCReg s = snap_slot(sn);
2072    int32_t ofs = 8*((int32_t)s-1);
2073    IRRef ref = snap_ref(sn);
2074    IRIns *ir = IR(ref);
2075    if ((sn & SNAP_NORESTORE))
2076      continue;
2077    if (irt_isnum(ir->t)) {
2078#if LJ_SOFTFP
2079      Reg tmp;
2080      RegSet allow = rset_exclude(RSET_GPR, RID_BASE);
2081      /* LJ_SOFTFP: must be a number constant. */
2082      lj_assertA(irref_isk(ref), "unsplit FP op");
2083      tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.lo, allow);
2084      emit_tai(as, PPCI_STW, tmp, RID_BASE, ofs+(LJ_BE?4:0));
2085      if (rset_test(as->freeset, tmp+1)) allow = RID2RSET(tmp+1);
2086      tmp = ra_allock(as, (int32_t)ir_knum(ir)->u32.hi, allow);
2087      emit_tai(as, PPCI_STW, tmp, RID_BASE, ofs+(LJ_BE?0:4));
2088#else
2089      Reg src = ra_alloc1(as, ref, RSET_FPR);
2090      emit_fai(as, PPCI_STFD, src, RID_BASE, ofs);
2091#endif
2092    } else {
2093      Reg type;
2094      RegSet allow = rset_exclude(RSET_GPR, RID_BASE);
2095      lj_assertA(irt_ispri(ir->t) || irt_isaddr(ir->t) || irt_isinteger(ir->t),
2096		 "restore of IR type %d", irt_type(ir->t));
2097      if (!irt_ispri(ir->t)) {
2098	Reg src = ra_alloc1(as, ref, allow);
2099	rset_clear(allow, src);
2100	emit_tai(as, PPCI_STW, src, RID_BASE, ofs+4);
2101      }
2102      if ((sn & (SNAP_CONT|SNAP_FRAME))) {
2103	if (s == 0) continue;  /* Do not overwrite link to previous frame. */
2104	type = ra_allock(as, (int32_t)(*flinks--), allow);
2105#if LJ_SOFTFP
2106      } else if ((sn & SNAP_SOFTFPNUM)) {
2107	type = ra_alloc1(as, ref+1, rset_exclude(RSET_GPR, RID_BASE));
2108#endif
2109      } else if ((sn & SNAP_KEYINDEX)) {
2110	type = ra_allock(as, (int32_t)LJ_KEYINDEX, allow);
2111      } else {
2112	type = ra_allock(as, (int32_t)irt_toitype(ir->t), allow);
2113      }
2114      emit_tai(as, PPCI_STW, type, RID_BASE, ofs);
2115    }
2116    checkmclim(as);
2117  }
2118  lj_assertA(map + nent == flinks, "inconsistent frames in snapshot");
2119}
2120
2121/* -- GC handling --------------------------------------------------------- */
2122
2123/* Marker to prevent patching the GC check exit. */
2124#define PPC_NOPATCH_GC_CHECK	PPCI_ORIS
2125
2126/* Check GC threshold and do one or more GC steps. */
2127static void asm_gc_check(ASMState *as)
2128{
2129  const CCallInfo *ci = &lj_ir_callinfo[IRCALL_lj_gc_step_jit];
2130  IRRef args[2];
2131  MCLabel l_end;
2132  Reg tmp;
2133  ra_evictset(as, RSET_SCRATCH);
2134  l_end = emit_label(as);
2135  /* Exit trace if in GCSatomic or GCSfinalize. Avoids syncing GC objects. */
2136  asm_guardcc(as, CC_NE);  /* Assumes asm_snap_prep() already done. */
2137  *--as->mcp = PPC_NOPATCH_GC_CHECK;
2138  emit_ai(as, PPCI_CMPWI, RID_RET, 0);
2139  args[0] = ASMREF_TMP1;  /* global_State *g */
2140  args[1] = ASMREF_TMP2;  /* MSize steps     */
2141  asm_gencall(as, ci, args);
2142  emit_tai(as, PPCI_ADDI, ra_releasetmp(as, ASMREF_TMP1), RID_JGL, -32768);
2143  tmp = ra_releasetmp(as, ASMREF_TMP2);
2144  emit_loadi(as, tmp, as->gcsteps);
2145  /* Jump around GC step if GC total < GC threshold. */
2146  emit_condbranch(as, PPCI_BC|PPCF_Y, CC_LT, l_end);
2147  emit_ab(as, PPCI_CMPLW, RID_TMP, tmp);
2148  emit_getgl(as, tmp, gc.threshold);
2149  emit_getgl(as, RID_TMP, gc.total);
2150  as->gcsteps = 0;
2151  checkmclim(as);
2152}
2153
2154/* -- Loop handling ------------------------------------------------------- */
2155
2156/* Fixup the loop branch. */
2157static void asm_loop_fixup(ASMState *as)
2158{
2159  MCode *p = as->mctop;
2160  MCode *target = as->mcp;
2161  if (as->loopinv) {  /* Inverted loop branch? */
2162    /* asm_guardcc already inverted the cond branch and patched the final b. */
2163    p[-2] = (p[-2] & (0xffff0000u & ~PPCF_Y)) | (((target-p+2) & 0x3fffu) << 2);
2164  } else {
2165    p[-1] = PPCI_B|(((target-p+1)&0x00ffffffu)<<2);
2166  }
2167}
2168
2169/* Fixup the tail of the loop. */
2170static void asm_loop_tail_fixup(ASMState *as)
2171{
2172  UNUSED(as);  /* Nothing to do. */
2173}
2174
2175/* -- Head of trace ------------------------------------------------------- */
2176
2177/* Coalesce BASE register for a root trace. */
2178static void asm_head_root_base(ASMState *as)
2179{
2180  IRIns *ir = IR(REF_BASE);
2181  Reg r = ir->r;
2182  if (ra_hasreg(r)) {
2183    ra_free(as, r);
2184    if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2185      ir->r = RID_INIT;  /* No inheritance for modified BASE register. */
2186    if (r != RID_BASE)
2187      emit_mr(as, r, RID_BASE);
2188  }
2189}
2190
2191/* Coalesce BASE register for a side trace. */
2192static Reg asm_head_side_base(ASMState *as, IRIns *irp)
2193{
2194  IRIns *ir = IR(REF_BASE);
2195  Reg r = ir->r;
2196  if (ra_hasreg(r)) {
2197    ra_free(as, r);
2198    if (rset_test(as->modset, r) || irt_ismarked(ir->t))
2199      ir->r = RID_INIT;  /* No inheritance for modified BASE register. */
2200    if (irp->r == r) {
2201      return r;  /* Same BASE register already coalesced. */
2202    } else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
2203      emit_mr(as, r, irp->r);  /* Move from coalesced parent reg. */
2204      return irp->r;
2205    } else {
2206      emit_getgl(as, r, jit_base);  /* Otherwise reload BASE. */
2207    }
2208  }
2209  return RID_NONE;
2210}
2211
2212/* -- Tail of trace ------------------------------------------------------- */
2213
2214/* Fixup the tail code. */
2215static void asm_tail_fixup(ASMState *as, TraceNo lnk)
2216{
2217  uintptr_t target = lnk ? (uintptr_t)traceref(as->J, lnk)->mcode : (uintptr_t)(void *)lj_vm_exit_interp;
2218  MCode *mcp = as->mctail;
2219  int32_t spadj = as->T->spadjust;
2220  if (spadj) {  /* Emit stack adjustment. */
2221    lj_assertA(checki16(CFRAME_SIZE+spadj), "stack adjustment out of range");
2222    *mcp++ = PPCI_ADDI | PPCF_T(RID_TMP) | PPCF_A(RID_SP) | (CFRAME_SIZE+spadj);
2223    *mcp++ = PPCI_STWU | PPCF_T(RID_TMP) | PPCF_A(RID_SP) | spadj;
2224  }
2225  /* Emit exit branch. */
2226  if ((((target - (uintptr_t)mcp) + 0x02000000u) >> 26) == 0) {
2227    *mcp = PPCI_B | ((target - (uintptr_t)mcp) & 0x03fffffcu); mcp++;
2228  } else {
2229    *mcp++ = PPCI_LWZ | PPCF_T(RID_TMP) | PPCF_A(RID_JGL) |
2230	     jglofs(as, &as->J->k32[LJ_K32_VM_EXIT_INTERP]);
2231    *mcp++ = PPCI_MTCTR | PPCF_T(RID_TMP);
2232    *mcp++ = PPCI_BCTR;
2233  }
2234  while (as->mctop > mcp) *--as->mctop = PPCI_NOP;
2235}
2236
2237/* Prepare tail of code. */
2238static void asm_tail_prep(ASMState *as, TraceNo lnk)
2239{
2240  MCode *p = as->mctop - 1;  /* Leave room for exit branch. */
2241  if (as->loopref) {
2242    as->invmcp = as->mcp = p;
2243  } else {
2244    if (!lnk) {
2245      uintptr_t target = (uintptr_t)(void *)lj_vm_exit_interp;
2246      if ((((target - (uintptr_t)p) + 0x02000000u) >> 26) ||
2247	  (((target - (uintptr_t)(p-2)) + 0x02000000u) >> 26)) p -= 2;
2248    }
2249    p -= 2;  /* Leave room for stack pointer adjustment. */
2250    as->mcp = p;
2251    as->invmcp = NULL;
2252  }
2253  as->mctail = p;
2254}
2255
2256/* -- Trace setup --------------------------------------------------------- */
2257
2258/* Ensure there are enough stack slots for call arguments. */
2259static Reg asm_setup_call_slots(ASMState *as, IRIns *ir, const CCallInfo *ci)
2260{
2261  IRRef args[CCI_NARGS_MAX*2];
2262  uint32_t i, nargs = CCI_XNARGS(ci);
2263  int nslots = 2, ngpr = REGARG_NUMGPR, nfpr = REGARG_NUMFPR;
2264  asm_collectargs(as, ir, ci, args);
2265  for (i = 0; i < nargs; i++)
2266    if (!LJ_SOFTFP && args[i] && irt_isfp(IR(args[i])->t)) {
2267      if (nfpr > 0) nfpr--; else nslots = (nslots+3) & ~1;
2268    } else {
2269      if (ngpr > 0) ngpr--; else nslots++;
2270    }
2271  if (nslots > as->evenspill)  /* Leave room for args in stack slots. */
2272    as->evenspill = nslots;
2273  return (!LJ_SOFTFP && irt_isfp(ir->t)) ? REGSP_HINT(RID_FPRET) :
2274					   REGSP_HINT(RID_RET);
2275}
2276
2277static void asm_setup_target(ASMState *as)
2278{
2279  asm_exitstub_setup(as, as->T->nsnap + (as->parent ? 1 : 0));
2280}
2281
2282/* -- Trace patching ------------------------------------------------------ */
2283
2284/* Patch exit jumps of existing machine code to a new target. */
2285void lj_asm_patchexit(jit_State *J, GCtrace *T, ExitNo exitno, MCode *target)
2286{
2287  MCode *p = T->mcode;
2288  MCode *pe = (MCode *)((char *)p + T->szmcode);
2289  MCode *px = exitstub_trace_addr(T, exitno);
2290  MCode *cstart = NULL;
2291  MCode *mcarea = lj_mcode_patch(J, p, 0);
2292  int clearso = 0, patchlong = 1;
2293  for (; p < pe; p++) {
2294    /* Look for exitstub branch, try to replace with branch to target. */
2295    uint32_t ins = *p;
2296    if ((ins & 0xfc000000u) == 0x40000000u &&
2297	((ins ^ ((char *)px-(char *)p)) & 0xffffu) == 0) {
2298      ptrdiff_t delta = (char *)target - (char *)p;
2299      if (((ins >> 16) & 3) == (CC_SO&3)) {
2300	clearso = sizeof(MCode);
2301	delta -= sizeof(MCode);
2302      }
2303      /* Many, but not all short-range branches can be patched directly. */
2304      if (p[-1] == PPC_NOPATCH_GC_CHECK) {
2305	patchlong = 0;
2306      } else if (((delta + 0x8000) >> 16) == 0) {
2307	*p = (ins & 0xffdf0000u) | ((uint32_t)delta & 0xffffu) |
2308	     ((delta & 0x8000) * (PPCF_Y/0x8000));
2309	if (!cstart) cstart = p;
2310      }
2311    } else if ((ins & 0xfc000000u) == PPCI_B &&
2312	       ((ins ^ ((char *)px-(char *)p)) & 0x03ffffffu) == 0) {
2313      ptrdiff_t delta = (char *)target - (char *)p;
2314      lj_assertJ(((delta + 0x02000000) >> 26) == 0,
2315		 "branch target out of range");
2316      *p = PPCI_B | ((uint32_t)delta & 0x03ffffffu);
2317      if (!cstart) cstart = p;
2318    }
2319  }
2320  /* Always patch long-range branch in exit stub itself. Except, if we can't. */
2321  if (patchlong) {
2322    ptrdiff_t delta = (char *)target - (char *)px - clearso;
2323    lj_assertJ(((delta + 0x02000000) >> 26) == 0,
2324	       "branch target out of range");
2325    *px = PPCI_B | ((uint32_t)delta & 0x03ffffffu);
2326  }
2327  if (!cstart) cstart = px;
2328  lj_mcode_sync(cstart, px+1);
2329  if (clearso) {  /* Extend the current trace. Ugly workaround. */
2330    MCode *pp = J->cur.mcode;
2331    J->cur.szmcode += sizeof(MCode);
2332    *--pp = PPCI_MCRXR;  /* Clear SO flag. */
2333    J->cur.mcode = pp;
2334    lj_mcode_sync(pp, pp+1);
2335  }
2336  lj_mcode_patch(J, mcarea, 1);
2337}
2338