luna - wolfssl/wolfcrypt/src/port/arm/armv8-32-curve25519.S

   1/* armv8-32-curve25519
   2 *
   3 * Copyright (C) 2006-2026 wolfSSL Inc.
   4 *
   5 * This file is part of wolfSSL.
   6 *
   7 * wolfSSL is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 3 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * wolfSSL is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  20 */
  21
  22/* Generated using (from wolfssl):
  23 *   cd ../scripts
  24 *   ruby ./x25519/x25519.rb arm32 \
  25 *       ../wolfssl/wolfcrypt/src/port/arm/armv8-32-curve25519.S
  26 */
  27
  28#include <wolfssl/wolfcrypt/libwolfssl_sources_asm.h>
  29
  30#ifdef WOLFSSL_ARMASM
  31#if !defined(__aarch64__) && !defined(WOLFSSL_ARMASM_THUMB2)
  32#ifndef WOLFSSL_ARMASM_INLINE
  33#if defined(HAVE_CURVE25519) || defined(HAVE_ED25519)
  34#if !defined(CURVE25519_SMALL) || !defined(ED25519_SMALL)
  35
  36	.text
  37	.align	4
  38	.globl	fe_init
  39	.type	fe_init, %function
  40fe_init:
  41	bx	lr
  42	.size	fe_init,.-fe_init
  43	.text
  44	.align	4
  45	.globl	fe_add_sub_op
  46	.type	fe_add_sub_op, %function
  47fe_add_sub_op:
  48	push	{lr}
  49	# Add-Sub
  50#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
  51	ldm	r2, {r4, r5}
  52#else
  53	ldrd	r4, r5, [r2]
  54#endif
  55#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
  56	ldm	r3, {r6, r7}
  57#else
  58	ldrd	r6, r7, [r3]
  59#endif
  60	#  Add
  61	adds	r8, r4, r6
  62	mov	r12, #0
  63	adcs	r9, r5, r7
  64	adc	r12, r12, #0
  65#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
  66	stm	r0, {r8, r9}
  67#else
  68	strd	r8, r9, [r0]
  69#endif
  70	#  Sub
  71	subs	r10, r4, r6
  72	sbcs	r11, r5, r7
  73#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
  74	stm	r1, {r10, r11}
  75#else
  76	strd	r10, r11, [r1]
  77#endif
  78#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
  79	ldr	r4, [r2, #8]
  80	ldr	r5, [r2, #12]
  81#else
  82	ldrd	r4, r5, [r2, #8]
  83#endif
  84#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
  85	ldr	r6, [r3, #8]
  86	ldr	r7, [r3, #12]
  87#else
  88	ldrd	r6, r7, [r3, #8]
  89#endif
  90	#  Sub
  91	sbcs	r10, r4, r6
  92	mov	lr, #0
  93	sbcs	r11, r5, r7
  94	adc	lr, lr, #0
  95#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
  96	str	r10, [r1, #8]
  97	str	r11, [r1, #12]
  98#else
  99	strd	r10, r11, [r1, #8]
 100#endif
 101	#  Add
 102	subs	r12, r12, #1
 103	adcs	r8, r4, r6
 104	adcs	r9, r5, r7
 105#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 106	str	r8, [r0, #8]
 107	str	r9, [r0, #12]
 108#else
 109	strd	r8, r9, [r0, #8]
 110#endif
 111#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 112	ldr	r4, [r2, #16]
 113	ldr	r5, [r2, #20]
 114#else
 115	ldrd	r4, r5, [r2, #16]
 116#endif
 117#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 118	ldr	r6, [r3, #16]
 119	ldr	r7, [r3, #20]
 120#else
 121	ldrd	r6, r7, [r3, #16]
 122#endif
 123	#  Add
 124	adcs	r8, r4, r6
 125	mov	r12, #0
 126	adcs	r9, r5, r7
 127	adc	r12, r12, #0
 128#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 129	str	r8, [r0, #16]
 130	str	r9, [r0, #20]
 131#else
 132	strd	r8, r9, [r0, #16]
 133#endif
 134	#  Sub
 135	subs	lr, lr, #1
 136	sbcs	r10, r4, r6
 137	sbcs	r11, r5, r7
 138#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 139	str	r10, [r1, #16]
 140	str	r11, [r1, #20]
 141#else
 142	strd	r10, r11, [r1, #16]
 143#endif
 144#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 145	ldr	r4, [r2, #24]
 146	ldr	r5, [r2, #28]
 147#else
 148	ldrd	r4, r5, [r2, #24]
 149#endif
 150#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 151	ldr	r6, [r3, #24]
 152	ldr	r7, [r3, #28]
 153#else
 154	ldrd	r6, r7, [r3, #24]
 155#endif
 156	#  Sub
 157	sbcs	r10, r4, r6
 158	sbcs	r11, r5, r7
 159	sbc	lr, lr, lr
 160	#  Add
 161	subs	r12, r12, #1
 162	adcs	r8, r4, r6
 163	mov	r12, #0
 164	adcs	r9, r5, r7
 165	adc	r12, r12, #0
 166	#   Multiply -modulus by overflow
 167	lsl	r3, r12, #1
 168	mov	r12, #19
 169	orr	r3, r3, r9, lsr #31
 170	mul	r12, r3, r12
 171	#   Add -x*modulus (if overflow)
 172#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 173	ldm	r0, {r4, r5}
 174#else
 175	ldrd	r4, r5, [r0]
 176#endif
 177#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 178	ldr	r6, [r0, #8]
 179	ldr	r7, [r0, #12]
 180#else
 181	ldrd	r6, r7, [r0, #8]
 182#endif
 183	adds	r4, r4, r12
 184	adcs	r5, r5, #0
 185	adcs	r6, r6, #0
 186	adcs	r7, r7, #0
 187#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 188	stm	r0, {r4, r5}
 189#else
 190	strd	r4, r5, [r0]
 191#endif
 192#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 193	str	r6, [r0, #8]
 194	str	r7, [r0, #12]
 195#else
 196	strd	r6, r7, [r0, #8]
 197#endif
 198#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 199	ldr	r4, [r0, #16]
 200	ldr	r5, [r0, #20]
 201#else
 202	ldrd	r4, r5, [r0, #16]
 203#endif
 204	adcs	r4, r4, #0
 205	adcs	r5, r5, #0
 206#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 207	str	r4, [r0, #16]
 208	str	r5, [r0, #20]
 209#else
 210	strd	r4, r5, [r0, #16]
 211#endif
 212#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 213	bic	r9, r9, #0x80000000
 214#else
 215	bfc	r9, #31, #1
 216#endif
 217	adcs	r8, r8, #0
 218	adc	r9, r9, #0
 219#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 220	str	r8, [r0, #24]
 221	str	r9, [r0, #28]
 222#else
 223	strd	r8, r9, [r0, #24]
 224#endif
 225	#   Multiply -modulus by underflow
 226	lsl	r3, lr, #1
 227	mvn	lr, #18
 228	orr	r3, r3, r11, lsr #31
 229	mul	lr, r3, lr
 230	#   Sub -x*modulus (if overflow)
 231	ldm	r1, {r4, r5, r6, r7, r8, r9}
 232	subs	r4, r4, lr
 233	sbcs	r5, r5, #0
 234	sbcs	r6, r6, #0
 235	sbcs	r7, r7, #0
 236	sbcs	r8, r8, #0
 237	sbcs	r9, r9, #0
 238#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 239	bic	r11, r11, #0x80000000
 240#else
 241	bfc	r11, #31, #1
 242#endif
 243	sbcs	r10, r10, #0
 244	sbc	r11, r11, #0
 245	stm	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
 246	# Done Add-Sub
 247	pop	{pc}
 248	.size	fe_add_sub_op,.-fe_add_sub_op
 249	.text
 250	.align	4
 251	.globl	fe_sub_op
 252	.type	fe_sub_op, %function
 253fe_sub_op:
 254	push	{lr}
 255	# Sub
 256	ldm	r2!, {r6, r7, r8, r9, r10, r11, r12, lr}
 257	ldm	r1!, {r2, r3, r4, r5}
 258	subs	r6, r2, r6
 259	sbcs	r7, r3, r7
 260	sbcs	r8, r4, r8
 261	sbcs	r9, r5, r9
 262	ldm	r1!, {r2, r3, r4, r5}
 263	sbcs	r10, r2, r10
 264	sbcs	r11, r3, r11
 265	sbcs	r12, r4, r12
 266	sbcs	lr, r5, lr
 267	sbc	r3, r3, r3
 268	mvn	r2, #18
 269	lsl	r3, r3, #1
 270	orr	r3, r3, lr, lsr #31
 271	mul	r2, r3, r2
 272	subs	r6, r6, r2
 273	sbcs	r7, r7, #0
 274	sbcs	r8, r8, #0
 275	sbcs	r9, r9, #0
 276	sbcs	r10, r10, #0
 277	sbcs	r11, r11, #0
 278#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 279	bic	lr, lr, #0x80000000
 280#else
 281	bfc	lr, #31, #1
 282#endif
 283	sbcs	r12, r12, #0
 284	sbc	lr, lr, #0
 285	stm	r0, {r6, r7, r8, r9, r10, r11, r12, lr}
 286	# Done Sub
 287	pop	{pc}
 288	.size	fe_sub_op,.-fe_sub_op
 289	.text
 290	.align	4
 291	.globl	fe_sub
 292	.type	fe_sub, %function
 293fe_sub:
 294	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 295	bl	fe_sub_op
 296	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 297	.size	fe_sub,.-fe_sub
 298	.text
 299	.align	4
 300	.globl	fe_add_op
 301	.type	fe_add_op, %function
 302fe_add_op:
 303	push	{lr}
 304	# Add
 305	ldm	r2!, {r6, r7, r8, r9, r10, r11, r12, lr}
 306	ldm	r1!, {r2, r3, r4, r5}
 307	adds	r6, r2, r6
 308	adcs	r7, r3, r7
 309	adcs	r8, r4, r8
 310	adcs	r9, r5, r9
 311	ldm	r1!, {r2, r3, r4, r5}
 312	adcs	r10, r2, r10
 313	adcs	r11, r3, r11
 314	adcs	r12, r4, r12
 315	mov	r3, #0
 316	adcs	lr, r5, lr
 317	adc	r3, r3, #0
 318	mov	r2, #19
 319	lsl	r3, r3, #1
 320	orr	r3, r3, lr, lsr #31
 321	mul	r2, r3, r2
 322	adds	r6, r6, r2
 323	adcs	r7, r7, #0
 324	adcs	r8, r8, #0
 325	adcs	r9, r9, #0
 326	adcs	r10, r10, #0
 327	adcs	r11, r11, #0
 328#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 329	bic	lr, lr, #0x80000000
 330#else
 331	bfc	lr, #31, #1
 332#endif
 333	adcs	r12, r12, #0
 334	adc	lr, lr, #0
 335	stm	r0, {r6, r7, r8, r9, r10, r11, r12, lr}
 336	# Done Add
 337	pop	{pc}
 338	.size	fe_add_op,.-fe_add_op
 339	.text
 340	.align	4
 341	.globl	fe_add
 342	.type	fe_add, %function
 343fe_add:
 344	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 345	bl	fe_add_op
 346	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 347	.size	fe_add,.-fe_add
 348#if defined(HAVE_ED25519) || defined(WOLFSSL_CURVE25519_USE_ED25519)
 349	.text
 350	.align	4
 351	.globl	fe_frombytes
 352	.type	fe_frombytes, %function
 353fe_frombytes:
 354	push	{r4, r5, r6, r7, r8, r9, lr}
 355	ldr	r2, [r1]
 356	ldr	r3, [r1, #4]
 357	ldr	r4, [r1, #8]
 358	ldr	r5, [r1, #12]
 359	ldr	r6, [r1, #16]
 360	ldr	r7, [r1, #20]
 361	ldr	r8, [r1, #24]
 362	ldr	r9, [r1, #28]
 363#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 364	bic	r9, r9, #0x80000000
 365#else
 366	bfc	r9, #31, #1
 367#endif
 368	str	r2, [r0]
 369	str	r3, [r0, #4]
 370	str	r4, [r0, #8]
 371	str	r5, [r0, #12]
 372	str	r6, [r0, #16]
 373	str	r7, [r0, #20]
 374	str	r8, [r0, #24]
 375	str	r9, [r0, #28]
 376	pop	{r4, r5, r6, r7, r8, r9, pc}
 377	.size	fe_frombytes,.-fe_frombytes
 378	.text
 379	.align	4
 380	.globl	fe_tobytes
 381	.type	fe_tobytes, %function
 382fe_tobytes:
 383	push	{r4, r5, r6, r7, r8, r9, lr}
 384	ldm	r1, {r2, r3, r4, r5, r6, r7, r8, r9}
 385	adds	r12, r2, #19
 386	adcs	r12, r3, #0
 387	adcs	r12, r4, #0
 388	adcs	r12, r5, #0
 389	adcs	r12, r6, #0
 390	adcs	r12, r7, #0
 391	adcs	r12, r8, #0
 392	adc	r12, r9, #0
 393	asr	r12, r12, #31
 394	and	r12, r12, #19
 395	adds	r2, r2, r12
 396	adcs	r3, r3, #0
 397	adcs	r4, r4, #0
 398	adcs	r5, r5, #0
 399	adcs	r6, r6, #0
 400	adcs	r7, r7, #0
 401	adcs	r8, r8, #0
 402	adc	r9, r9, #0
 403#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 404	bic	r9, r9, #0x80000000
 405#else
 406	bfc	r9, #31, #1
 407#endif
 408	str	r2, [r0]
 409	str	r3, [r0, #4]
 410	str	r4, [r0, #8]
 411	str	r5, [r0, #12]
 412	str	r6, [r0, #16]
 413	str	r7, [r0, #20]
 414	str	r8, [r0, #24]
 415	str	r9, [r0, #28]
 416	pop	{r4, r5, r6, r7, r8, r9, pc}
 417	.size	fe_tobytes,.-fe_tobytes
 418	.text
 419	.align	4
 420	.globl	fe_1
 421	.type	fe_1, %function
 422fe_1:
 423	push	{r4, r5, r6, r7, r8, r9, lr}
 424	# Set one
 425	mov	r2, #1
 426	mov	r3, #0
 427	mov	r4, #0
 428	mov	r5, #0
 429	mov	r6, #0
 430	mov	r7, #0
 431	mov	r8, #0
 432	mov	r9, #0
 433	stm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
 434	pop	{r4, r5, r6, r7, r8, r9, pc}
 435	.size	fe_1,.-fe_1
 436	.text
 437	.align	4
 438	.globl	fe_0
 439	.type	fe_0, %function
 440fe_0:
 441	push	{r4, r5, r6, r7, r8, r9, lr}
 442	# Set zero
 443	mov	r2, #0
 444	mov	r3, #0
 445	mov	r4, #0
 446	mov	r5, #0
 447	mov	r6, #0
 448	mov	r7, #0
 449	mov	r8, #0
 450	mov	r9, #0
 451	stm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
 452	pop	{r4, r5, r6, r7, r8, r9, pc}
 453	.size	fe_0,.-fe_0
 454	.text
 455	.align	4
 456	.globl	fe_copy
 457	.type	fe_copy, %function
 458fe_copy:
 459	push	{r4, r5, lr}
 460	# Copy
 461#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 462	ldm	r1, {r2, r3}
 463#else
 464	ldrd	r2, r3, [r1]
 465#endif
 466#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 467	ldr	r4, [r1, #8]
 468	ldr	r5, [r1, #12]
 469#else
 470	ldrd	r4, r5, [r1, #8]
 471#endif
 472#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 473	stm	r0, {r2, r3}
 474#else
 475	strd	r2, r3, [r0]
 476#endif
 477#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 478	str	r4, [r0, #8]
 479	str	r5, [r0, #12]
 480#else
 481	strd	r4, r5, [r0, #8]
 482#endif
 483#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 484	ldr	r2, [r1, #16]
 485	ldr	r3, [r1, #20]
 486#else
 487	ldrd	r2, r3, [r1, #16]
 488#endif
 489#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 490	ldr	r4, [r1, #24]
 491	ldr	r5, [r1, #28]
 492#else
 493	ldrd	r4, r5, [r1, #24]
 494#endif
 495#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 496	str	r2, [r0, #16]
 497	str	r3, [r0, #20]
 498#else
 499	strd	r2, r3, [r0, #16]
 500#endif
 501#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 502	str	r4, [r0, #24]
 503	str	r5, [r0, #28]
 504#else
 505	strd	r4, r5, [r0, #24]
 506#endif
 507	pop	{r4, r5, pc}
 508	.size	fe_copy,.-fe_copy
 509	.text
 510	.align	4
 511	.globl	fe_neg
 512	.type	fe_neg, %function
 513fe_neg:
 514	push	{r4, r5, lr}
 515	mvn	lr, #0
 516	mvn	r12, #18
 517	ldm	r1!, {r2, r3, r4, r5}
 518	subs	r2, r12, r2
 519	sbcs	r3, lr, r3
 520	sbcs	r4, lr, r4
 521	sbcs	r5, lr, r5
 522	stm	r0!, {r2, r3, r4, r5}
 523	mvn	r12, #0x80000000
 524	ldm	r1!, {r2, r3, r4, r5}
 525	sbcs	r2, lr, r2
 526	sbcs	r3, lr, r3
 527	sbcs	r4, lr, r4
 528	sbc	r5, r12, r5
 529	stm	r0!, {r2, r3, r4, r5}
 530	pop	{r4, r5, pc}
 531	.size	fe_neg,.-fe_neg
 532	.text
 533	.align	4
 534	.globl	fe_isnonzero
 535	.type	fe_isnonzero, %function
 536fe_isnonzero:
 537	push	{r4, r5, r6, r7, r8, r9, lr}
 538	ldm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
 539	adds	r1, r2, #19
 540	adcs	r1, r3, #0
 541	adcs	r1, r4, #0
 542	adcs	r1, r5, #0
 543	adcs	r1, r6, #0
 544	adcs	r1, r7, #0
 545	adcs	r1, r8, #0
 546	adc	r1, r9, #0
 547	asr	r1, r1, #31
 548	and	r1, r1, #19
 549	adds	r2, r2, r1
 550	adcs	r3, r3, #0
 551	adcs	r4, r4, #0
 552	adcs	r5, r5, #0
 553	adcs	r6, r6, #0
 554	adcs	r7, r7, #0
 555	adcs	r8, r8, #0
 556	adc	r9, r9, #0
 557#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 558	bic	r9, r9, #0x80000000
 559#else
 560	bfc	r9, #31, #1
 561#endif
 562	orr	r2, r2, r3
 563	orr	r4, r4, r5
 564	orr	r6, r6, r7
 565	orr	r8, r8, r9
 566	orr	r4, r4, r6
 567	orr	r2, r2, r8
 568	orr	r0, r2, r4
 569	pop	{r4, r5, r6, r7, r8, r9, pc}
 570	.size	fe_isnonzero,.-fe_isnonzero
 571	.text
 572	.align	4
 573	.globl	fe_isnegative
 574	.type	fe_isnegative, %function
 575fe_isnegative:
 576	push	{r4, r5, lr}
 577	ldm	r0!, {r2, r3, r4, r5}
 578	adds	r1, r2, #19
 579	adcs	r1, r3, #0
 580	adcs	r1, r4, #0
 581	adcs	r1, r5, #0
 582	ldm	r0, {r2, r3, r4, r5}
 583	adcs	r1, r2, #0
 584	adcs	r1, r3, #0
 585	adcs	r1, r4, #0
 586	ldr	r2, [r0, #-16]
 587	adc	r1, r5, #0
 588	and	r0, r2, #1
 589	lsr	r1, r1, #31
 590	eor	r0, r0, r1
 591	pop	{r4, r5, pc}
 592	.size	fe_isnegative,.-fe_isnegative
 593#if defined(HAVE_ED25519_MAKE_KEY) || defined(HAVE_ED25519_SIGN) || defined(WOLFSSL_CURVE25519_USE_ED25519)
 594#ifndef WC_NO_CACHE_RESISTANT
 595	.text
 596	.align	4
 597	.globl	fe_cmov_table
 598	.type	fe_cmov_table, %function
 599fe_cmov_table:
 600	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 601#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
 602	lsl	r2, r2, #24
 603	asr	r2, r2, #24
 604#else
 605	sxtb	r2, r2
 606#endif
 607#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 608	lsl	r3, r2, #24
 609	asr	r3, r3, #31
 610#else
 611	sbfx	r3, r2, #7, #1
 612#endif
 613	eor	r12, r2, r3
 614	sub	r12, r12, r3
 615	mov	r4, #1
 616	mov	r5, #0
 617	mov	r6, #1
 618	mov	r7, #0
 619	mov	r8, #0
 620	mov	r9, #0
 621	mov	r3, #0x80000000
 622	ror	r3, r3, #31
 623	ror	r3, r3, r12
 624	asr	r3, r3, #31
 625#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 626	ldm	r1, {r10, r11}
 627#else
 628	ldrd	r10, r11, [r1]
 629#endif
 630	eor	r10, r10, r4
 631	eor	r11, r11, r5
 632	and	r10, r10, r3
 633	and	r11, r11, r3
 634	eor	r4, r4, r10
 635	eor	r5, r5, r11
 636#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 637	ldr	r10, [r1, #32]
 638	ldr	r11, [r1, #36]
 639#else
 640	ldrd	r10, r11, [r1, #32]
 641#endif
 642	eor	r10, r10, r6
 643	eor	r11, r11, r7
 644	and	r10, r10, r3
 645	and	r11, r11, r3
 646	eor	r6, r6, r10
 647	eor	r7, r7, r11
 648#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 649	ldr	r10, [r1, #64]
 650	ldr	r11, [r1, #68]
 651#else
 652	ldrd	r10, r11, [r1, #64]
 653#endif
 654	eor	r10, r10, r8
 655	eor	r11, r11, r9
 656	and	r10, r10, r3
 657	and	r11, r11, r3
 658	eor	r8, r8, r10
 659	eor	r9, r9, r11
 660	add	r1, r1, #0x60
 661	mov	r3, #0x80000000
 662	ror	r3, r3, #30
 663	ror	r3, r3, r12
 664	asr	r3, r3, #31
 665#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 666	ldm	r1, {r10, r11}
 667#else
 668	ldrd	r10, r11, [r1]
 669#endif
 670	eor	r10, r10, r4
 671	eor	r11, r11, r5
 672	and	r10, r10, r3
 673	and	r11, r11, r3
 674	eor	r4, r4, r10
 675	eor	r5, r5, r11
 676#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 677	ldr	r10, [r1, #32]
 678	ldr	r11, [r1, #36]
 679#else
 680	ldrd	r10, r11, [r1, #32]
 681#endif
 682	eor	r10, r10, r6
 683	eor	r11, r11, r7
 684	and	r10, r10, r3
 685	and	r11, r11, r3
 686	eor	r6, r6, r10
 687	eor	r7, r7, r11
 688#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 689	ldr	r10, [r1, #64]
 690	ldr	r11, [r1, #68]
 691#else
 692	ldrd	r10, r11, [r1, #64]
 693#endif
 694	eor	r10, r10, r8
 695	eor	r11, r11, r9
 696	and	r10, r10, r3
 697	and	r11, r11, r3
 698	eor	r8, r8, r10
 699	eor	r9, r9, r11
 700	add	r1, r1, #0x60
 701	mov	r3, #0x80000000
 702	ror	r3, r3, #29
 703	ror	r3, r3, r12
 704	asr	r3, r3, #31
 705#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 706	ldm	r1, {r10, r11}
 707#else
 708	ldrd	r10, r11, [r1]
 709#endif
 710	eor	r10, r10, r4
 711	eor	r11, r11, r5
 712	and	r10, r10, r3
 713	and	r11, r11, r3
 714	eor	r4, r4, r10
 715	eor	r5, r5, r11
 716#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 717	ldr	r10, [r1, #32]
 718	ldr	r11, [r1, #36]
 719#else
 720	ldrd	r10, r11, [r1, #32]
 721#endif
 722	eor	r10, r10, r6
 723	eor	r11, r11, r7
 724	and	r10, r10, r3
 725	and	r11, r11, r3
 726	eor	r6, r6, r10
 727	eor	r7, r7, r11
 728#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 729	ldr	r10, [r1, #64]
 730	ldr	r11, [r1, #68]
 731#else
 732	ldrd	r10, r11, [r1, #64]
 733#endif
 734	eor	r10, r10, r8
 735	eor	r11, r11, r9
 736	and	r10, r10, r3
 737	and	r11, r11, r3
 738	eor	r8, r8, r10
 739	eor	r9, r9, r11
 740	add	r1, r1, #0x60
 741	mov	r3, #0x80000000
 742	ror	r3, r3, #28
 743	ror	r3, r3, r12
 744	asr	r3, r3, #31
 745#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 746	ldm	r1, {r10, r11}
 747#else
 748	ldrd	r10, r11, [r1]
 749#endif
 750	eor	r10, r10, r4
 751	eor	r11, r11, r5
 752	and	r10, r10, r3
 753	and	r11, r11, r3
 754	eor	r4, r4, r10
 755	eor	r5, r5, r11
 756#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 757	ldr	r10, [r1, #32]
 758	ldr	r11, [r1, #36]
 759#else
 760	ldrd	r10, r11, [r1, #32]
 761#endif
 762	eor	r10, r10, r6
 763	eor	r11, r11, r7
 764	and	r10, r10, r3
 765	and	r11, r11, r3
 766	eor	r6, r6, r10
 767	eor	r7, r7, r11
 768#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 769	ldr	r10, [r1, #64]
 770	ldr	r11, [r1, #68]
 771#else
 772	ldrd	r10, r11, [r1, #64]
 773#endif
 774	eor	r10, r10, r8
 775	eor	r11, r11, r9
 776	and	r10, r10, r3
 777	and	r11, r11, r3
 778	eor	r8, r8, r10
 779	eor	r9, r9, r11
 780	add	r1, r1, #0x60
 781	mov	r3, #0x80000000
 782	ror	r3, r3, #27
 783	ror	r3, r3, r12
 784	asr	r3, r3, #31
 785#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 786	ldm	r1, {r10, r11}
 787#else
 788	ldrd	r10, r11, [r1]
 789#endif
 790	eor	r10, r10, r4
 791	eor	r11, r11, r5
 792	and	r10, r10, r3
 793	and	r11, r11, r3
 794	eor	r4, r4, r10
 795	eor	r5, r5, r11
 796#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 797	ldr	r10, [r1, #32]
 798	ldr	r11, [r1, #36]
 799#else
 800	ldrd	r10, r11, [r1, #32]
 801#endif
 802	eor	r10, r10, r6
 803	eor	r11, r11, r7
 804	and	r10, r10, r3
 805	and	r11, r11, r3
 806	eor	r6, r6, r10
 807	eor	r7, r7, r11
 808#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 809	ldr	r10, [r1, #64]
 810	ldr	r11, [r1, #68]
 811#else
 812	ldrd	r10, r11, [r1, #64]
 813#endif
 814	eor	r10, r10, r8
 815	eor	r11, r11, r9
 816	and	r10, r10, r3
 817	and	r11, r11, r3
 818	eor	r8, r8, r10
 819	eor	r9, r9, r11
 820	add	r1, r1, #0x60
 821	mov	r3, #0x80000000
 822	ror	r3, r3, #26
 823	ror	r3, r3, r12
 824	asr	r3, r3, #31
 825#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 826	ldm	r1, {r10, r11}
 827#else
 828	ldrd	r10, r11, [r1]
 829#endif
 830	eor	r10, r10, r4
 831	eor	r11, r11, r5
 832	and	r10, r10, r3
 833	and	r11, r11, r3
 834	eor	r4, r4, r10
 835	eor	r5, r5, r11
 836#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 837	ldr	r10, [r1, #32]
 838	ldr	r11, [r1, #36]
 839#else
 840	ldrd	r10, r11, [r1, #32]
 841#endif
 842	eor	r10, r10, r6
 843	eor	r11, r11, r7
 844	and	r10, r10, r3
 845	and	r11, r11, r3
 846	eor	r6, r6, r10
 847	eor	r7, r7, r11
 848#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 849	ldr	r10, [r1, #64]
 850	ldr	r11, [r1, #68]
 851#else
 852	ldrd	r10, r11, [r1, #64]
 853#endif
 854	eor	r10, r10, r8
 855	eor	r11, r11, r9
 856	and	r10, r10, r3
 857	and	r11, r11, r3
 858	eor	r8, r8, r10
 859	eor	r9, r9, r11
 860	add	r1, r1, #0x60
 861	mov	r3, #0x80000000
 862	ror	r3, r3, #25
 863	ror	r3, r3, r12
 864	asr	r3, r3, #31
 865#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 866	ldm	r1, {r10, r11}
 867#else
 868	ldrd	r10, r11, [r1]
 869#endif
 870	eor	r10, r10, r4
 871	eor	r11, r11, r5
 872	and	r10, r10, r3
 873	and	r11, r11, r3
 874	eor	r4, r4, r10
 875	eor	r5, r5, r11
 876#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 877	ldr	r10, [r1, #32]
 878	ldr	r11, [r1, #36]
 879#else
 880	ldrd	r10, r11, [r1, #32]
 881#endif
 882	eor	r10, r10, r6
 883	eor	r11, r11, r7
 884	and	r10, r10, r3
 885	and	r11, r11, r3
 886	eor	r6, r6, r10
 887	eor	r7, r7, r11
 888#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 889	ldr	r10, [r1, #64]
 890	ldr	r11, [r1, #68]
 891#else
 892	ldrd	r10, r11, [r1, #64]
 893#endif
 894	eor	r10, r10, r8
 895	eor	r11, r11, r9
 896	and	r10, r10, r3
 897	and	r11, r11, r3
 898	eor	r8, r8, r10
 899	eor	r9, r9, r11
 900	add	r1, r1, #0x60
 901	mov	r3, #0x80000000
 902	ror	r3, r3, #24
 903	ror	r3, r3, r12
 904	asr	r3, r3, #31
 905#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 906	ldm	r1, {r10, r11}
 907#else
 908	ldrd	r10, r11, [r1]
 909#endif
 910	eor	r10, r10, r4
 911	eor	r11, r11, r5
 912	and	r10, r10, r3
 913	and	r11, r11, r3
 914	eor	r4, r4, r10
 915	eor	r5, r5, r11
 916#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 917	ldr	r10, [r1, #32]
 918	ldr	r11, [r1, #36]
 919#else
 920	ldrd	r10, r11, [r1, #32]
 921#endif
 922	eor	r10, r10, r6
 923	eor	r11, r11, r7
 924	and	r10, r10, r3
 925	and	r11, r11, r3
 926	eor	r6, r6, r10
 927	eor	r7, r7, r11
 928#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 929	ldr	r10, [r1, #64]
 930	ldr	r11, [r1, #68]
 931#else
 932	ldrd	r10, r11, [r1, #64]
 933#endif
 934	eor	r10, r10, r8
 935	eor	r11, r11, r9
 936	and	r10, r10, r3
 937	and	r11, r11, r3
 938	eor	r8, r8, r10
 939	eor	r9, r9, r11
 940	sub	r1, r1, #0x2a0
 941	mvn	r10, #18
 942	mvn	r11, #0
 943	subs	r10, r10, r8
 944	sbcs	r11, r11, r9
 945	sbc	lr, lr, lr
 946	asr	r12, r2, #31
 947	eor	r3, r4, r6
 948	and	r3, r3, r12
 949	eor	r4, r4, r3
 950	eor	r6, r6, r3
 951	eor	r3, r5, r7
 952	and	r3, r3, r12
 953	eor	r5, r5, r3
 954	eor	r7, r7, r3
 955	eor	r10, r10, r8
 956	and	r10, r10, r12
 957	eor	r8, r8, r10
 958	eor	r11, r11, r9
 959	and	r11, r11, r12
 960	eor	r9, r9, r11
 961#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 962	stm	r0, {r4, r5}
 963#else
 964	strd	r4, r5, [r0]
 965#endif
 966#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 967	str	r6, [r0, #32]
 968	str	r7, [r0, #36]
 969#else
 970	strd	r6, r7, [r0, #32]
 971#endif
 972#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 973	str	r8, [r0, #64]
 974	str	r9, [r0, #68]
 975#else
 976	strd	r8, r9, [r0, #64]
 977#endif
 978#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 979	lsl	r3, r2, #24
 980	asr	r3, r3, #31
 981#else
 982	sbfx	r3, r2, #7, #1
 983#endif
 984	eor	r12, r2, r3
 985	sub	r12, r12, r3
 986	mov	r4, #0
 987	mov	r5, #0
 988	mov	r6, #0
 989	mov	r7, #0
 990	mov	r8, #0
 991	mov	r9, #0
 992	mov	r3, #0x80000000
 993	ror	r3, r3, #31
 994	ror	r3, r3, r12
 995	asr	r3, r3, #31
 996#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
 997	ldr	r10, [r1, #8]
 998	ldr	r11, [r1, #12]
 999#else
1000	ldrd	r10, r11, [r1, #8]
1001#endif
1002	eor	r10, r10, r4
1003	eor	r11, r11, r5
1004	and	r10, r10, r3
1005	and	r11, r11, r3
1006	eor	r4, r4, r10
1007	eor	r5, r5, r11
1008#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1009	ldr	r10, [r1, #40]
1010	ldr	r11, [r1, #44]
1011#else
1012	ldrd	r10, r11, [r1, #40]
1013#endif
1014	eor	r10, r10, r6
1015	eor	r11, r11, r7
1016	and	r10, r10, r3
1017	and	r11, r11, r3
1018	eor	r6, r6, r10
1019	eor	r7, r7, r11
1020#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1021	ldr	r10, [r1, #72]
1022	ldr	r11, [r1, #76]
1023#else
1024	ldrd	r10, r11, [r1, #72]
1025#endif
1026	eor	r10, r10, r8
1027	eor	r11, r11, r9
1028	and	r10, r10, r3
1029	and	r11, r11, r3
1030	eor	r8, r8, r10
1031	eor	r9, r9, r11
1032	add	r1, r1, #0x60
1033	mov	r3, #0x80000000
1034	ror	r3, r3, #30
1035	ror	r3, r3, r12
1036	asr	r3, r3, #31
1037#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1038	ldr	r10, [r1, #8]
1039	ldr	r11, [r1, #12]
1040#else
1041	ldrd	r10, r11, [r1, #8]
1042#endif
1043	eor	r10, r10, r4
1044	eor	r11, r11, r5
1045	and	r10, r10, r3
1046	and	r11, r11, r3
1047	eor	r4, r4, r10
1048	eor	r5, r5, r11
1049#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1050	ldr	r10, [r1, #40]
1051	ldr	r11, [r1, #44]
1052#else
1053	ldrd	r10, r11, [r1, #40]
1054#endif
1055	eor	r10, r10, r6
1056	eor	r11, r11, r7
1057	and	r10, r10, r3
1058	and	r11, r11, r3
1059	eor	r6, r6, r10
1060	eor	r7, r7, r11
1061#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1062	ldr	r10, [r1, #72]
1063	ldr	r11, [r1, #76]
1064#else
1065	ldrd	r10, r11, [r1, #72]
1066#endif
1067	eor	r10, r10, r8
1068	eor	r11, r11, r9
1069	and	r10, r10, r3
1070	and	r11, r11, r3
1071	eor	r8, r8, r10
1072	eor	r9, r9, r11
1073	add	r1, r1, #0x60
1074	mov	r3, #0x80000000
1075	ror	r3, r3, #29
1076	ror	r3, r3, r12
1077	asr	r3, r3, #31
1078#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1079	ldr	r10, [r1, #8]
1080	ldr	r11, [r1, #12]
1081#else
1082	ldrd	r10, r11, [r1, #8]
1083#endif
1084	eor	r10, r10, r4
1085	eor	r11, r11, r5
1086	and	r10, r10, r3
1087	and	r11, r11, r3
1088	eor	r4, r4, r10
1089	eor	r5, r5, r11
1090#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1091	ldr	r10, [r1, #40]
1092	ldr	r11, [r1, #44]
1093#else
1094	ldrd	r10, r11, [r1, #40]
1095#endif
1096	eor	r10, r10, r6
1097	eor	r11, r11, r7
1098	and	r10, r10, r3
1099	and	r11, r11, r3
1100	eor	r6, r6, r10
1101	eor	r7, r7, r11
1102#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1103	ldr	r10, [r1, #72]
1104	ldr	r11, [r1, #76]
1105#else
1106	ldrd	r10, r11, [r1, #72]
1107#endif
1108	eor	r10, r10, r8
1109	eor	r11, r11, r9
1110	and	r10, r10, r3
1111	and	r11, r11, r3
1112	eor	r8, r8, r10
1113	eor	r9, r9, r11
1114	add	r1, r1, #0x60
1115	mov	r3, #0x80000000
1116	ror	r3, r3, #28
1117	ror	r3, r3, r12
1118	asr	r3, r3, #31
1119#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1120	ldr	r10, [r1, #8]
1121	ldr	r11, [r1, #12]
1122#else
1123	ldrd	r10, r11, [r1, #8]
1124#endif
1125	eor	r10, r10, r4
1126	eor	r11, r11, r5
1127	and	r10, r10, r3
1128	and	r11, r11, r3
1129	eor	r4, r4, r10
1130	eor	r5, r5, r11
1131#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1132	ldr	r10, [r1, #40]
1133	ldr	r11, [r1, #44]
1134#else
1135	ldrd	r10, r11, [r1, #40]
1136#endif
1137	eor	r10, r10, r6
1138	eor	r11, r11, r7
1139	and	r10, r10, r3
1140	and	r11, r11, r3
1141	eor	r6, r6, r10
1142	eor	r7, r7, r11
1143#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1144	ldr	r10, [r1, #72]
1145	ldr	r11, [r1, #76]
1146#else
1147	ldrd	r10, r11, [r1, #72]
1148#endif
1149	eor	r10, r10, r8
1150	eor	r11, r11, r9
1151	and	r10, r10, r3
1152	and	r11, r11, r3
1153	eor	r8, r8, r10
1154	eor	r9, r9, r11
1155	add	r1, r1, #0x60
1156	mov	r3, #0x80000000
1157	ror	r3, r3, #27
1158	ror	r3, r3, r12
1159	asr	r3, r3, #31
1160#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1161	ldr	r10, [r1, #8]
1162	ldr	r11, [r1, #12]
1163#else
1164	ldrd	r10, r11, [r1, #8]
1165#endif
1166	eor	r10, r10, r4
1167	eor	r11, r11, r5
1168	and	r10, r10, r3
1169	and	r11, r11, r3
1170	eor	r4, r4, r10
1171	eor	r5, r5, r11
1172#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1173	ldr	r10, [r1, #40]
1174	ldr	r11, [r1, #44]
1175#else
1176	ldrd	r10, r11, [r1, #40]
1177#endif
1178	eor	r10, r10, r6
1179	eor	r11, r11, r7
1180	and	r10, r10, r3
1181	and	r11, r11, r3
1182	eor	r6, r6, r10
1183	eor	r7, r7, r11
1184#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1185	ldr	r10, [r1, #72]
1186	ldr	r11, [r1, #76]
1187#else
1188	ldrd	r10, r11, [r1, #72]
1189#endif
1190	eor	r10, r10, r8
1191	eor	r11, r11, r9
1192	and	r10, r10, r3
1193	and	r11, r11, r3
1194	eor	r8, r8, r10
1195	eor	r9, r9, r11
1196	add	r1, r1, #0x60
1197	mov	r3, #0x80000000
1198	ror	r3, r3, #26
1199	ror	r3, r3, r12
1200	asr	r3, r3, #31
1201#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1202	ldr	r10, [r1, #8]
1203	ldr	r11, [r1, #12]
1204#else
1205	ldrd	r10, r11, [r1, #8]
1206#endif
1207	eor	r10, r10, r4
1208	eor	r11, r11, r5
1209	and	r10, r10, r3
1210	and	r11, r11, r3
1211	eor	r4, r4, r10
1212	eor	r5, r5, r11
1213#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1214	ldr	r10, [r1, #40]
1215	ldr	r11, [r1, #44]
1216#else
1217	ldrd	r10, r11, [r1, #40]
1218#endif
1219	eor	r10, r10, r6
1220	eor	r11, r11, r7
1221	and	r10, r10, r3
1222	and	r11, r11, r3
1223	eor	r6, r6, r10
1224	eor	r7, r7, r11
1225#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1226	ldr	r10, [r1, #72]
1227	ldr	r11, [r1, #76]
1228#else
1229	ldrd	r10, r11, [r1, #72]
1230#endif
1231	eor	r10, r10, r8
1232	eor	r11, r11, r9
1233	and	r10, r10, r3
1234	and	r11, r11, r3
1235	eor	r8, r8, r10
1236	eor	r9, r9, r11
1237	add	r1, r1, #0x60
1238	mov	r3, #0x80000000
1239	ror	r3, r3, #25
1240	ror	r3, r3, r12
1241	asr	r3, r3, #31
1242#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1243	ldr	r10, [r1, #8]
1244	ldr	r11, [r1, #12]
1245#else
1246	ldrd	r10, r11, [r1, #8]
1247#endif
1248	eor	r10, r10, r4
1249	eor	r11, r11, r5
1250	and	r10, r10, r3
1251	and	r11, r11, r3
1252	eor	r4, r4, r10
1253	eor	r5, r5, r11
1254#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1255	ldr	r10, [r1, #40]
1256	ldr	r11, [r1, #44]
1257#else
1258	ldrd	r10, r11, [r1, #40]
1259#endif
1260	eor	r10, r10, r6
1261	eor	r11, r11, r7
1262	and	r10, r10, r3
1263	and	r11, r11, r3
1264	eor	r6, r6, r10
1265	eor	r7, r7, r11
1266#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1267	ldr	r10, [r1, #72]
1268	ldr	r11, [r1, #76]
1269#else
1270	ldrd	r10, r11, [r1, #72]
1271#endif
1272	eor	r10, r10, r8
1273	eor	r11, r11, r9
1274	and	r10, r10, r3
1275	and	r11, r11, r3
1276	eor	r8, r8, r10
1277	eor	r9, r9, r11
1278	add	r1, r1, #0x60
1279	mov	r3, #0x80000000
1280	ror	r3, r3, #24
1281	ror	r3, r3, r12
1282	asr	r3, r3, #31
1283#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1284	ldr	r10, [r1, #8]
1285	ldr	r11, [r1, #12]
1286#else
1287	ldrd	r10, r11, [r1, #8]
1288#endif
1289	eor	r10, r10, r4
1290	eor	r11, r11, r5
1291	and	r10, r10, r3
1292	and	r11, r11, r3
1293	eor	r4, r4, r10
1294	eor	r5, r5, r11
1295#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1296	ldr	r10, [r1, #40]
1297	ldr	r11, [r1, #44]
1298#else
1299	ldrd	r10, r11, [r1, #40]
1300#endif
1301	eor	r10, r10, r6
1302	eor	r11, r11, r7
1303	and	r10, r10, r3
1304	and	r11, r11, r3
1305	eor	r6, r6, r10
1306	eor	r7, r7, r11
1307#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1308	ldr	r10, [r1, #72]
1309	ldr	r11, [r1, #76]
1310#else
1311	ldrd	r10, r11, [r1, #72]
1312#endif
1313	eor	r10, r10, r8
1314	eor	r11, r11, r9
1315	and	r10, r10, r3
1316	and	r11, r11, r3
1317	eor	r8, r8, r10
1318	eor	r9, r9, r11
1319	sub	r1, r1, #0x2a0
1320	mvn	r10, #0
1321	mvn	r11, #0
1322	rsbs	lr, lr, #0
1323	sbcs	r10, r10, r8
1324	sbcs	r11, r11, r9
1325	sbc	lr, lr, lr
1326	asr	r12, r2, #31
1327	eor	r3, r4, r6
1328	and	r3, r3, r12
1329	eor	r4, r4, r3
1330	eor	r6, r6, r3
1331	eor	r3, r5, r7
1332	and	r3, r3, r12
1333	eor	r5, r5, r3
1334	eor	r7, r7, r3
1335	eor	r10, r10, r8
1336	and	r10, r10, r12
1337	eor	r8, r8, r10
1338	eor	r11, r11, r9
1339	and	r11, r11, r12
1340	eor	r9, r9, r11
1341#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1342	str	r4, [r0, #8]
1343	str	r5, [r0, #12]
1344#else
1345	strd	r4, r5, [r0, #8]
1346#endif
1347#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1348	str	r6, [r0, #40]
1349	str	r7, [r0, #44]
1350#else
1351	strd	r6, r7, [r0, #40]
1352#endif
1353#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1354	str	r8, [r0, #72]
1355	str	r9, [r0, #76]
1356#else
1357	strd	r8, r9, [r0, #72]
1358#endif
1359#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1360	lsl	r3, r2, #24
1361	asr	r3, r3, #31
1362#else
1363	sbfx	r3, r2, #7, #1
1364#endif
1365	eor	r12, r2, r3
1366	sub	r12, r12, r3
1367	mov	r4, #0
1368	mov	r5, #0
1369	mov	r6, #0
1370	mov	r7, #0
1371	mov	r8, #0
1372	mov	r9, #0
1373	mov	r3, #0x80000000
1374	ror	r3, r3, #31
1375	ror	r3, r3, r12
1376	asr	r3, r3, #31
1377#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1378	ldr	r10, [r1, #16]
1379	ldr	r11, [r1, #20]
1380#else
1381	ldrd	r10, r11, [r1, #16]
1382#endif
1383	eor	r10, r10, r4
1384	eor	r11, r11, r5
1385	and	r10, r10, r3
1386	and	r11, r11, r3
1387	eor	r4, r4, r10
1388	eor	r5, r5, r11
1389#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1390	ldr	r10, [r1, #48]
1391	ldr	r11, [r1, #52]
1392#else
1393	ldrd	r10, r11, [r1, #48]
1394#endif
1395	eor	r10, r10, r6
1396	eor	r11, r11, r7
1397	and	r10, r10, r3
1398	and	r11, r11, r3
1399	eor	r6, r6, r10
1400	eor	r7, r7, r11
1401#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1402	ldr	r10, [r1, #80]
1403	ldr	r11, [r1, #84]
1404#else
1405	ldrd	r10, r11, [r1, #80]
1406#endif
1407	eor	r10, r10, r8
1408	eor	r11, r11, r9
1409	and	r10, r10, r3
1410	and	r11, r11, r3
1411	eor	r8, r8, r10
1412	eor	r9, r9, r11
1413	add	r1, r1, #0x60
1414	mov	r3, #0x80000000
1415	ror	r3, r3, #30
1416	ror	r3, r3, r12
1417	asr	r3, r3, #31
1418#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1419	ldr	r10, [r1, #16]
1420	ldr	r11, [r1, #20]
1421#else
1422	ldrd	r10, r11, [r1, #16]
1423#endif
1424	eor	r10, r10, r4
1425	eor	r11, r11, r5
1426	and	r10, r10, r3
1427	and	r11, r11, r3
1428	eor	r4, r4, r10
1429	eor	r5, r5, r11
1430#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1431	ldr	r10, [r1, #48]
1432	ldr	r11, [r1, #52]
1433#else
1434	ldrd	r10, r11, [r1, #48]
1435#endif
1436	eor	r10, r10, r6
1437	eor	r11, r11, r7
1438	and	r10, r10, r3
1439	and	r11, r11, r3
1440	eor	r6, r6, r10
1441	eor	r7, r7, r11
1442#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1443	ldr	r10, [r1, #80]
1444	ldr	r11, [r1, #84]
1445#else
1446	ldrd	r10, r11, [r1, #80]
1447#endif
1448	eor	r10, r10, r8
1449	eor	r11, r11, r9
1450	and	r10, r10, r3
1451	and	r11, r11, r3
1452	eor	r8, r8, r10
1453	eor	r9, r9, r11
1454	add	r1, r1, #0x60
1455	mov	r3, #0x80000000
1456	ror	r3, r3, #29
1457	ror	r3, r3, r12
1458	asr	r3, r3, #31
1459#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1460	ldr	r10, [r1, #16]
1461	ldr	r11, [r1, #20]
1462#else
1463	ldrd	r10, r11, [r1, #16]
1464#endif
1465	eor	r10, r10, r4
1466	eor	r11, r11, r5
1467	and	r10, r10, r3
1468	and	r11, r11, r3
1469	eor	r4, r4, r10
1470	eor	r5, r5, r11
1471#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1472	ldr	r10, [r1, #48]
1473	ldr	r11, [r1, #52]
1474#else
1475	ldrd	r10, r11, [r1, #48]
1476#endif
1477	eor	r10, r10, r6
1478	eor	r11, r11, r7
1479	and	r10, r10, r3
1480	and	r11, r11, r3
1481	eor	r6, r6, r10
1482	eor	r7, r7, r11
1483#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1484	ldr	r10, [r1, #80]
1485	ldr	r11, [r1, #84]
1486#else
1487	ldrd	r10, r11, [r1, #80]
1488#endif
1489	eor	r10, r10, r8
1490	eor	r11, r11, r9
1491	and	r10, r10, r3
1492	and	r11, r11, r3
1493	eor	r8, r8, r10
1494	eor	r9, r9, r11
1495	add	r1, r1, #0x60
1496	mov	r3, #0x80000000
1497	ror	r3, r3, #28
1498	ror	r3, r3, r12
1499	asr	r3, r3, #31
1500#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1501	ldr	r10, [r1, #16]
1502	ldr	r11, [r1, #20]
1503#else
1504	ldrd	r10, r11, [r1, #16]
1505#endif
1506	eor	r10, r10, r4
1507	eor	r11, r11, r5
1508	and	r10, r10, r3
1509	and	r11, r11, r3
1510	eor	r4, r4, r10
1511	eor	r5, r5, r11
1512#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1513	ldr	r10, [r1, #48]
1514	ldr	r11, [r1, #52]
1515#else
1516	ldrd	r10, r11, [r1, #48]
1517#endif
1518	eor	r10, r10, r6
1519	eor	r11, r11, r7
1520	and	r10, r10, r3
1521	and	r11, r11, r3
1522	eor	r6, r6, r10
1523	eor	r7, r7, r11
1524#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1525	ldr	r10, [r1, #80]
1526	ldr	r11, [r1, #84]
1527#else
1528	ldrd	r10, r11, [r1, #80]
1529#endif
1530	eor	r10, r10, r8
1531	eor	r11, r11, r9
1532	and	r10, r10, r3
1533	and	r11, r11, r3
1534	eor	r8, r8, r10
1535	eor	r9, r9, r11
1536	add	r1, r1, #0x60
1537	mov	r3, #0x80000000
1538	ror	r3, r3, #27
1539	ror	r3, r3, r12
1540	asr	r3, r3, #31
1541#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1542	ldr	r10, [r1, #16]
1543	ldr	r11, [r1, #20]
1544#else
1545	ldrd	r10, r11, [r1, #16]
1546#endif
1547	eor	r10, r10, r4
1548	eor	r11, r11, r5
1549	and	r10, r10, r3
1550	and	r11, r11, r3
1551	eor	r4, r4, r10
1552	eor	r5, r5, r11
1553#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1554	ldr	r10, [r1, #48]
1555	ldr	r11, [r1, #52]
1556#else
1557	ldrd	r10, r11, [r1, #48]
1558#endif
1559	eor	r10, r10, r6
1560	eor	r11, r11, r7
1561	and	r10, r10, r3
1562	and	r11, r11, r3
1563	eor	r6, r6, r10
1564	eor	r7, r7, r11
1565#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1566	ldr	r10, [r1, #80]
1567	ldr	r11, [r1, #84]
1568#else
1569	ldrd	r10, r11, [r1, #80]
1570#endif
1571	eor	r10, r10, r8
1572	eor	r11, r11, r9
1573	and	r10, r10, r3
1574	and	r11, r11, r3
1575	eor	r8, r8, r10
1576	eor	r9, r9, r11
1577	add	r1, r1, #0x60
1578	mov	r3, #0x80000000
1579	ror	r3, r3, #26
1580	ror	r3, r3, r12
1581	asr	r3, r3, #31
1582#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1583	ldr	r10, [r1, #16]
1584	ldr	r11, [r1, #20]
1585#else
1586	ldrd	r10, r11, [r1, #16]
1587#endif
1588	eor	r10, r10, r4
1589	eor	r11, r11, r5
1590	and	r10, r10, r3
1591	and	r11, r11, r3
1592	eor	r4, r4, r10
1593	eor	r5, r5, r11
1594#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1595	ldr	r10, [r1, #48]
1596	ldr	r11, [r1, #52]
1597#else
1598	ldrd	r10, r11, [r1, #48]
1599#endif
1600	eor	r10, r10, r6
1601	eor	r11, r11, r7
1602	and	r10, r10, r3
1603	and	r11, r11, r3
1604	eor	r6, r6, r10
1605	eor	r7, r7, r11
1606#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1607	ldr	r10, [r1, #80]
1608	ldr	r11, [r1, #84]
1609#else
1610	ldrd	r10, r11, [r1, #80]
1611#endif
1612	eor	r10, r10, r8
1613	eor	r11, r11, r9
1614	and	r10, r10, r3
1615	and	r11, r11, r3
1616	eor	r8, r8, r10
1617	eor	r9, r9, r11
1618	add	r1, r1, #0x60
1619	mov	r3, #0x80000000
1620	ror	r3, r3, #25
1621	ror	r3, r3, r12
1622	asr	r3, r3, #31
1623#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1624	ldr	r10, [r1, #16]
1625	ldr	r11, [r1, #20]
1626#else
1627	ldrd	r10, r11, [r1, #16]
1628#endif
1629	eor	r10, r10, r4
1630	eor	r11, r11, r5
1631	and	r10, r10, r3
1632	and	r11, r11, r3
1633	eor	r4, r4, r10
1634	eor	r5, r5, r11
1635#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1636	ldr	r10, [r1, #48]
1637	ldr	r11, [r1, #52]
1638#else
1639	ldrd	r10, r11, [r1, #48]
1640#endif
1641	eor	r10, r10, r6
1642	eor	r11, r11, r7
1643	and	r10, r10, r3
1644	and	r11, r11, r3
1645	eor	r6, r6, r10
1646	eor	r7, r7, r11
1647#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1648	ldr	r10, [r1, #80]
1649	ldr	r11, [r1, #84]
1650#else
1651	ldrd	r10, r11, [r1, #80]
1652#endif
1653	eor	r10, r10, r8
1654	eor	r11, r11, r9
1655	and	r10, r10, r3
1656	and	r11, r11, r3
1657	eor	r8, r8, r10
1658	eor	r9, r9, r11
1659	add	r1, r1, #0x60
1660	mov	r3, #0x80000000
1661	ror	r3, r3, #24
1662	ror	r3, r3, r12
1663	asr	r3, r3, #31
1664#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1665	ldr	r10, [r1, #16]
1666	ldr	r11, [r1, #20]
1667#else
1668	ldrd	r10, r11, [r1, #16]
1669#endif
1670	eor	r10, r10, r4
1671	eor	r11, r11, r5
1672	and	r10, r10, r3
1673	and	r11, r11, r3
1674	eor	r4, r4, r10
1675	eor	r5, r5, r11
1676#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1677	ldr	r10, [r1, #48]
1678	ldr	r11, [r1, #52]
1679#else
1680	ldrd	r10, r11, [r1, #48]
1681#endif
1682	eor	r10, r10, r6
1683	eor	r11, r11, r7
1684	and	r10, r10, r3
1685	and	r11, r11, r3
1686	eor	r6, r6, r10
1687	eor	r7, r7, r11
1688#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1689	ldr	r10, [r1, #80]
1690	ldr	r11, [r1, #84]
1691#else
1692	ldrd	r10, r11, [r1, #80]
1693#endif
1694	eor	r10, r10, r8
1695	eor	r11, r11, r9
1696	and	r10, r10, r3
1697	and	r11, r11, r3
1698	eor	r8, r8, r10
1699	eor	r9, r9, r11
1700	sub	r1, r1, #0x2a0
1701	mvn	r10, #0
1702	mvn	r11, #0
1703	rsbs	lr, lr, #0
1704	sbcs	r10, r10, r8
1705	sbcs	r11, r11, r9
1706	sbc	lr, lr, lr
1707	asr	r12, r2, #31
1708	eor	r3, r4, r6
1709	and	r3, r3, r12
1710	eor	r4, r4, r3
1711	eor	r6, r6, r3
1712	eor	r3, r5, r7
1713	and	r3, r3, r12
1714	eor	r5, r5, r3
1715	eor	r7, r7, r3
1716	eor	r10, r10, r8
1717	and	r10, r10, r12
1718	eor	r8, r8, r10
1719	eor	r11, r11, r9
1720	and	r11, r11, r12
1721	eor	r9, r9, r11
1722#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1723	str	r4, [r0, #16]
1724	str	r5, [r0, #20]
1725#else
1726	strd	r4, r5, [r0, #16]
1727#endif
1728#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1729	str	r6, [r0, #48]
1730	str	r7, [r0, #52]
1731#else
1732	strd	r6, r7, [r0, #48]
1733#endif
1734#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1735	str	r8, [r0, #80]
1736	str	r9, [r0, #84]
1737#else
1738	strd	r8, r9, [r0, #80]
1739#endif
1740#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1741	lsl	r3, r2, #24
1742	asr	r3, r3, #31
1743#else
1744	sbfx	r3, r2, #7, #1
1745#endif
1746	eor	r12, r2, r3
1747	sub	r12, r12, r3
1748	mov	r4, #0
1749	mov	r5, #0
1750	mov	r6, #0
1751	mov	r7, #0
1752	mov	r8, #0
1753	mov	r9, #0
1754	mov	r3, #0x80000000
1755	ror	r3, r3, #31
1756	ror	r3, r3, r12
1757	asr	r3, r3, #31
1758#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1759	ldr	r10, [r1, #24]
1760	ldr	r11, [r1, #28]
1761#else
1762	ldrd	r10, r11, [r1, #24]
1763#endif
1764	eor	r10, r10, r4
1765	eor	r11, r11, r5
1766	and	r10, r10, r3
1767	and	r11, r11, r3
1768	eor	r4, r4, r10
1769	eor	r5, r5, r11
1770#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1771	ldr	r10, [r1, #56]
1772	ldr	r11, [r1, #60]
1773#else
1774	ldrd	r10, r11, [r1, #56]
1775#endif
1776	eor	r10, r10, r6
1777	eor	r11, r11, r7
1778	and	r10, r10, r3
1779	and	r11, r11, r3
1780	eor	r6, r6, r10
1781	eor	r7, r7, r11
1782#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1783	ldr	r10, [r1, #88]
1784	ldr	r11, [r1, #92]
1785#else
1786	ldrd	r10, r11, [r1, #88]
1787#endif
1788	eor	r10, r10, r8
1789	eor	r11, r11, r9
1790	and	r10, r10, r3
1791	and	r11, r11, r3
1792	eor	r8, r8, r10
1793	eor	r9, r9, r11
1794	add	r1, r1, #0x60
1795	mov	r3, #0x80000000
1796	ror	r3, r3, #30
1797	ror	r3, r3, r12
1798	asr	r3, r3, #31
1799#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1800	ldr	r10, [r1, #24]
1801	ldr	r11, [r1, #28]
1802#else
1803	ldrd	r10, r11, [r1, #24]
1804#endif
1805	eor	r10, r10, r4
1806	eor	r11, r11, r5
1807	and	r10, r10, r3
1808	and	r11, r11, r3
1809	eor	r4, r4, r10
1810	eor	r5, r5, r11
1811#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1812	ldr	r10, [r1, #56]
1813	ldr	r11, [r1, #60]
1814#else
1815	ldrd	r10, r11, [r1, #56]
1816#endif
1817	eor	r10, r10, r6
1818	eor	r11, r11, r7
1819	and	r10, r10, r3
1820	and	r11, r11, r3
1821	eor	r6, r6, r10
1822	eor	r7, r7, r11
1823#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1824	ldr	r10, [r1, #88]
1825	ldr	r11, [r1, #92]
1826#else
1827	ldrd	r10, r11, [r1, #88]
1828#endif
1829	eor	r10, r10, r8
1830	eor	r11, r11, r9
1831	and	r10, r10, r3
1832	and	r11, r11, r3
1833	eor	r8, r8, r10
1834	eor	r9, r9, r11
1835	add	r1, r1, #0x60
1836	mov	r3, #0x80000000
1837	ror	r3, r3, #29
1838	ror	r3, r3, r12
1839	asr	r3, r3, #31
1840#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1841	ldr	r10, [r1, #24]
1842	ldr	r11, [r1, #28]
1843#else
1844	ldrd	r10, r11, [r1, #24]
1845#endif
1846	eor	r10, r10, r4
1847	eor	r11, r11, r5
1848	and	r10, r10, r3
1849	and	r11, r11, r3
1850	eor	r4, r4, r10
1851	eor	r5, r5, r11
1852#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1853	ldr	r10, [r1, #56]
1854	ldr	r11, [r1, #60]
1855#else
1856	ldrd	r10, r11, [r1, #56]
1857#endif
1858	eor	r10, r10, r6
1859	eor	r11, r11, r7
1860	and	r10, r10, r3
1861	and	r11, r11, r3
1862	eor	r6, r6, r10
1863	eor	r7, r7, r11
1864#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1865	ldr	r10, [r1, #88]
1866	ldr	r11, [r1, #92]
1867#else
1868	ldrd	r10, r11, [r1, #88]
1869#endif
1870	eor	r10, r10, r8
1871	eor	r11, r11, r9
1872	and	r10, r10, r3
1873	and	r11, r11, r3
1874	eor	r8, r8, r10
1875	eor	r9, r9, r11
1876	add	r1, r1, #0x60
1877	mov	r3, #0x80000000
1878	ror	r3, r3, #28
1879	ror	r3, r3, r12
1880	asr	r3, r3, #31
1881#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1882	ldr	r10, [r1, #24]
1883	ldr	r11, [r1, #28]
1884#else
1885	ldrd	r10, r11, [r1, #24]
1886#endif
1887	eor	r10, r10, r4
1888	eor	r11, r11, r5
1889	and	r10, r10, r3
1890	and	r11, r11, r3
1891	eor	r4, r4, r10
1892	eor	r5, r5, r11
1893#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1894	ldr	r10, [r1, #56]
1895	ldr	r11, [r1, #60]
1896#else
1897	ldrd	r10, r11, [r1, #56]
1898#endif
1899	eor	r10, r10, r6
1900	eor	r11, r11, r7
1901	and	r10, r10, r3
1902	and	r11, r11, r3
1903	eor	r6, r6, r10
1904	eor	r7, r7, r11
1905#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1906	ldr	r10, [r1, #88]
1907	ldr	r11, [r1, #92]
1908#else
1909	ldrd	r10, r11, [r1, #88]
1910#endif
1911	eor	r10, r10, r8
1912	eor	r11, r11, r9
1913	and	r10, r10, r3
1914	and	r11, r11, r3
1915	eor	r8, r8, r10
1916	eor	r9, r9, r11
1917	add	r1, r1, #0x60
1918	mov	r3, #0x80000000
1919	ror	r3, r3, #27
1920	ror	r3, r3, r12
1921	asr	r3, r3, #31
1922#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1923	ldr	r10, [r1, #24]
1924	ldr	r11, [r1, #28]
1925#else
1926	ldrd	r10, r11, [r1, #24]
1927#endif
1928	eor	r10, r10, r4
1929	eor	r11, r11, r5
1930	and	r10, r10, r3
1931	and	r11, r11, r3
1932	eor	r4, r4, r10
1933	eor	r5, r5, r11
1934#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1935	ldr	r10, [r1, #56]
1936	ldr	r11, [r1, #60]
1937#else
1938	ldrd	r10, r11, [r1, #56]
1939#endif
1940	eor	r10, r10, r6
1941	eor	r11, r11, r7
1942	and	r10, r10, r3
1943	and	r11, r11, r3
1944	eor	r6, r6, r10
1945	eor	r7, r7, r11
1946#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1947	ldr	r10, [r1, #88]
1948	ldr	r11, [r1, #92]
1949#else
1950	ldrd	r10, r11, [r1, #88]
1951#endif
1952	eor	r10, r10, r8
1953	eor	r11, r11, r9
1954	and	r10, r10, r3
1955	and	r11, r11, r3
1956	eor	r8, r8, r10
1957	eor	r9, r9, r11
1958	add	r1, r1, #0x60
1959	mov	r3, #0x80000000
1960	ror	r3, r3, #26
1961	ror	r3, r3, r12
1962	asr	r3, r3, #31
1963#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1964	ldr	r10, [r1, #24]
1965	ldr	r11, [r1, #28]
1966#else
1967	ldrd	r10, r11, [r1, #24]
1968#endif
1969	eor	r10, r10, r4
1970	eor	r11, r11, r5
1971	and	r10, r10, r3
1972	and	r11, r11, r3
1973	eor	r4, r4, r10
1974	eor	r5, r5, r11
1975#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1976	ldr	r10, [r1, #56]
1977	ldr	r11, [r1, #60]
1978#else
1979	ldrd	r10, r11, [r1, #56]
1980#endif
1981	eor	r10, r10, r6
1982	eor	r11, r11, r7
1983	and	r10, r10, r3
1984	and	r11, r11, r3
1985	eor	r6, r6, r10
1986	eor	r7, r7, r11
1987#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
1988	ldr	r10, [r1, #88]
1989	ldr	r11, [r1, #92]
1990#else
1991	ldrd	r10, r11, [r1, #88]
1992#endif
1993	eor	r10, r10, r8
1994	eor	r11, r11, r9
1995	and	r10, r10, r3
1996	and	r11, r11, r3
1997	eor	r8, r8, r10
1998	eor	r9, r9, r11
1999	add	r1, r1, #0x60
2000	mov	r3, #0x80000000
2001	ror	r3, r3, #25
2002	ror	r3, r3, r12
2003	asr	r3, r3, #31
2004#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2005	ldr	r10, [r1, #24]
2006	ldr	r11, [r1, #28]
2007#else
2008	ldrd	r10, r11, [r1, #24]
2009#endif
2010	eor	r10, r10, r4
2011	eor	r11, r11, r5
2012	and	r10, r10, r3
2013	and	r11, r11, r3
2014	eor	r4, r4, r10
2015	eor	r5, r5, r11
2016#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2017	ldr	r10, [r1, #56]
2018	ldr	r11, [r1, #60]
2019#else
2020	ldrd	r10, r11, [r1, #56]
2021#endif
2022	eor	r10, r10, r6
2023	eor	r11, r11, r7
2024	and	r10, r10, r3
2025	and	r11, r11, r3
2026	eor	r6, r6, r10
2027	eor	r7, r7, r11
2028#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2029	ldr	r10, [r1, #88]
2030	ldr	r11, [r1, #92]
2031#else
2032	ldrd	r10, r11, [r1, #88]
2033#endif
2034	eor	r10, r10, r8
2035	eor	r11, r11, r9
2036	and	r10, r10, r3
2037	and	r11, r11, r3
2038	eor	r8, r8, r10
2039	eor	r9, r9, r11
2040	add	r1, r1, #0x60
2041	mov	r3, #0x80000000
2042	ror	r3, r3, #24
2043	ror	r3, r3, r12
2044	asr	r3, r3, #31
2045#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2046	ldr	r10, [r1, #24]
2047	ldr	r11, [r1, #28]
2048#else
2049	ldrd	r10, r11, [r1, #24]
2050#endif
2051	eor	r10, r10, r4
2052	eor	r11, r11, r5
2053	and	r10, r10, r3
2054	and	r11, r11, r3
2055	eor	r4, r4, r10
2056	eor	r5, r5, r11
2057#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2058	ldr	r10, [r1, #56]
2059	ldr	r11, [r1, #60]
2060#else
2061	ldrd	r10, r11, [r1, #56]
2062#endif
2063	eor	r10, r10, r6
2064	eor	r11, r11, r7
2065	and	r10, r10, r3
2066	and	r11, r11, r3
2067	eor	r6, r6, r10
2068	eor	r7, r7, r11
2069#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2070	ldr	r10, [r1, #88]
2071	ldr	r11, [r1, #92]
2072#else
2073	ldrd	r10, r11, [r1, #88]
2074#endif
2075	eor	r10, r10, r8
2076	eor	r11, r11, r9
2077	and	r10, r10, r3
2078	and	r11, r11, r3
2079	eor	r8, r8, r10
2080	eor	r9, r9, r11
2081	sub	r1, r1, #0x2a0
2082	mvn	r10, #0
2083	mvn	r11, #0x80000000
2084	rsbs	lr, lr, #0
2085	sbcs	r10, r10, r8
2086	sbc	r11, r11, r9
2087	asr	r12, r2, #31
2088	eor	r3, r4, r6
2089	and	r3, r3, r12
2090	eor	r4, r4, r3
2091	eor	r6, r6, r3
2092	eor	r3, r5, r7
2093	and	r3, r3, r12
2094	eor	r5, r5, r3
2095	eor	r7, r7, r3
2096	eor	r10, r10, r8
2097	and	r10, r10, r12
2098	eor	r8, r8, r10
2099	eor	r11, r11, r9
2100	and	r11, r11, r12
2101	eor	r9, r9, r11
2102#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2103	str	r4, [r0, #24]
2104	str	r5, [r0, #28]
2105#else
2106	strd	r4, r5, [r0, #24]
2107#endif
2108#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2109	str	r6, [r0, #56]
2110	str	r7, [r0, #60]
2111#else
2112	strd	r6, r7, [r0, #56]
2113#endif
2114#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2115	str	r8, [r0, #88]
2116	str	r9, [r0, #92]
2117#else
2118	strd	r8, r9, [r0, #88]
2119#endif
2120	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2121	.size	fe_cmov_table,.-fe_cmov_table
2122#else
2123	.text
2124	.align	4
2125	.globl	fe_cmov_table
2126	.type	fe_cmov_table, %function
2127fe_cmov_table:
2128	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2129#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
2130	lsl	r2, r2, #24
2131	asr	r2, r2, #24
2132#else
2133	sxtb	r2, r2
2134#endif
2135#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2136	lsl	r3, r2, #24
2137	asr	r3, r3, #31
2138#else
2139	sbfx	r3, r2, #7, #1
2140#endif
2141	eor	r2, r2, r3
2142	sub	r2, r2, r3
2143#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
2144	sub	lr, r2, #1
2145#else
2146	clz	lr, r2
2147	lsl	lr, lr, #26
2148#endif /* defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6) */
2149	asr	lr, lr, #31
2150	mvn	lr, lr
2151	add	r2, r2, lr
2152	mov	r12, #0x60
2153	mul	r2, r2, r12
2154	add	r1, r1, r2
2155	ldm	r1!, {r4, r5, r6, r7, r8, r9, r10, r11}
2156	and	r4, r4, lr
2157	and	r5, r5, lr
2158	and	r6, r6, lr
2159	and	r7, r7, lr
2160	and	r8, r8, lr
2161	and	r9, r9, lr
2162	and	r10, r10, lr
2163	and	r11, r11, lr
2164	mvn	r12, lr
2165	sub	r4, r4, r12
2166	mov	r12, #32
2167	and	r12, r12, r3
2168	add	r0, r0, r12
2169	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
2170	sub	r0, r0, r12
2171	ldm	r1!, {r4, r5, r6, r7, r8, r9, r10, r11}
2172	and	r4, r4, lr
2173	and	r5, r5, lr
2174	and	r6, r6, lr
2175	and	r7, r7, lr
2176	and	r8, r8, lr
2177	and	r9, r9, lr
2178	and	r10, r10, lr
2179	and	r11, r11, lr
2180	mvn	r12, lr
2181	sub	r4, r4, r12
2182	mov	r12, #32
2183	bic	r12, r12, r3
2184	add	r0, r0, r12
2185	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
2186	sub	r0, r0, r12
2187	add	r0, r0, #0x40
2188	ldm	r1!, {r4, r5, r6, r7}
2189	mvn	r12, #18
2190	subs	r8, r12, r4
2191	sbcs	r9, r3, r5
2192	sbcs	r10, r3, r6
2193	sbcs	r11, r3, r7
2194	bic	r4, r4, r3
2195	bic	r5, r5, r3
2196	bic	r6, r6, r3
2197	bic	r7, r7, r3
2198	and	r8, r8, r3
2199	and	r9, r9, r3
2200	and	r10, r10, r3
2201	and	r11, r11, r3
2202	orr	r4, r4, r8
2203	orr	r5, r5, r9
2204	orr	r6, r6, r10
2205	orr	r7, r7, r11
2206	and	r4, r4, lr
2207	and	r5, r5, lr
2208	and	r6, r6, lr
2209	and	r7, r7, lr
2210	stm	r0!, {r4, r5, r6, r7}
2211	ldm	r1!, {r4, r5, r6, r7}
2212	mvn	r12, #0x80000000
2213	sbcs	r8, r3, r4
2214	sbcs	r9, r3, r5
2215	sbcs	r10, r3, r6
2216	sbc	r11, r12, r7
2217	bic	r4, r4, r3
2218	bic	r5, r5, r3
2219	bic	r6, r6, r3
2220	bic	r7, r7, r3
2221	and	r8, r8, r3
2222	and	r9, r9, r3
2223	and	r10, r10, r3
2224	and	r11, r11, r3
2225	orr	r4, r4, r8
2226	orr	r5, r5, r9
2227	orr	r6, r6, r10
2228	orr	r7, r7, r11
2229	and	r4, r4, lr
2230	and	r5, r5, lr
2231	and	r6, r6, lr
2232	and	r7, r7, lr
2233	stm	r0!, {r4, r5, r6, r7}
2234	sub	r1, r1, r2
2235	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2236	.size	fe_cmov_table,.-fe_cmov_table
2237#endif /* WC_NO_CACHE_RESISTANT */
2238#endif /* HAVE_ED25519_MAKE_KEY || HAVE_ED25519_SIGN || WOLFSSL_CURVE25519_USE_ED25519 */
2239#endif /* HAVE_ED25519 || WOLFSSL_CURVE25519_USE_ED25519 */
2240#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
2241	.text
2242	.align	4
2243	.globl	fe_mul_op
2244	.type	fe_mul_op, %function
2245fe_mul_op:
2246	push	{lr}
2247	sub	sp, sp, #40
2248	str	r0, [sp, #36]
2249	mov	r0, #0
2250	ldr	r12, [r1]
2251	# A[0] * B[0]
2252	ldr	lr, [r2]
2253	umull	r3, r4, r12, lr
2254	# A[0] * B[2]
2255	ldr	lr, [r2, #8]
2256	umull	r5, r6, r12, lr
2257	# A[0] * B[4]
2258	ldr	lr, [r2, #16]
2259	umull	r7, r8, r12, lr
2260	# A[0] * B[6]
2261	ldr	lr, [r2, #24]
2262	umull	r9, r10, r12, lr
2263	str	r3, [sp]
2264	# A[0] * B[1]
2265	ldr	lr, [r2, #4]
2266	mov	r11, r0
2267	umlal	r4, r11, r12, lr
2268	adds	r5, r5, r11
2269	# A[0] * B[3]
2270	ldr	lr, [r2, #12]
2271	adcs	r6, r6, #0
2272	adc	r11, r0, #0
2273	umlal	r6, r11, r12, lr
2274	adds	r7, r7, r11
2275	# A[0] * B[5]
2276	ldr	lr, [r2, #20]
2277	adcs	r8, r8, #0
2278	adc	r11, r0, #0
2279	umlal	r8, r11, r12, lr
2280	adds	r9, r9, r11
2281	# A[0] * B[7]
2282	ldr	lr, [r2, #28]
2283	adcs	r10, r10, #0
2284	adc	r3, r0, #0
2285	umlal	r10, r3, r12, lr
2286	# A[1] * B[0]
2287	ldr	r12, [r1, #4]
2288	ldr	lr, [r2]
2289	mov	r11, #0
2290	umlal	r4, r11, r12, lr
2291	str	r4, [sp, #4]
2292	adds	r5, r5, r11
2293	# A[1] * B[1]
2294	ldr	lr, [r2, #4]
2295	adc	r11, r0, #0
2296	umlal	r5, r11, r12, lr
2297	adds	r6, r6, r11
2298	# A[1] * B[2]
2299	ldr	lr, [r2, #8]
2300	adc	r11, r0, #0
2301	umlal	r6, r11, r12, lr
2302	adds	r7, r7, r11
2303	# A[1] * B[3]
2304	ldr	lr, [r2, #12]
2305	adc	r11, r0, #0
2306	umlal	r7, r11, r12, lr
2307	adds	r8, r8, r11
2308	# A[1] * B[4]
2309	ldr	lr, [r2, #16]
2310	adc	r11, r0, #0
2311	umlal	r8, r11, r12, lr
2312	adds	r9, r9, r11
2313	# A[1] * B[5]
2314	ldr	lr, [r2, #20]
2315	adc	r11, r0, #0
2316	umlal	r9, r11, r12, lr
2317	adds	r10, r10, r11
2318	# A[1] * B[6]
2319	ldr	lr, [r2, #24]
2320	adc	r11, r0, #0
2321	umlal	r10, r11, r12, lr
2322	adds	r3, r3, r11
2323	# A[1] * B[7]
2324	ldr	lr, [r2, #28]
2325	adc	r4, r0, #0
2326	umlal	r3, r4, r12, lr
2327	# A[2] * B[0]
2328	ldr	r12, [r1, #8]
2329	ldr	lr, [r2]
2330	mov	r11, #0
2331	umlal	r5, r11, r12, lr
2332	str	r5, [sp, #8]
2333	adds	r6, r6, r11
2334	# A[2] * B[1]
2335	ldr	lr, [r2, #4]
2336	adc	r11, r0, #0
2337	umlal	r6, r11, r12, lr
2338	adds	r7, r7, r11
2339	# A[2] * B[2]
2340	ldr	lr, [r2, #8]
2341	adc	r11, r0, #0
2342	umlal	r7, r11, r12, lr
2343	adds	r8, r8, r11
2344	# A[2] * B[3]
2345	ldr	lr, [r2, #12]
2346	adc	r11, r0, #0
2347	umlal	r8, r11, r12, lr
2348	adds	r9, r9, r11
2349	# A[2] * B[4]
2350	ldr	lr, [r2, #16]
2351	adc	r11, r0, #0
2352	umlal	r9, r11, r12, lr
2353	adds	r10, r10, r11
2354	# A[2] * B[5]
2355	ldr	lr, [r2, #20]
2356	adc	r11, r0, #0
2357	umlal	r10, r11, r12, lr
2358	adds	r3, r3, r11
2359	# A[2] * B[6]
2360	ldr	lr, [r2, #24]
2361	adc	r11, r0, #0
2362	umlal	r3, r11, r12, lr
2363	adds	r4, r4, r11
2364	# A[2] * B[7]
2365	ldr	lr, [r2, #28]
2366	adc	r5, r0, #0
2367	umlal	r4, r5, r12, lr
2368	# A[3] * B[0]
2369	ldr	r12, [r1, #12]
2370	ldr	lr, [r2]
2371	mov	r11, #0
2372	umlal	r6, r11, r12, lr
2373	str	r6, [sp, #12]
2374	adds	r7, r7, r11
2375	# A[3] * B[1]
2376	ldr	lr, [r2, #4]
2377	adc	r11, r0, #0
2378	umlal	r7, r11, r12, lr
2379	adds	r8, r8, r11
2380	# A[3] * B[2]
2381	ldr	lr, [r2, #8]
2382	adc	r11, r0, #0
2383	umlal	r8, r11, r12, lr
2384	adds	r9, r9, r11
2385	# A[3] * B[3]
2386	ldr	lr, [r2, #12]
2387	adc	r11, r0, #0
2388	umlal	r9, r11, r12, lr
2389	adds	r10, r10, r11
2390	# A[3] * B[4]
2391	ldr	lr, [r2, #16]
2392	adc	r11, r0, #0
2393	umlal	r10, r11, r12, lr
2394	adds	r3, r3, r11
2395	# A[3] * B[5]
2396	ldr	lr, [r2, #20]
2397	adc	r11, r0, #0
2398	umlal	r3, r11, r12, lr
2399	adds	r4, r4, r11
2400	# A[3] * B[6]
2401	ldr	lr, [r2, #24]
2402	adc	r11, r0, #0
2403	umlal	r4, r11, r12, lr
2404	adds	r5, r5, r11
2405	# A[3] * B[7]
2406	ldr	lr, [r2, #28]
2407	adc	r6, r0, #0
2408	umlal	r5, r6, r12, lr
2409	# A[4] * B[0]
2410	ldr	r12, [r1, #16]
2411	ldr	lr, [r2]
2412	mov	r11, #0
2413	umlal	r7, r11, r12, lr
2414	str	r7, [sp, #16]
2415	adds	r8, r8, r11
2416	# A[4] * B[1]
2417	ldr	lr, [r2, #4]
2418	adc	r11, r0, #0
2419	umlal	r8, r11, r12, lr
2420	adds	r9, r9, r11
2421	# A[4] * B[2]
2422	ldr	lr, [r2, #8]
2423	adc	r11, r0, #0
2424	umlal	r9, r11, r12, lr
2425	adds	r10, r10, r11
2426	# A[4] * B[3]
2427	ldr	lr, [r2, #12]
2428	adc	r11, r0, #0
2429	umlal	r10, r11, r12, lr
2430	adds	r3, r3, r11
2431	# A[4] * B[4]
2432	ldr	lr, [r2, #16]
2433	adc	r11, r0, #0
2434	umlal	r3, r11, r12, lr
2435	adds	r4, r4, r11
2436	# A[4] * B[5]
2437	ldr	lr, [r2, #20]
2438	adc	r11, r0, #0
2439	umlal	r4, r11, r12, lr
2440	adds	r5, r5, r11
2441	# A[4] * B[6]
2442	ldr	lr, [r2, #24]
2443	adc	r11, r0, #0
2444	umlal	r5, r11, r12, lr
2445	adds	r6, r6, r11
2446	# A[4] * B[7]
2447	ldr	lr, [r2, #28]
2448	adc	r7, r0, #0
2449	umlal	r6, r7, r12, lr
2450	# A[5] * B[0]
2451	ldr	r12, [r1, #20]
2452	ldr	lr, [r2]
2453	mov	r11, #0
2454	umlal	r8, r11, r12, lr
2455	str	r8, [sp, #20]
2456	adds	r9, r9, r11
2457	# A[5] * B[1]
2458	ldr	lr, [r2, #4]
2459	adc	r11, r0, #0
2460	umlal	r9, r11, r12, lr
2461	adds	r10, r10, r11
2462	# A[5] * B[2]
2463	ldr	lr, [r2, #8]
2464	adc	r11, r0, #0
2465	umlal	r10, r11, r12, lr
2466	adds	r3, r3, r11
2467	# A[5] * B[3]
2468	ldr	lr, [r2, #12]
2469	adc	r11, r0, #0
2470	umlal	r3, r11, r12, lr
2471	adds	r4, r4, r11
2472	# A[5] * B[4]
2473	ldr	lr, [r2, #16]
2474	adc	r11, r0, #0
2475	umlal	r4, r11, r12, lr
2476	adds	r5, r5, r11
2477	# A[5] * B[5]
2478	ldr	lr, [r2, #20]
2479	adc	r11, r0, #0
2480	umlal	r5, r11, r12, lr
2481	adds	r6, r6, r11
2482	# A[5] * B[6]
2483	ldr	lr, [r2, #24]
2484	adc	r11, r0, #0
2485	umlal	r6, r11, r12, lr
2486	adds	r7, r7, r11
2487	# A[5] * B[7]
2488	ldr	lr, [r2, #28]
2489	adc	r8, r0, #0
2490	umlal	r7, r8, r12, lr
2491	# A[6] * B[0]
2492	ldr	r12, [r1, #24]
2493	ldr	lr, [r2]
2494	mov	r11, #0
2495	umlal	r9, r11, r12, lr
2496	str	r9, [sp, #24]
2497	adds	r10, r10, r11
2498	# A[6] * B[1]
2499	ldr	lr, [r2, #4]
2500	adc	r11, r0, #0
2501	umlal	r10, r11, r12, lr
2502	adds	r3, r3, r11
2503	# A[6] * B[2]
2504	ldr	lr, [r2, #8]
2505	adc	r11, r0, #0
2506	umlal	r3, r11, r12, lr
2507	adds	r4, r4, r11
2508	# A[6] * B[3]
2509	ldr	lr, [r2, #12]
2510	adc	r11, r0, #0
2511	umlal	r4, r11, r12, lr
2512	adds	r5, r5, r11
2513	# A[6] * B[4]
2514	ldr	lr, [r2, #16]
2515	adc	r11, r0, #0
2516	umlal	r5, r11, r12, lr
2517	adds	r6, r6, r11
2518	# A[6] * B[5]
2519	ldr	lr, [r2, #20]
2520	adc	r11, r0, #0
2521	umlal	r6, r11, r12, lr
2522	adds	r7, r7, r11
2523	# A[6] * B[6]
2524	ldr	lr, [r2, #24]
2525	adc	r11, r0, #0
2526	umlal	r7, r11, r12, lr
2527	adds	r8, r8, r11
2528	# A[6] * B[7]
2529	ldr	lr, [r2, #28]
2530	adc	r9, r0, #0
2531	umlal	r8, r9, r12, lr
2532	# A[7] * B[0]
2533	ldr	r12, [r1, #28]
2534	ldr	lr, [r2]
2535	mov	r11, #0
2536	umlal	r10, r11, r12, lr
2537	str	r10, [sp, #28]
2538	adds	r3, r3, r11
2539	# A[7] * B[1]
2540	ldr	lr, [r2, #4]
2541	adc	r11, r0, #0
2542	umlal	r3, r11, r12, lr
2543	adds	r4, r4, r11
2544	# A[7] * B[2]
2545	ldr	lr, [r2, #8]
2546	adc	r11, r0, #0
2547	umlal	r4, r11, r12, lr
2548	adds	r5, r5, r11
2549	# A[7] * B[3]
2550	ldr	lr, [r2, #12]
2551	adc	r11, r0, #0
2552	umlal	r5, r11, r12, lr
2553	adds	r6, r6, r11
2554	# A[7] * B[4]
2555	ldr	lr, [r2, #16]
2556	adc	r11, r0, #0
2557	umlal	r6, r11, r12, lr
2558	adds	r7, r7, r11
2559	# A[7] * B[5]
2560	ldr	lr, [r2, #20]
2561	adc	r11, r0, #0
2562	umlal	r7, r11, r12, lr
2563	adds	r8, r8, r11
2564	# A[7] * B[6]
2565	ldr	lr, [r2, #24]
2566	adc	r11, r0, #0
2567	umlal	r8, r11, r12, lr
2568	adds	r9, r9, r11
2569	# A[7] * B[7]
2570	ldr	lr, [r2, #28]
2571	adc	r10, r0, #0
2572	umlal	r9, r10, r12, lr
2573	# Reduce
2574	ldr	r2, [sp, #28]
2575	mov	lr, sp
2576	mov	r12, #38
2577	umull	r10, r11, r12, r10
2578	adds	r10, r10, r2
2579	adc	r11, r11, #0
2580	mov	r12, #19
2581	lsl	r11, r11, #1
2582	orr	r11, r11, r10, lsr #31
2583	mul	r11, r12, r11
2584	ldm	lr!, {r1, r2}
2585	mov	r12, #38
2586	adds	r1, r1, r11
2587	adc	r11, r0, #0
2588	umlal	r1, r11, r3, r12
2589	adds	r2, r2, r11
2590	adc	r11, r0, #0
2591	umlal	r2, r11, r4, r12
2592	ldm	lr!, {r3, r4}
2593	adds	r3, r3, r11
2594	adc	r11, r0, #0
2595	umlal	r3, r11, r5, r12
2596	adds	r4, r4, r11
2597	adc	r11, r0, #0
2598	umlal	r4, r11, r6, r12
2599	ldm	lr!, {r5, r6}
2600	adds	r5, r5, r11
2601	adc	r11, r0, #0
2602	umlal	r5, r11, r7, r12
2603	adds	r6, r6, r11
2604	adc	r11, r0, #0
2605	umlal	r6, r11, r8, r12
2606	ldm	lr!, {r7, r8}
2607	adds	r7, r7, r11
2608	adc	r11, r0, #0
2609	umlal	r7, r11, r9, r12
2610#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2611	bic	r10, r10, #0x80000000
2612#else
2613	bfc	r10, #31, #1
2614#endif
2615	adds	r8, r10, r11
2616	# Store
2617	ldr	r0, [sp, #36]
2618	stm	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
2619	add	sp, sp, #40
2620	pop	{pc}
2621	.size	fe_mul_op,.-fe_mul_op
2622#else
2623	.text
2624	.align	4
2625	.globl	fe_mul_op
2626	.type	fe_mul_op, %function
2627fe_mul_op:
2628	push	{lr}
2629	sub	sp, sp, #44
2630#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2631	str	r0, [sp, #36]
2632	str	r1, [sp, #40]
2633#else
2634	strd	r0, r1, [sp, #36]
2635#endif
2636	mov	lr, r2
2637	ldm	r1, {r0, r1, r2, r3}
2638	ldm	lr!, {r4, r5, r6}
2639	umull	r10, r11, r0, r4
2640	umull	r12, r7, r1, r4
2641	umaal	r11, r12, r0, r5
2642	umull	r8, r9, r2, r4
2643	umaal	r12, r8, r1, r5
2644	umaal	r12, r7, r0, r6
2645	umaal	r8, r9, r3, r4
2646	stm	sp, {r10, r11, r12}
2647	umaal	r7, r8, r2, r5
2648	ldm	lr!, {r4}
2649	umull	r10, r11, r1, r6
2650	umaal	r8, r9, r2, r6
2651	umaal	r7, r10, r0, r4
2652	umaal	r8, r11, r3, r5
2653	str	r7, [sp, #12]
2654	umaal	r8, r10, r1, r4
2655	umaal	r9, r11, r3, r6
2656	umaal	r9, r10, r2, r4
2657	umaal	r10, r11, r3, r4
2658	ldm	lr, {r4, r5, r6, r7}
2659	mov	r12, #0
2660	umlal	r8, r12, r0, r4
2661	umaal	r9, r12, r1, r4
2662	umaal	r10, r12, r2, r4
2663	umaal	r11, r12, r3, r4
2664	mov	r4, #0
2665	umlal	r9, r4, r0, r5
2666	umaal	r10, r4, r1, r5
2667	umaal	r11, r4, r2, r5
2668	umaal	r12, r4, r3, r5
2669	mov	r5, #0
2670	umlal	r10, r5, r0, r6
2671	umaal	r11, r5, r1, r6
2672	umaal	r12, r5, r2, r6
2673	umaal	r4, r5, r3, r6
2674	mov	r6, #0
2675	umlal	r11, r6, r0, r7
2676	ldr	r0, [sp, #40]
2677	umaal	r12, r6, r1, r7
2678	add	r0, r0, #16
2679	umaal	r4, r6, r2, r7
2680	sub	lr, lr, #16
2681	umaal	r5, r6, r3, r7
2682	ldm	r0, {r0, r1, r2, r3}
2683	str	r6, [sp, #32]
2684	ldm	lr!, {r6}
2685	mov	r7, #0
2686	umlal	r8, r7, r0, r6
2687	umaal	r9, r7, r1, r6
2688	str	r8, [sp, #16]
2689	umaal	r10, r7, r2, r6
2690	umaal	r11, r7, r3, r6
2691	ldm	lr!, {r6}
2692	mov	r8, #0
2693	umlal	r9, r8, r0, r6
2694	umaal	r10, r8, r1, r6
2695	str	r9, [sp, #20]
2696	umaal	r11, r8, r2, r6
2697	umaal	r12, r8, r3, r6
2698	ldm	lr!, {r6}
2699	mov	r9, #0
2700	umlal	r10, r9, r0, r6
2701	umaal	r11, r9, r1, r6
2702	str	r10, [sp, #24]
2703	umaal	r12, r9, r2, r6
2704	umaal	r4, r9, r3, r6
2705	ldm	lr!, {r6}
2706	mov	r10, #0
2707	umlal	r11, r10, r0, r6
2708	umaal	r12, r10, r1, r6
2709	str	r11, [sp, #28]
2710	umaal	r4, r10, r2, r6
2711	umaal	r5, r10, r3, r6
2712	ldm	lr!, {r11}
2713	umaal	r12, r7, r0, r11
2714	umaal	r4, r7, r1, r11
2715	ldr	r6, [sp, #32]
2716	umaal	r5, r7, r2, r11
2717	umaal	r6, r7, r3, r11
2718	ldm	lr!, {r11}
2719	umaal	r4, r8, r0, r11
2720	umaal	r5, r8, r1, r11
2721	umaal	r6, r8, r2, r11
2722	umaal	r7, r8, r3, r11
2723	ldm	lr, {r11, lr}
2724	umaal	r5, r9, r0, r11
2725	umaal	r6, r10, r0, lr
2726	umaal	r6, r9, r1, r11
2727	umaal	r7, r10, r1, lr
2728	umaal	r7, r9, r2, r11
2729	umaal	r8, r10, r2, lr
2730	umaal	r8, r9, r3, r11
2731	umaal	r9, r10, r3, lr
2732	# Reduce
2733	ldr	r0, [sp, #28]
2734	mov	lr, #37
2735	umaal	r10, r0, r10, lr
2736	mov	lr, #19
2737	lsl	r0, r0, #1
2738	orr	r0, r0, r10, lsr #31
2739	mul	r11, r0, lr
2740	pop	{r0-r2}
2741	mov	lr, #38
2742	umaal	r0, r11, r12, lr
2743	umaal	r1, r11, r4, lr
2744	umaal	r2, r11, r5, lr
2745	pop	{r3-r5}
2746	umaal	r3, r11, r6, lr
2747	umaal	r4, r11, r7, lr
2748	umaal	r5, r11, r8, lr
2749	pop	{r6}
2750#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
2751	bic	r10, r10, #0x80000000
2752#else
2753	bfc	r10, #31, #1
2754#endif
2755	umaal	r6, r11, r9, lr
2756	add	r7, r10, r11
2757	ldr	lr, [sp, #8]
2758	# Store
2759	stm	lr, {r0, r1, r2, r3, r4, r5, r6, r7}
2760	add	sp, sp, #16
2761	pop	{pc}
2762	.size	fe_mul_op,.-fe_mul_op
2763#endif /* WOLFSSL_ARM_ARCH && WOLFSSL_ARM_ARCH < 6 */
2764	.text
2765	.align	4
2766	.globl	fe_mul
2767	.type	fe_mul, %function
2768fe_mul:
2769	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2770	bl	fe_mul_op
2771	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2772	.size	fe_mul,.-fe_mul
2773#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
2774	.text
2775	.align	4
2776	.globl	fe_sq_op
2777	.type	fe_sq_op, %function
2778fe_sq_op:
2779	push	{lr}
2780	sub	sp, sp, #0x44
2781	str	r0, [sp, #64]
2782	# Square
2783	mov	r0, #0
2784	ldr	r12, [r1]
2785	# A[0] * A[1]
2786	ldr	lr, [r1, #4]
2787	umull	r4, r5, r12, lr
2788	# A[0] * A[3]
2789	ldr	lr, [r1, #12]
2790	umull	r6, r7, r12, lr
2791	# A[0] * A[5]
2792	ldr	lr, [r1, #20]
2793	umull	r8, r9, r12, lr
2794	# A[0] * A[7]
2795	ldr	lr, [r1, #28]
2796	umull	r10, r3, r12, lr
2797	# A[0] * A[2]
2798	ldr	lr, [r1, #8]
2799	mov	r11, #0
2800	umlal	r5, r11, r12, lr
2801	adds	r6, r6, r11
2802	# A[0] * A[4]
2803	ldr	lr, [r1, #16]
2804	adcs	r7, r7, #0
2805	adc	r11, r0, #0
2806	umlal	r7, r11, r12, lr
2807	adds	r8, r8, r11
2808	# A[0] * A[6]
2809	ldr	lr, [r1, #24]
2810	adcs	r9, r9, #0
2811	adc	r11, r0, #0
2812	umlal	r9, r11, r12, lr
2813	adds	r10, r10, r11
2814	adcs	r3, r3, #0
2815	str	r4, [sp, #4]
2816	str	r5, [sp, #8]
2817	# A[1] * A[2]
2818	ldr	r12, [r1, #4]
2819	ldr	lr, [r1, #8]
2820	mov	r11, #0
2821	umlal	r6, r11, r12, lr
2822	str	r6, [sp, #12]
2823	adds	r7, r7, r11
2824	# A[1] * A[3]
2825	ldr	lr, [r1, #12]
2826	adc	r11, r0, #0
2827	umlal	r7, r11, r12, lr
2828	str	r7, [sp, #16]
2829	adds	r8, r8, r11
2830	# A[1] * A[4]
2831	ldr	lr, [r1, #16]
2832	adc	r11, r0, #0
2833	umlal	r8, r11, r12, lr
2834	adds	r9, r9, r11
2835	# A[1] * A[5]
2836	ldr	lr, [r1, #20]
2837	adc	r11, r0, #0
2838	umlal	r9, r11, r12, lr
2839	adds	r10, r10, r11
2840	# A[1] * A[6]
2841	ldr	lr, [r1, #24]
2842	adc	r11, r0, #0
2843	umlal	r10, r11, r12, lr
2844	adds	r3, r3, r11
2845	# A[1] * A[7]
2846	ldr	lr, [r1, #28]
2847	adc	r4, r0, #0
2848	umlal	r3, r4, r12, lr
2849	# A[2] * A[3]
2850	ldr	r12, [r1, #8]
2851	ldr	lr, [r1, #12]
2852	mov	r11, #0
2853	umlal	r8, r11, r12, lr
2854	str	r8, [sp, #20]
2855	adds	r9, r9, r11
2856	# A[2] * A[4]
2857	ldr	lr, [r1, #16]
2858	adc	r11, r0, #0
2859	umlal	r9, r11, r12, lr
2860	str	r9, [sp, #24]
2861	adds	r10, r10, r11
2862	# A[2] * A[5]
2863	ldr	lr, [r1, #20]
2864	adc	r11, r0, #0
2865	umlal	r10, r11, r12, lr
2866	adds	r3, r3, r11
2867	# A[2] * A[6]
2868	ldr	lr, [r1, #24]
2869	adc	r11, r0, #0
2870	umlal	r3, r11, r12, lr
2871	adds	r4, r4, r11
2872	# A[2] * A[7]
2873	ldr	lr, [r1, #28]
2874	adc	r5, r0, #0
2875	umlal	r4, r5, r12, lr
2876	# A[3] * A[4]
2877	ldr	r12, [r1, #12]
2878	ldr	lr, [r1, #16]
2879	mov	r11, #0
2880	umlal	r10, r11, r12, lr
2881	str	r10, [sp, #28]
2882	adds	r3, r3, r11
2883	# A[3] * A[5]
2884	ldr	lr, [r1, #20]
2885	adc	r11, r0, #0
2886	umlal	r3, r11, r12, lr
2887	adds	r4, r4, r11
2888	# A[3] * A[6]
2889	ldr	lr, [r1, #24]
2890	adc	r11, r0, #0
2891	umlal	r4, r11, r12, lr
2892	adds	r5, r5, r11
2893	# A[3] * A[7]
2894	ldr	lr, [r1, #28]
2895	adc	r6, r0, #0
2896	umlal	r5, r6, r12, lr
2897	# A[4] * A[5]
2898	ldr	r12, [r1, #16]
2899	ldr	lr, [r1, #20]
2900	mov	r11, #0
2901	umlal	r4, r11, r12, lr
2902	adds	r5, r5, r11
2903	# A[4] * A[6]
2904	ldr	lr, [r1, #24]
2905	adc	r11, r0, #0
2906	umlal	r5, r11, r12, lr
2907	adds	r6, r6, r11
2908	# A[4] * A[7]
2909	ldr	lr, [r1, #28]
2910	adc	r7, r0, #0
2911	umlal	r6, r7, r12, lr
2912	# A[5] * A[6]
2913	ldr	r12, [r1, #20]
2914	ldr	lr, [r1, #24]
2915	mov	r11, #0
2916	umlal	r6, r11, r12, lr
2917	adds	r7, r7, r11
2918	# A[5] * A[7]
2919	ldr	lr, [r1, #28]
2920	adc	r8, r0, #0
2921	umlal	r7, r8, r12, lr
2922	# A[6] * A[7]
2923	ldr	r12, [r1, #24]
2924	ldr	lr, [r1, #28]
2925	mov	r9, #0
2926	umlal	r8, r9, r12, lr
2927	add	lr, sp, #32
2928	stm	lr, {r3, r4, r5, r6, r7, r8, r9}
2929	add	lr, sp, #4
2930	ldm	lr, {r4, r5, r6, r7, r8, r9, r10}
2931	adds	r4, r4, r4
2932	adcs	r5, r5, r5
2933	adcs	r6, r6, r6
2934	adcs	r7, r7, r7
2935	adcs	r8, r8, r8
2936	adcs	r9, r9, r9
2937	adcs	r10, r10, r10
2938	stm	lr!, {r4, r5, r6, r7, r8, r9, r10}
2939	ldm	lr, {r3, r4, r5, r6, r7, r8, r9}
2940	adcs	r3, r3, r3
2941	adcs	r4, r4, r4
2942	adcs	r5, r5, r5
2943	adcs	r6, r6, r6
2944	adcs	r7, r7, r7
2945	adcs	r8, r8, r8
2946	adcs	r9, r9, r9
2947	adc	r10, r0, #0
2948	stm	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
2949	add	lr, sp, #4
2950	ldm	lr, {r4, r5, r6, r7, r8, r9, r10}
2951	mov	lr, sp
2952	# A[0] * A[0]
2953	ldr	r12, [r1]
2954	umull	r3, r11, r12, r12
2955	adds	r4, r4, r11
2956	# A[1] * A[1]
2957	ldr	r12, [r1, #4]
2958	adcs	r5, r5, #0
2959	adc	r11, r0, #0
2960	umlal	r5, r11, r12, r12
2961	adds	r6, r6, r11
2962	# A[2] * A[2]
2963	ldr	r12, [r1, #8]
2964	adcs	r7, r7, #0
2965	adc	r11, r0, #0
2966	umlal	r7, r11, r12, r12
2967	adds	r8, r8, r11
2968	# A[3] * A[3]
2969	ldr	r12, [r1, #12]
2970	adcs	r9, r9, #0
2971	adc	r11, r0, #0
2972	umlal	r9, r11, r12, r12
2973	adds	r10, r10, r11
2974	stm	lr!, {r3, r4, r5, r6, r7, r8, r9, r10}
2975	ldm	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
2976	# A[4] * A[4]
2977	ldr	r12, [r1, #16]
2978	adcs	r3, r3, #0
2979	adc	r11, r0, #0
2980	umlal	r3, r11, r12, r12
2981	adds	r4, r4, r11
2982	# A[5] * A[5]
2983	ldr	r12, [r1, #20]
2984	adcs	r5, r5, #0
2985	adc	r11, r0, #0
2986	umlal	r5, r11, r12, r12
2987	adds	r6, r6, r11
2988	# A[6] * A[6]
2989	ldr	r12, [r1, #24]
2990	adcs	r7, r7, #0
2991	adc	r11, r0, #0
2992	umlal	r7, r11, r12, r12
2993	adds	r8, r8, r11
2994	# A[7] * A[7]
2995	ldr	r12, [r1, #28]
2996	adcs	r9, r9, #0
2997	adc	r10, r10, #0
2998	umlal	r9, r10, r12, r12
2999	# Reduce
3000	ldr	r2, [sp, #28]
3001	mov	lr, sp
3002	mov	r12, #38
3003	umull	r10, r11, r12, r10
3004	adds	r10, r10, r2
3005	adc	r11, r11, #0
3006	mov	r12, #19
3007	lsl	r11, r11, #1
3008	orr	r11, r11, r10, lsr #31
3009	mul	r11, r12, r11
3010	ldm	lr!, {r1, r2}
3011	mov	r12, #38
3012	adds	r1, r1, r11
3013	adc	r11, r0, #0
3014	umlal	r1, r11, r3, r12
3015	adds	r2, r2, r11
3016	adc	r11, r0, #0
3017	umlal	r2, r11, r4, r12
3018	ldm	lr!, {r3, r4}
3019	adds	r3, r3, r11
3020	adc	r11, r0, #0
3021	umlal	r3, r11, r5, r12
3022	adds	r4, r4, r11
3023	adc	r11, r0, #0
3024	umlal	r4, r11, r6, r12
3025	ldm	lr!, {r5, r6}
3026	adds	r5, r5, r11
3027	adc	r11, r0, #0
3028	umlal	r5, r11, r7, r12
3029	adds	r6, r6, r11
3030	adc	r11, r0, #0
3031	umlal	r6, r11, r8, r12
3032	ldm	lr!, {r7, r8}
3033	adds	r7, r7, r11
3034	adc	r11, r0, #0
3035	umlal	r7, r11, r9, r12
3036#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3037	bic	r10, r10, #0x80000000
3038#else
3039	bfc	r10, #31, #1
3040#endif
3041	adds	r8, r10, r11
3042	# Store
3043	ldr	r0, [sp, #64]
3044	stm	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
3045	add	sp, sp, #0x44
3046	pop	{pc}
3047	.size	fe_sq_op,.-fe_sq_op
3048#else
3049	.text
3050	.align	4
3051	.globl	fe_sq_op
3052	.type	fe_sq_op, %function
3053fe_sq_op:
3054	push	{lr}
3055	sub	sp, sp, #32
3056	str	r0, [sp, #28]
3057	ldm	r1, {r0, r1, r2, r3, r4, r5, r6, r7}
3058	# Square
3059	umull	r9, r10, r0, r0
3060	umull	r11, r12, r0, r1
3061	adds	r11, r11, r11
3062	mov	lr, #0
3063	umaal	r10, r11, lr, lr
3064	stm	sp, {r9, r10}
3065	mov	r8, lr
3066	umaal	r8, r12, r0, r2
3067	adcs	r8, r8, r8
3068	umaal	r8, r11, r1, r1
3069	umull	r9, r10, r0, r3
3070	umaal	r9, r12, r1, r2
3071	adcs	r9, r9, r9
3072	umaal	r9, r11, lr, lr
3073#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3074	str	r8, [sp, #8]
3075	str	r9, [sp, #12]
3076#else
3077	strd	r8, r9, [sp, #8]
3078#endif
3079	mov	r9, lr
3080	umaal	r9, r10, r0, r4
3081	umaal	r9, r12, r1, r3
3082	adcs	r9, r9, r9
3083	umaal	r9, r11, r2, r2
3084	str	r9, [sp, #16]
3085	umull	r9, r8, r0, r5
3086	umaal	r9, r12, r1, r4
3087	umaal	r9, r10, r2, r3
3088	adcs	r9, r9, r9
3089	umaal	r9, r11, lr, lr
3090	str	r9, [sp, #20]
3091	mov	r9, lr
3092	umaal	r9, r8, r0, r6
3093	umaal	r9, r12, r1, r5
3094	umaal	r9, r10, r2, r4
3095	adcs	r9, r9, r9
3096	umaal	r9, r11, r3, r3
3097	str	r9, [sp, #24]
3098	umull	r0, r9, r0, r7
3099	umaal	r0, r8, r1, r6
3100	umaal	r0, r12, r2, r5
3101	umaal	r0, r10, r3, r4
3102	adcs	r0, r0, r0
3103	umaal	r0, r11, lr, lr
3104	# R[7] = r0
3105	umaal	r9, r8, r1, r7
3106	umaal	r9, r10, r2, r6
3107	umaal	r12, r9, r3, r5
3108	adcs	r12, r12, r12
3109	umaal	r12, r11, r4, r4
3110	# R[8] = r12
3111	umaal	r9, r8, r2, r7
3112	umaal	r10, r9, r3, r6
3113	mov	r2, lr
3114	umaal	r10, r2, r4, r5
3115	adcs	r10, r10, r10
3116	umaal	r11, r10, lr, lr
3117	# R[9] = r11
3118	umaal	r2, r8, r3, r7
3119	umaal	r2, r9, r4, r6
3120	adcs	r3, r2, r2
3121	umaal	r10, r3, r5, r5
3122	# R[10] = r10
3123	mov	r1, lr
3124	umaal	r1, r8, r4, r7
3125	umaal	r1, r9, r5, r6
3126	adcs	r4, r1, r1
3127	umaal	r3, r4, lr, lr
3128	# R[11] = r3
3129	umaal	r8, r9, r5, r7
3130	adcs	r8, r8, r8
3131	umaal	r4, r8, r6, r6
3132	# R[12] = r4
3133	mov	r5, lr
3134	umaal	r5, r9, r6, r7
3135	adcs	r5, r5, r5
3136	umaal	r8, r5, lr, lr
3137	# R[13] = r8
3138	adcs	r9, r9, r9
3139	umaal	r9, r5, r7, r7
3140	adcs	r7, r5, lr
3141	# R[14] = r9
3142	# R[15] = r7
3143	# Reduce
3144	mov	r6, #37
3145	umaal	r7, r0, r7, r6
3146	mov	r6, #19
3147	lsl	r0, r0, #1
3148	orr	r0, r0, r7, lsr #31
3149	mul	lr, r0, r6
3150	pop	{r0-r1}
3151	mov	r6, #38
3152	umaal	r0, lr, r12, r6
3153	umaal	r1, lr, r11, r6
3154	mov	r12, r3
3155	mov	r11, r4
3156	pop	{r2-r4}
3157	umaal	r2, lr, r10, r6
3158	umaal	r3, lr, r12, r6
3159	umaal	r4, lr, r11, r6
3160	mov	r12, r6
3161	pop	{r5-r6}
3162	umaal	r5, lr, r8, r12
3163#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3164	bic	r7, r7, #0x80000000
3165#else
3166	bfc	r7, #31, #1
3167#endif
3168	umaal	r6, lr, r9, r12
3169	add	r7, r7, lr
3170	pop	{lr}
3171	# Store
3172	stm	lr, {r0, r1, r2, r3, r4, r5, r6, r7}
3173	pop	{pc}
3174	.size	fe_sq_op,.-fe_sq_op
3175#endif /* WOLFSSL_ARM_ARCH && WOLFSSL_ARM_ARCH < 6 */
3176	.text
3177	.align	4
3178	.globl	fe_sq
3179	.type	fe_sq, %function
3180fe_sq:
3181	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
3182	bl	fe_sq_op
3183	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
3184	.size	fe_sq,.-fe_sq
3185#ifdef HAVE_CURVE25519
3186#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
3187	.text
3188	.align	4
3189	.globl	fe_mul121666
3190	.type	fe_mul121666, %function
3191fe_mul121666:
3192	push	{r4, r5, r6, r7, r8, r9, r10, lr}
3193	# Multiply by 121666
3194	ldm	r1, {r2, r3, r4, r5, r6, r7, r8, r9}
3195#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3196	mov	r10, #0x42
3197	orr	r10, r10, #0x10000
3198	orr	r10, r10, #0xdb00
3199#else
3200#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3201	mov	r10, #0x42
3202	orr	r10, r10, #0xdb00
3203#else
3204	mov	r10, #0xdb42
3205#endif
3206#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3207	orr	r10, r10, #0x10000
3208#else
3209	movt	r10, #0x1
3210#endif
3211#endif
3212	umull	r2, r12, r10, r2
3213	umull	r3, lr, r10, r3
3214	adds	r3, r3, r12
3215	adc	lr, lr, #0
3216	umull	r4, r12, r10, r4
3217	adds	r4, r4, lr
3218	adc	r12, r12, #0
3219	umull	r5, lr, r10, r5
3220	adds	r5, r5, r12
3221	adc	lr, lr, #0
3222	umull	r6, r12, r10, r6
3223	adds	r6, r6, lr
3224	adc	r12, r12, #0
3225	umull	r7, lr, r10, r7
3226	adds	r7, r7, r12
3227	adc	lr, lr, #0
3228	umull	r8, r12, r10, r8
3229	adds	r8, r8, lr
3230	adc	r12, r12, #0
3231	umull	r9, lr, r10, r9
3232	adds	r9, r9, r12
3233	mov	r10, #19
3234	adc	lr, lr, #0
3235	lsl	lr, lr, #1
3236	orr	lr, lr, r9, lsr #31
3237	mul	lr, r10, lr
3238	adds	r2, r2, lr
3239	adcs	r3, r3, #0
3240	adcs	r4, r4, #0
3241	adcs	r5, r5, #0
3242	adcs	r6, r6, #0
3243	adcs	r7, r7, #0
3244#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3245	bic	r9, r9, #0x80000000
3246#else
3247	bfc	r9, #31, #1
3248#endif
3249	adcs	r8, r8, #0
3250	adc	r9, r9, #0
3251	stm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
3252	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
3253	.size	fe_mul121666,.-fe_mul121666
3254#else
3255	.text
3256	.align	4
3257	.globl	fe_mul121666
3258	.type	fe_mul121666, %function
3259fe_mul121666:
3260	push	{r4, r5, r6, r7, r8, r9, r10, lr}
3261	# Multiply by 121666
3262	ldm	r1, {r2, r3, r4, r5, r6, r7, r8, r9}
3263#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3264	mov	lr, #0x42
3265	orr	lr, lr, #0x10000
3266	orr	lr, lr, #0xdb00
3267#else
3268#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3269	mov	lr, #0x42
3270	orr	lr, lr, #0xdb00
3271#else
3272	mov	lr, #0xdb42
3273#endif
3274#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3275	orr	lr, lr, #0x10000
3276#else
3277	movt	lr, #0x1
3278#endif
3279#endif
3280	umull	r2, r10, lr, r2
3281	sub	r12, lr, #1
3282	umaal	r3, r10, r12, r3
3283	umaal	r4, r10, r12, r4
3284	umaal	r5, r10, r12, r5
3285	umaal	r6, r10, r12, r6
3286	umaal	r7, r10, r12, r7
3287	umaal	r8, r10, r12, r8
3288	mov	lr, #19
3289	umaal	r9, r10, r12, r9
3290	lsl	r10, r10, #1
3291	orr	r10, r10, r9, lsr #31
3292	mul	r10, lr, r10
3293	adds	r2, r2, r10
3294	adcs	r3, r3, #0
3295	adcs	r4, r4, #0
3296	adcs	r5, r5, #0
3297	adcs	r6, r6, #0
3298	adcs	r7, r7, #0
3299#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3300	bic	r9, r9, #0x80000000
3301#else
3302	bfc	r9, #31, #1
3303#endif
3304	adcs	r8, r8, #0
3305	adc	r9, r9, #0
3306	stm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
3307	pop	{r4, r5, r6, r7, r8, r9, r10, pc}
3308	.size	fe_mul121666,.-fe_mul121666
3309#endif /* WOLFSSL_ARM_ARCH && WOLFSSL_ARM_ARCH < 6 */
3310#ifndef WC_NO_CACHE_RESISTANT
3311	.text
3312	.align	4
3313	.globl	curve25519
3314	.type	curve25519, %function
3315curve25519:
3316	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
3317	sub	sp, sp, #0xbc
3318	str	r0, [sp, #160]
3319	str	r1, [sp, #164]
3320	str	r2, [sp, #168]
3321	mov	r1, #0
3322	str	r1, [sp, #172]
3323	mov	r4, #1
3324	mov	r5, #0
3325	mov	r6, #0
3326	mov	r7, #0
3327	mov	r8, #0
3328	mov	r9, #0
3329	mov	r10, #0
3330	mov	r11, #0
3331	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
3332	add	r3, sp, #32
3333	stm	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
3334	mov	r4, #0
3335	mov	r3, sp
3336	stm	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
3337	add	r3, sp, #0x40
3338	# Copy
3339	ldm	r2, {r4, r5, r6, r7, r8, r9, r10, r11}
3340	stm	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
3341	mov	r1, #30
3342	str	r1, [sp, #180]
3343	mov	r2, #28
3344	str	r2, [sp, #176]
3345L_curve25519_words:
3346L_curve25519_bits:
3347	ldr	r1, [sp, #164]
3348	ldr	r2, [r1, r2]
3349	ldr	r1, [sp, #180]
3350	lsr	r2, r2, r1
3351	and	r2, r2, #1
3352	str	r2, [sp, #184]
3353	ldr	r1, [sp, #172]
3354	eor	r1, r1, r2
3355	str	r1, [sp, #172]
3356	ldr	r0, [sp, #160]
3357	# Conditional Swap
3358	rsb	r1, r1, #0
3359	mov	r3, r0
3360	add	r12, sp, #0x40
3361	ldm	r3, {r4, r5}
3362	ldm	r12, {r6, r7}
3363	eor	r8, r4, r6
3364	eor	r9, r5, r7
3365	and	r8, r8, r1
3366	and	r9, r9, r1
3367	eor	r4, r4, r8
3368	eor	r5, r5, r9
3369	eor	r6, r6, r8
3370	eor	r7, r7, r9
3371	stm	r3!, {r4, r5}
3372	stm	r12!, {r6, r7}
3373	ldm	r3, {r4, r5}
3374	ldm	r12, {r6, r7}
3375	eor	r8, r4, r6
3376	eor	r9, r5, r7
3377	and	r8, r8, r1
3378	and	r9, r9, r1
3379	eor	r4, r4, r8
3380	eor	r5, r5, r9
3381	eor	r6, r6, r8
3382	eor	r7, r7, r9
3383	stm	r3!, {r4, r5}
3384	stm	r12!, {r6, r7}
3385	ldm	r3, {r4, r5}
3386	ldm	r12, {r6, r7}
3387	eor	r8, r4, r6
3388	eor	r9, r5, r7
3389	and	r8, r8, r1
3390	and	r9, r9, r1
3391	eor	r4, r4, r8
3392	eor	r5, r5, r9
3393	eor	r6, r6, r8
3394	eor	r7, r7, r9
3395	stm	r3!, {r4, r5}
3396	stm	r12!, {r6, r7}
3397	ldm	r3, {r4, r5}
3398	ldm	r12, {r6, r7}
3399	eor	r8, r4, r6
3400	eor	r9, r5, r7
3401	and	r8, r8, r1
3402	and	r9, r9, r1
3403	eor	r4, r4, r8
3404	eor	r5, r5, r9
3405	eor	r6, r6, r8
3406	eor	r7, r7, r9
3407	stm	r3!, {r4, r5}
3408	stm	r12!, {r6, r7}
3409	ldr	r1, [sp, #172]
3410	# Conditional Swap
3411	rsb	r1, r1, #0
3412	mov	r3, sp
3413	add	r12, sp, #32
3414	ldm	r3, {r4, r5}
3415	ldm	r12, {r6, r7}
3416	eor	r8, r4, r6
3417	eor	r9, r5, r7
3418	and	r8, r8, r1
3419	and	r9, r9, r1
3420	eor	r4, r4, r8
3421	eor	r5, r5, r9
3422	eor	r6, r6, r8
3423	eor	r7, r7, r9
3424	stm	r3!, {r4, r5}
3425	stm	r12!, {r6, r7}
3426	ldm	r3, {r4, r5}
3427	ldm	r12, {r6, r7}
3428	eor	r8, r4, r6
3429	eor	r9, r5, r7
3430	and	r8, r8, r1
3431	and	r9, r9, r1
3432	eor	r4, r4, r8
3433	eor	r5, r5, r9
3434	eor	r6, r6, r8
3435	eor	r7, r7, r9
3436	stm	r3!, {r4, r5}
3437	stm	r12!, {r6, r7}
3438	ldm	r3, {r4, r5}
3439	ldm	r12, {r6, r7}
3440	eor	r8, r4, r6
3441	eor	r9, r5, r7
3442	and	r8, r8, r1
3443	and	r9, r9, r1
3444	eor	r4, r4, r8
3445	eor	r5, r5, r9
3446	eor	r6, r6, r8
3447	eor	r7, r7, r9
3448	stm	r3!, {r4, r5}
3449	stm	r12!, {r6, r7}
3450	ldm	r3, {r4, r5}
3451	ldm	r12, {r6, r7}
3452	eor	r8, r4, r6
3453	eor	r9, r5, r7
3454	and	r8, r8, r1
3455	and	r9, r9, r1
3456	eor	r4, r4, r8
3457	eor	r5, r5, r9
3458	eor	r6, r6, r8
3459	eor	r7, r7, r9
3460	stm	r3!, {r4, r5}
3461	stm	r12!, {r6, r7}
3462	ldr	r1, [sp, #184]
3463	str	r1, [sp, #172]
3464	mov	r3, sp
3465	ldr	r2, [sp, #160]
3466	add	r1, sp, #0x80
3467	ldr	r0, [sp, #160]
3468	bl	fe_add_sub_op
3469	add	r3, sp, #32
3470	add	r2, sp, #0x40
3471	add	r1, sp, #0x60
3472	mov	r0, sp
3473	bl	fe_add_sub_op
3474	ldr	r2, [sp, #160]
3475	add	r1, sp, #0x60
3476	add	r0, sp, #32
3477	bl	fe_mul_op
3478	add	r2, sp, #0x80
3479	mov	r1, sp
3480	mov	r0, sp
3481	bl	fe_mul_op
3482	add	r1, sp, #0x80
3483	add	r0, sp, #0x80
3484	bl	fe_sq_op
3485	ldr	r1, [sp, #160]
3486	add	r0, sp, #0x60
3487	bl	fe_sq_op
3488	mov	r3, sp
3489	add	r2, sp, #32
3490	mov	r1, sp
3491	add	r0, sp, #0x40
3492	bl	fe_add_sub_op
3493	add	r2, sp, #0x80
3494	add	r1, sp, #0x60
3495	ldr	r0, [sp, #160]
3496	bl	fe_mul_op
3497	add	r2, sp, #0x80
3498	add	r1, sp, #0x60
3499	add	r0, sp, #0x60
3500	bl	fe_sub_op
3501	mov	r1, sp
3502	mov	r0, sp
3503	bl	fe_sq_op
3504	add	r1, sp, #0x60
3505	add	r0, sp, #32
3506	bl	fe_mul121666
3507	add	r1, sp, #0x40
3508	add	r0, sp, #0x40
3509	bl	fe_sq_op
3510	add	r2, sp, #32
3511	add	r1, sp, #0x80
3512	add	r0, sp, #0x80
3513	bl	fe_add_op
3514	mov	r2, sp
3515	ldr	r1, [sp, #168]
3516	add	r0, sp, #32
3517	bl	fe_mul_op
3518	add	r2, sp, #0x80
3519	add	r1, sp, #0x60
3520	mov	r0, sp
3521	bl	fe_mul_op
3522	ldr	r2, [sp, #176]
3523	ldr	r1, [sp, #180]
3524	subs	r1, r1, #1
3525	str	r1, [sp, #180]
3526	bge	L_curve25519_bits
3527	mov	r1, #31
3528	str	r1, [sp, #180]
3529	subs	r2, r2, #4
3530	str	r2, [sp, #176]
3531	bge	L_curve25519_words
3532	# Invert
3533	add	r1, sp, #0
3534	add	r0, sp, #32
3535	bl	fe_sq_op
3536	add	r1, sp, #32
3537	add	r0, sp, #0x40
3538	bl	fe_sq_op
3539	add	r1, sp, #0x40
3540	add	r0, sp, #0x40
3541	bl	fe_sq_op
3542	add	r2, sp, #0x40
3543	add	r1, sp, #0
3544	add	r0, sp, #0x40
3545	bl	fe_mul_op
3546	add	r2, sp, #0x40
3547	add	r1, sp, #32
3548	add	r0, sp, #32
3549	bl	fe_mul_op
3550	add	r1, sp, #32
3551	add	r0, sp, #0x60
3552	bl	fe_sq_op
3553	add	r2, sp, #0x60
3554	add	r1, sp, #0x40
3555	add	r0, sp, #0x40
3556	bl	fe_mul_op
3557	add	r1, sp, #0x40
3558	add	r0, sp, #0x60
3559	bl	fe_sq_op
3560	mov	r12, #4
3561L_curve25519_inv_1:
3562	add	r1, sp, #0x60
3563	add	r0, sp, #0x60
3564	push	{r12}
3565	bl	fe_sq_op
3566	pop	{r12}
3567	subs	r12, r12, #1
3568	bne	L_curve25519_inv_1
3569	add	r2, sp, #0x40
3570	add	r1, sp, #0x60
3571	add	r0, sp, #0x40
3572	bl	fe_mul_op
3573	add	r1, sp, #0x40
3574	add	r0, sp, #0x60
3575	bl	fe_sq_op
3576	mov	r12, #9
3577L_curve25519_inv_2:
3578	add	r1, sp, #0x60
3579	add	r0, sp, #0x60
3580	push	{r12}
3581	bl	fe_sq_op
3582	pop	{r12}
3583	subs	r12, r12, #1
3584	bne	L_curve25519_inv_2
3585	add	r2, sp, #0x40
3586	add	r1, sp, #0x60
3587	add	r0, sp, #0x60
3588	bl	fe_mul_op
3589	add	r1, sp, #0x60
3590	add	r0, sp, #0x80
3591	bl	fe_sq_op
3592	mov	r12, #19
3593L_curve25519_inv_3:
3594	add	r1, sp, #0x80
3595	add	r0, sp, #0x80
3596	push	{r12}
3597	bl	fe_sq_op
3598	pop	{r12}
3599	subs	r12, r12, #1
3600	bne	L_curve25519_inv_3
3601	add	r2, sp, #0x60
3602	add	r1, sp, #0x80
3603	add	r0, sp, #0x60
3604	bl	fe_mul_op
3605	mov	r12, #10
3606L_curve25519_inv_4:
3607	add	r1, sp, #0x60
3608	add	r0, sp, #0x60
3609	push	{r12}
3610	bl	fe_sq_op
3611	pop	{r12}
3612	subs	r12, r12, #1
3613	bne	L_curve25519_inv_4
3614	add	r2, sp, #0x40
3615	add	r1, sp, #0x60
3616	add	r0, sp, #0x40
3617	bl	fe_mul_op
3618	add	r1, sp, #0x40
3619	add	r0, sp, #0x60
3620	bl	fe_sq_op
3621	mov	r12, #49
3622L_curve25519_inv_5:
3623	add	r1, sp, #0x60
3624	add	r0, sp, #0x60
3625	push	{r12}
3626	bl	fe_sq_op
3627	pop	{r12}
3628	subs	r12, r12, #1
3629	bne	L_curve25519_inv_5
3630	add	r2, sp, #0x40
3631	add	r1, sp, #0x60
3632	add	r0, sp, #0x60
3633	bl	fe_mul_op
3634	add	r1, sp, #0x60
3635	add	r0, sp, #0x80
3636	bl	fe_sq_op
3637	mov	r12, #0x63
3638L_curve25519_inv_6:
3639	add	r1, sp, #0x80
3640	add	r0, sp, #0x80
3641	push	{r12}
3642	bl	fe_sq_op
3643	pop	{r12}
3644	subs	r12, r12, #1
3645	bne	L_curve25519_inv_6
3646	add	r2, sp, #0x60
3647	add	r1, sp, #0x80
3648	add	r0, sp, #0x60
3649	bl	fe_mul_op
3650	mov	r12, #50
3651L_curve25519_inv_7:
3652	add	r1, sp, #0x60
3653	add	r0, sp, #0x60
3654	push	{r12}
3655	bl	fe_sq_op
3656	pop	{r12}
3657	subs	r12, r12, #1
3658	bne	L_curve25519_inv_7
3659	add	r2, sp, #0x40
3660	add	r1, sp, #0x60
3661	add	r0, sp, #0x40
3662	bl	fe_mul_op
3663	mov	r12, #5
3664L_curve25519_inv_8:
3665	add	r1, sp, #0x40
3666	add	r0, sp, #0x40
3667	push	{r12}
3668	bl	fe_sq_op
3669	pop	{r12}
3670	subs	r12, r12, #1
3671	bne	L_curve25519_inv_8
3672	add	r2, sp, #32
3673	add	r1, sp, #0x40
3674	add	r0, sp, #0
3675	bl	fe_mul_op
3676	mov	r2, sp
3677	ldr	r1, [sp, #160]
3678	ldr	r0, [sp, #160]
3679	bl	fe_mul_op
3680	mov	r0, #0
3681	add	sp, sp, #0xbc
3682	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
3683	.size	curve25519,.-curve25519
3684#else
3685	.text
3686	.align	4
3687	.globl	curve25519
3688	.type	curve25519, %function
3689curve25519:
3690	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
3691	sub	sp, sp, #0xc0
3692	str	r0, [sp, #176]
3693	str	r1, [sp, #160]
3694	str	r2, [sp, #172]
3695	add	r5, sp, #0x40
3696	add	r4, sp, #32
3697	str	sp, [sp, #184]
3698	str	r5, [sp, #180]
3699	str	r4, [sp, #188]
3700	mov	r1, #0
3701	str	r1, [sp, #164]
3702	mov	r4, #1
3703	mov	r5, #0
3704	mov	r6, #0
3705	mov	r7, #0
3706	mov	r8, #0
3707	mov	r9, #0
3708	mov	r10, #0
3709	mov	r11, #0
3710	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
3711	add	r3, sp, #32
3712	stm	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
3713	mov	r4, #0
3714	mov	r3, sp
3715	stm	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
3716	add	r3, sp, #0x40
3717	# Copy
3718	ldm	r2, {r4, r5, r6, r7, r8, r9, r10, r11}
3719	stm	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
3720	mov	r2, #0xfe
3721L_curve25519_bits:
3722	str	r2, [sp, #168]
3723	ldr	r1, [sp, #160]
3724	and	r4, r2, #31
3725	lsr	r2, r2, #5
3726	ldr	r2, [r1, r2, lsl #2]
3727	rsb	r4, r4, #31
3728	lsl	r2, r2, r4
3729	ldr	r1, [sp, #164]
3730	eor	r1, r1, r2
3731	asr	r1, r1, #31
3732	str	r2, [sp, #164]
3733	# Conditional Swap
3734	add	r11, sp, #0xb0
3735	ldm	r11, {r4, r5, r6, r7}
3736	eor	r8, r4, r5
3737	eor	r9, r6, r7
3738	and	r8, r8, r1
3739	and	r9, r9, r1
3740	eor	r4, r4, r8
3741	eor	r5, r5, r8
3742	eor	r6, r6, r9
3743	eor	r7, r7, r9
3744	stm	r11, {r4, r5, r6, r7}
3745	# Ladder step
3746	ldr	r3, [sp, #184]
3747	ldr	r2, [sp, #176]
3748	add	r1, sp, #0x80
3749	ldr	r0, [sp, #176]
3750	bl	fe_add_sub_op
3751	ldr	r3, [sp, #188]
3752	ldr	r2, [sp, #180]
3753	add	r1, sp, #0x60
3754	ldr	r0, [sp, #184]
3755	bl	fe_add_sub_op
3756	ldr	r2, [sp, #176]
3757	add	r1, sp, #0x60
3758	ldr	r0, [sp, #188]
3759	bl	fe_mul_op
3760	add	r2, sp, #0x80
3761	ldr	r1, [sp, #184]
3762	ldr	r0, [sp, #184]
3763	bl	fe_mul_op
3764	add	r1, sp, #0x80
3765	add	r0, sp, #0x60
3766	bl	fe_sq_op
3767	ldr	r1, [sp, #176]
3768	add	r0, sp, #0x80
3769	bl	fe_sq_op
3770	ldr	r3, [sp, #184]
3771	ldr	r2, [sp, #188]
3772	ldr	r1, [sp, #184]
3773	ldr	r0, [sp, #180]
3774	bl	fe_add_sub_op
3775	add	r2, sp, #0x60
3776	add	r1, sp, #0x80
3777	ldr	r0, [sp, #176]
3778	bl	fe_mul_op
3779	add	r2, sp, #0x60
3780	add	r1, sp, #0x80
3781	add	r0, sp, #0x80
3782	bl	fe_sub_op
3783	ldr	r1, [sp, #184]
3784	ldr	r0, [sp, #184]
3785	bl	fe_sq_op
3786	add	r1, sp, #0x80
3787	ldr	r0, [sp, #188]
3788	bl	fe_mul121666
3789	ldr	r1, [sp, #180]
3790	ldr	r0, [sp, #180]
3791	bl	fe_sq_op
3792	ldr	r2, [sp, #188]
3793	add	r1, sp, #0x60
3794	add	r0, sp, #0x60
3795	bl	fe_add_op
3796	ldr	r2, [sp, #184]
3797	ldr	r1, [sp, #172]
3798	ldr	r0, [sp, #188]
3799	bl	fe_mul_op
3800	add	r2, sp, #0x60
3801	add	r1, sp, #0x80
3802	ldr	r0, [sp, #184]
3803	bl	fe_mul_op
3804	ldr	r2, [sp, #168]
3805	subs	r2, r2, #1
3806	bge	L_curve25519_bits
3807	ldr	r1, [sp, #184]
3808	# Copy
3809	ldm	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
3810	stm	sp, {r4, r5, r6, r7, r8, r9, r10, r11}
3811	# Invert
3812	add	r1, sp, #0
3813	add	r0, sp, #32
3814	bl	fe_sq_op
3815	add	r1, sp, #32
3816	add	r0, sp, #0x40
3817	bl	fe_sq_op
3818	add	r1, sp, #0x40
3819	add	r0, sp, #0x40
3820	bl	fe_sq_op
3821	add	r2, sp, #0x40
3822	add	r1, sp, #0
3823	add	r0, sp, #0x40
3824	bl	fe_mul_op
3825	add	r2, sp, #0x40
3826	add	r1, sp, #32
3827	add	r0, sp, #32
3828	bl	fe_mul_op
3829	add	r1, sp, #32
3830	add	r0, sp, #0x60
3831	bl	fe_sq_op
3832	add	r2, sp, #0x60
3833	add	r1, sp, #0x40
3834	add	r0, sp, #0x40
3835	bl	fe_mul_op
3836	add	r1, sp, #0x40
3837	add	r0, sp, #0x60
3838	bl	fe_sq_op
3839	mov	r12, #4
3840L_curve25519_inv_1:
3841	add	r1, sp, #0x60
3842	add	r0, sp, #0x60
3843	push	{r12}
3844	bl	fe_sq_op
3845	pop	{r12}
3846	subs	r12, r12, #1
3847	bne	L_curve25519_inv_1
3848	add	r2, sp, #0x40
3849	add	r1, sp, #0x60
3850	add	r0, sp, #0x40
3851	bl	fe_mul_op
3852	add	r1, sp, #0x40
3853	add	r0, sp, #0x60
3854	bl	fe_sq_op
3855	mov	r12, #9
3856L_curve25519_inv_2:
3857	add	r1, sp, #0x60
3858	add	r0, sp, #0x60
3859	push	{r12}
3860	bl	fe_sq_op
3861	pop	{r12}
3862	subs	r12, r12, #1
3863	bne	L_curve25519_inv_2
3864	add	r2, sp, #0x40
3865	add	r1, sp, #0x60
3866	add	r0, sp, #0x60
3867	bl	fe_mul_op
3868	add	r1, sp, #0x60
3869	add	r0, sp, #0x80
3870	bl	fe_sq_op
3871	mov	r12, #19
3872L_curve25519_inv_3:
3873	add	r1, sp, #0x80
3874	add	r0, sp, #0x80
3875	push	{r12}
3876	bl	fe_sq_op
3877	pop	{r12}
3878	subs	r12, r12, #1
3879	bne	L_curve25519_inv_3
3880	add	r2, sp, #0x60
3881	add	r1, sp, #0x80
3882	add	r0, sp, #0x60
3883	bl	fe_mul_op
3884	mov	r12, #10
3885L_curve25519_inv_4:
3886	add	r1, sp, #0x60
3887	add	r0, sp, #0x60
3888	push	{r12}
3889	bl	fe_sq_op
3890	pop	{r12}
3891	subs	r12, r12, #1
3892	bne	L_curve25519_inv_4
3893	add	r2, sp, #0x40
3894	add	r1, sp, #0x60
3895	add	r0, sp, #0x40
3896	bl	fe_mul_op
3897	add	r1, sp, #0x40
3898	add	r0, sp, #0x60
3899	bl	fe_sq_op
3900	mov	r12, #49
3901L_curve25519_inv_5:
3902	add	r1, sp, #0x60
3903	add	r0, sp, #0x60
3904	push	{r12}
3905	bl	fe_sq_op
3906	pop	{r12}
3907	subs	r12, r12, #1
3908	bne	L_curve25519_inv_5
3909	add	r2, sp, #0x40
3910	add	r1, sp, #0x60
3911	add	r0, sp, #0x60
3912	bl	fe_mul_op
3913	add	r1, sp, #0x60
3914	add	r0, sp, #0x80
3915	bl	fe_sq_op
3916	mov	r12, #0x63
3917L_curve25519_inv_6:
3918	add	r1, sp, #0x80
3919	add	r0, sp, #0x80
3920	push	{r12}
3921	bl	fe_sq_op
3922	pop	{r12}
3923	subs	r12, r12, #1
3924	bne	L_curve25519_inv_6
3925	add	r2, sp, #0x60
3926	add	r1, sp, #0x80
3927	add	r0, sp, #0x60
3928	bl	fe_mul_op
3929	mov	r12, #50
3930L_curve25519_inv_7:
3931	add	r1, sp, #0x60
3932	add	r0, sp, #0x60
3933	push	{r12}
3934	bl	fe_sq_op
3935	pop	{r12}
3936	subs	r12, r12, #1
3937	bne	L_curve25519_inv_7
3938	add	r2, sp, #0x40
3939	add	r1, sp, #0x60
3940	add	r0, sp, #0x40
3941	bl	fe_mul_op
3942	mov	r12, #5
3943L_curve25519_inv_8:
3944	add	r1, sp, #0x40
3945	add	r0, sp, #0x40
3946	push	{r12}
3947	bl	fe_sq_op
3948	pop	{r12}
3949	subs	r12, r12, #1
3950	bne	L_curve25519_inv_8
3951	add	r2, sp, #32
3952	add	r1, sp, #0x40
3953	add	r0, sp, #0
3954	bl	fe_mul_op
3955	ldr	r2, [sp, #184]
3956	ldr	r1, [sp, #176]
3957	ldr	r0, [sp, #176]
3958	bl	fe_mul_op
3959	# Ensure result is less than modulus
3960	ldr	r0, [sp, #176]
3961	ldm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
3962	mov	r2, #19
3963	and	r2, r2, r11, asr #31
3964	adds	r4, r4, r2
3965	adcs	r5, r5, #0
3966	adcs	r6, r6, #0
3967	adcs	r7, r7, #0
3968	adcs	r8, r8, #0
3969	adcs	r9, r9, #0
3970#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
3971	bic	r11, r11, #0x80000000
3972#else
3973	bfc	r11, #31, #1
3974#endif
3975	adcs	r10, r10, #0
3976	adc	r11, r11, #0
3977	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
3978	mov	r0, #0
3979	add	sp, sp, #0xc0
3980	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
3981	.size	curve25519,.-curve25519
3982#endif /* WC_NO_CACHE_RESISTANT */
3983#endif /* HAVE_CURVE25519 */
3984#if defined(HAVE_ED25519) || defined(WOLFSSL_CURVE25519_USE_ED25519)
3985	.text
3986	.align	4
3987	.globl	fe_invert
3988	.type	fe_invert, %function
3989fe_invert:
3990	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
3991	sub	sp, sp, #0x88
3992	# Invert
3993	str	r0, [sp, #128]
3994	str	r1, [sp, #132]
3995	ldr	r1, [sp, #132]
3996	mov	r0, sp
3997	bl	fe_sq_op
3998	mov	r1, sp
3999	add	r0, sp, #32
4000	bl	fe_sq_op
4001	add	r1, sp, #32
4002	add	r0, sp, #32
4003	bl	fe_sq_op
4004	add	r2, sp, #32
4005	ldr	r1, [sp, #132]
4006	add	r0, sp, #32
4007	bl	fe_mul_op
4008	add	r2, sp, #32
4009	mov	r1, sp
4010	mov	r0, sp
4011	bl	fe_mul_op
4012	mov	r1, sp
4013	add	r0, sp, #0x40
4014	bl	fe_sq_op
4015	add	r2, sp, #0x40
4016	add	r1, sp, #32
4017	add	r0, sp, #32
4018	bl	fe_mul_op
4019	add	r1, sp, #32
4020	add	r0, sp, #0x40
4021	bl	fe_sq_op
4022	mov	r12, #4
4023L_fe_invert1:
4024	add	r1, sp, #0x40
4025	add	r0, sp, #0x40
4026	push	{r12}
4027	bl	fe_sq_op
4028	pop	{r12}
4029	subs	r12, r12, #1
4030	bne	L_fe_invert1
4031	add	r2, sp, #32
4032	add	r1, sp, #0x40
4033	add	r0, sp, #32
4034	bl	fe_mul_op
4035	add	r1, sp, #32
4036	add	r0, sp, #0x40
4037	bl	fe_sq_op
4038	mov	r12, #9
4039L_fe_invert2:
4040	add	r1, sp, #0x40
4041	add	r0, sp, #0x40
4042	push	{r12}
4043	bl	fe_sq_op
4044	pop	{r12}
4045	subs	r12, r12, #1
4046	bne	L_fe_invert2
4047	add	r2, sp, #32
4048	add	r1, sp, #0x40
4049	add	r0, sp, #0x40
4050	bl	fe_mul_op
4051	add	r1, sp, #0x40
4052	add	r0, sp, #0x60
4053	bl	fe_sq_op
4054	mov	r12, #19
4055L_fe_invert3:
4056	add	r1, sp, #0x60
4057	add	r0, sp, #0x60
4058	push	{r12}
4059	bl	fe_sq_op
4060	pop	{r12}
4061	subs	r12, r12, #1
4062	bne	L_fe_invert3
4063	add	r2, sp, #0x40
4064	add	r1, sp, #0x60
4065	add	r0, sp, #0x40
4066	bl	fe_mul_op
4067	mov	r12, #10
4068L_fe_invert4:
4069	add	r1, sp, #0x40
4070	add	r0, sp, #0x40
4071	push	{r12}
4072	bl	fe_sq_op
4073	pop	{r12}
4074	subs	r12, r12, #1
4075	bne	L_fe_invert4
4076	add	r2, sp, #32
4077	add	r1, sp, #0x40
4078	add	r0, sp, #32
4079	bl	fe_mul_op
4080	add	r1, sp, #32
4081	add	r0, sp, #0x40
4082	bl	fe_sq_op
4083	mov	r12, #49
4084L_fe_invert5:
4085	add	r1, sp, #0x40
4086	add	r0, sp, #0x40
4087	push	{r12}
4088	bl	fe_sq_op
4089	pop	{r12}
4090	subs	r12, r12, #1
4091	bne	L_fe_invert5
4092	add	r2, sp, #32
4093	add	r1, sp, #0x40
4094	add	r0, sp, #0x40
4095	bl	fe_mul_op
4096	add	r1, sp, #0x40
4097	add	r0, sp, #0x60
4098	bl	fe_sq_op
4099	mov	r12, #0x63
4100L_fe_invert6:
4101	add	r1, sp, #0x60
4102	add	r0, sp, #0x60
4103	push	{r12}
4104	bl	fe_sq_op
4105	pop	{r12}
4106	subs	r12, r12, #1
4107	bne	L_fe_invert6
4108	add	r2, sp, #0x40
4109	add	r1, sp, #0x60
4110	add	r0, sp, #0x40
4111	bl	fe_mul_op
4112	mov	r12, #50
4113L_fe_invert7:
4114	add	r1, sp, #0x40
4115	add	r0, sp, #0x40
4116	push	{r12}
4117	bl	fe_sq_op
4118	pop	{r12}
4119	subs	r12, r12, #1
4120	bne	L_fe_invert7
4121	add	r2, sp, #32
4122	add	r1, sp, #0x40
4123	add	r0, sp, #32
4124	bl	fe_mul_op
4125	mov	r12, #5
4126L_fe_invert8:
4127	add	r1, sp, #32
4128	add	r0, sp, #32
4129	push	{r12}
4130	bl	fe_sq_op
4131	pop	{r12}
4132	subs	r12, r12, #1
4133	bne	L_fe_invert8
4134	mov	r2, sp
4135	add	r1, sp, #32
4136	ldr	r0, [sp, #128]
4137	bl	fe_mul_op
4138	ldr	r1, [sp, #132]
4139	ldr	r0, [sp, #128]
4140	add	sp, sp, #0x88
4141	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4142	.size	fe_invert,.-fe_invert
4143#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
4144	.text
4145	.align	4
4146	.globl	fe_sq2
4147	.type	fe_sq2, %function
4148fe_sq2:
4149	push	{lr}
4150	sub	sp, sp, #0x44
4151	str	r0, [sp, #64]
4152	# Square * 2
4153	mov	r0, #0
4154	ldr	r12, [r1]
4155	# A[0] * A[1]
4156	ldr	lr, [r1, #4]
4157	umull	r4, r5, r12, lr
4158	# A[0] * A[3]
4159	ldr	lr, [r1, #12]
4160	umull	r6, r7, r12, lr
4161	# A[0] * A[5]
4162	ldr	lr, [r1, #20]
4163	umull	r8, r9, r12, lr
4164	# A[0] * A[7]
4165	ldr	lr, [r1, #28]
4166	umull	r10, r3, r12, lr
4167	# A[0] * A[2]
4168	ldr	lr, [r1, #8]
4169	mov	r11, #0
4170	umlal	r5, r11, r12, lr
4171	adds	r6, r6, r11
4172	# A[0] * A[4]
4173	ldr	lr, [r1, #16]
4174	adcs	r7, r7, #0
4175	adc	r11, r0, #0
4176	umlal	r7, r11, r12, lr
4177	adds	r8, r8, r11
4178	# A[0] * A[6]
4179	ldr	lr, [r1, #24]
4180	adcs	r9, r9, #0
4181	adc	r11, r0, #0
4182	umlal	r9, r11, r12, lr
4183	adds	r10, r10, r11
4184	adcs	r3, r3, #0
4185	str	r4, [sp, #4]
4186	str	r5, [sp, #8]
4187	# A[1] * A[2]
4188	ldr	r12, [r1, #4]
4189	ldr	lr, [r1, #8]
4190	mov	r11, #0
4191	umlal	r6, r11, r12, lr
4192	str	r6, [sp, #12]
4193	adds	r7, r7, r11
4194	# A[1] * A[3]
4195	ldr	lr, [r1, #12]
4196	adc	r11, r0, #0
4197	umlal	r7, r11, r12, lr
4198	str	r7, [sp, #16]
4199	adds	r8, r8, r11
4200	# A[1] * A[4]
4201	ldr	lr, [r1, #16]
4202	adc	r11, r0, #0
4203	umlal	r8, r11, r12, lr
4204	adds	r9, r9, r11
4205	# A[1] * A[5]
4206	ldr	lr, [r1, #20]
4207	adc	r11, r0, #0
4208	umlal	r9, r11, r12, lr
4209	adds	r10, r10, r11
4210	# A[1] * A[6]
4211	ldr	lr, [r1, #24]
4212	adc	r11, r0, #0
4213	umlal	r10, r11, r12, lr
4214	adds	r3, r3, r11
4215	# A[1] * A[7]
4216	ldr	lr, [r1, #28]
4217	adc	r4, r0, #0
4218	umlal	r3, r4, r12, lr
4219	# A[2] * A[3]
4220	ldr	r12, [r1, #8]
4221	ldr	lr, [r1, #12]
4222	mov	r11, #0
4223	umlal	r8, r11, r12, lr
4224	str	r8, [sp, #20]
4225	adds	r9, r9, r11
4226	# A[2] * A[4]
4227	ldr	lr, [r1, #16]
4228	adc	r11, r0, #0
4229	umlal	r9, r11, r12, lr
4230	str	r9, [sp, #24]
4231	adds	r10, r10, r11
4232	# A[2] * A[5]
4233	ldr	lr, [r1, #20]
4234	adc	r11, r0, #0
4235	umlal	r10, r11, r12, lr
4236	adds	r3, r3, r11
4237	# A[2] * A[6]
4238	ldr	lr, [r1, #24]
4239	adc	r11, r0, #0
4240	umlal	r3, r11, r12, lr
4241	adds	r4, r4, r11
4242	# A[2] * A[7]
4243	ldr	lr, [r1, #28]
4244	adc	r5, r0, #0
4245	umlal	r4, r5, r12, lr
4246	# A[3] * A[4]
4247	ldr	r12, [r1, #12]
4248	ldr	lr, [r1, #16]
4249	mov	r11, #0
4250	umlal	r10, r11, r12, lr
4251	str	r10, [sp, #28]
4252	adds	r3, r3, r11
4253	# A[3] * A[5]
4254	ldr	lr, [r1, #20]
4255	adc	r11, r0, #0
4256	umlal	r3, r11, r12, lr
4257	adds	r4, r4, r11
4258	# A[3] * A[6]
4259	ldr	lr, [r1, #24]
4260	adc	r11, r0, #0
4261	umlal	r4, r11, r12, lr
4262	adds	r5, r5, r11
4263	# A[3] * A[7]
4264	ldr	lr, [r1, #28]
4265	adc	r6, r0, #0
4266	umlal	r5, r6, r12, lr
4267	# A[4] * A[5]
4268	ldr	r12, [r1, #16]
4269	ldr	lr, [r1, #20]
4270	mov	r11, #0
4271	umlal	r4, r11, r12, lr
4272	adds	r5, r5, r11
4273	# A[4] * A[6]
4274	ldr	lr, [r1, #24]
4275	adc	r11, r0, #0
4276	umlal	r5, r11, r12, lr
4277	adds	r6, r6, r11
4278	# A[4] * A[7]
4279	ldr	lr, [r1, #28]
4280	adc	r7, r0, #0
4281	umlal	r6, r7, r12, lr
4282	# A[5] * A[6]
4283	ldr	r12, [r1, #20]
4284	ldr	lr, [r1, #24]
4285	mov	r11, #0
4286	umlal	r6, r11, r12, lr
4287	adds	r7, r7, r11
4288	# A[5] * A[7]
4289	ldr	lr, [r1, #28]
4290	adc	r8, r0, #0
4291	umlal	r7, r8, r12, lr
4292	# A[6] * A[7]
4293	ldr	r12, [r1, #24]
4294	ldr	lr, [r1, #28]
4295	mov	r9, #0
4296	umlal	r8, r9, r12, lr
4297	add	lr, sp, #32
4298	stm	lr, {r3, r4, r5, r6, r7, r8, r9}
4299	add	lr, sp, #4
4300	ldm	lr, {r4, r5, r6, r7, r8, r9, r10}
4301	adds	r4, r4, r4
4302	adcs	r5, r5, r5
4303	adcs	r6, r6, r6
4304	adcs	r7, r7, r7
4305	adcs	r8, r8, r8
4306	adcs	r9, r9, r9
4307	adcs	r10, r10, r10
4308	stm	lr!, {r4, r5, r6, r7, r8, r9, r10}
4309	ldm	lr, {r3, r4, r5, r6, r7, r8, r9}
4310	adcs	r3, r3, r3
4311	adcs	r4, r4, r4
4312	adcs	r5, r5, r5
4313	adcs	r6, r6, r6
4314	adcs	r7, r7, r7
4315	adcs	r8, r8, r8
4316	adcs	r9, r9, r9
4317	adc	r10, r0, #0
4318	stm	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
4319	add	lr, sp, #4
4320	ldm	lr, {r4, r5, r6, r7, r8, r9, r10}
4321	mov	lr, sp
4322	# A[0] * A[0]
4323	ldr	r12, [r1]
4324	umull	r3, r11, r12, r12
4325	adds	r4, r4, r11
4326	# A[1] * A[1]
4327	ldr	r12, [r1, #4]
4328	adcs	r5, r5, #0
4329	adc	r11, r0, #0
4330	umlal	r5, r11, r12, r12
4331	adds	r6, r6, r11
4332	# A[2] * A[2]
4333	ldr	r12, [r1, #8]
4334	adcs	r7, r7, #0
4335	adc	r11, r0, #0
4336	umlal	r7, r11, r12, r12
4337	adds	r8, r8, r11
4338	# A[3] * A[3]
4339	ldr	r12, [r1, #12]
4340	adcs	r9, r9, #0
4341	adc	r11, r0, #0
4342	umlal	r9, r11, r12, r12
4343	adds	r10, r10, r11
4344	stm	lr!, {r3, r4, r5, r6, r7, r8, r9, r10}
4345	ldm	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
4346	# A[4] * A[4]
4347	ldr	r12, [r1, #16]
4348	adcs	r3, r3, #0
4349	adc	r11, r0, #0
4350	umlal	r3, r11, r12, r12
4351	adds	r4, r4, r11
4352	# A[5] * A[5]
4353	ldr	r12, [r1, #20]
4354	adcs	r5, r5, #0
4355	adc	r11, r0, #0
4356	umlal	r5, r11, r12, r12
4357	adds	r6, r6, r11
4358	# A[6] * A[6]
4359	ldr	r12, [r1, #24]
4360	adcs	r7, r7, #0
4361	adc	r11, r0, #0
4362	umlal	r7, r11, r12, r12
4363	adds	r8, r8, r11
4364	# A[7] * A[7]
4365	ldr	r12, [r1, #28]
4366	adcs	r9, r9, #0
4367	adc	r10, r10, #0
4368	umlal	r9, r10, r12, r12
4369	# Reduce
4370	ldr	r2, [sp, #28]
4371	mov	lr, sp
4372	mov	r12, #38
4373	umull	r10, r11, r12, r10
4374	adds	r10, r10, r2
4375	adc	r11, r11, #0
4376	mov	r12, #19
4377	lsl	r11, r11, #1
4378	orr	r11, r11, r10, lsr #31
4379	mul	r11, r12, r11
4380	ldm	lr!, {r1, r2}
4381	mov	r12, #38
4382	adds	r1, r1, r11
4383	adc	r11, r0, #0
4384	umlal	r1, r11, r3, r12
4385	adds	r2, r2, r11
4386	adc	r11, r0, #0
4387	umlal	r2, r11, r4, r12
4388	ldm	lr!, {r3, r4}
4389	adds	r3, r3, r11
4390	adc	r11, r0, #0
4391	umlal	r3, r11, r5, r12
4392	adds	r4, r4, r11
4393	adc	r11, r0, #0
4394	umlal	r4, r11, r6, r12
4395	ldm	lr!, {r5, r6}
4396	adds	r5, r5, r11
4397	adc	r11, r0, #0
4398	umlal	r5, r11, r7, r12
4399	adds	r6, r6, r11
4400	adc	r11, r0, #0
4401	umlal	r6, r11, r8, r12
4402	ldm	lr!, {r7, r8}
4403	adds	r7, r7, r11
4404	adc	r11, r0, #0
4405	umlal	r7, r11, r9, r12
4406#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4407	bic	r10, r10, #0x80000000
4408#else
4409	bfc	r10, #31, #1
4410#endif
4411	adds	r8, r10, r11
4412	# Reduce if top bit set
4413	mov	r12, #19
4414	and	r11, r12, r8, asr #31
4415	adds	r1, r1, r11
4416	adcs	r2, r2, #0
4417	adcs	r3, r3, #0
4418	adcs	r4, r4, #0
4419	adcs	r5, r5, #0
4420	adcs	r6, r6, #0
4421#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4422	bic	r8, r8, #0x80000000
4423#else
4424	bfc	r8, #31, #1
4425#endif
4426	adcs	r7, r7, #0
4427	adc	r8, r8, #0
4428	# Double
4429	adds	r1, r1, r1
4430	adcs	r2, r2, r2
4431	adcs	r3, r3, r3
4432	adcs	r4, r4, r4
4433	adcs	r5, r5, r5
4434	adcs	r6, r6, r6
4435	adcs	r7, r7, r7
4436	adc	r8, r8, r8
4437	# Reduce if top bit set
4438	mov	r12, #19
4439	and	r11, r12, r8, asr #31
4440	adds	r1, r1, r11
4441	adcs	r2, r2, #0
4442	adcs	r3, r3, #0
4443	adcs	r4, r4, #0
4444	adcs	r5, r5, #0
4445	adcs	r6, r6, #0
4446#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4447	bic	r8, r8, #0x80000000
4448#else
4449	bfc	r8, #31, #1
4450#endif
4451	adcs	r7, r7, #0
4452	adc	r8, r8, #0
4453	# Store
4454	ldr	r0, [sp, #64]
4455	stm	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
4456	add	sp, sp, #0x44
4457	pop	{pc}
4458	.size	fe_sq2,.-fe_sq2
4459#else
4460	.text
4461	.align	4
4462	.globl	fe_sq2
4463	.type	fe_sq2, %function
4464fe_sq2:
4465	push	{lr}
4466	sub	sp, sp, #36
4467#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4468	str	r0, [sp, #28]
4469	str	r1, [sp, #32]
4470#else
4471	strd	r0, r1, [sp, #28]
4472#endif
4473	ldm	r1, {r0, r1, r2, r3, r4, r5, r6, r7}
4474	# Square * 2
4475	umull	r9, r10, r0, r0
4476	umull	r11, r12, r0, r1
4477	adds	r11, r11, r11
4478	mov	lr, #0
4479	umaal	r10, r11, lr, lr
4480	stm	sp, {r9, r10}
4481	mov	r8, lr
4482	umaal	r8, r12, r0, r2
4483	adcs	r8, r8, r8
4484	umaal	r8, r11, r1, r1
4485	umull	r9, r10, r0, r3
4486	umaal	r9, r12, r1, r2
4487	adcs	r9, r9, r9
4488	umaal	r9, r11, lr, lr
4489#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4490	str	r8, [sp, #8]
4491	str	r9, [sp, #12]
4492#else
4493	strd	r8, r9, [sp, #8]
4494#endif
4495	mov	r9, lr
4496	umaal	r9, r10, r0, r4
4497	umaal	r9, r12, r1, r3
4498	adcs	r9, r9, r9
4499	umaal	r9, r11, r2, r2
4500	str	r9, [sp, #16]
4501	umull	r9, r8, r0, r5
4502	umaal	r9, r12, r1, r4
4503	umaal	r9, r10, r2, r3
4504	adcs	r9, r9, r9
4505	umaal	r9, r11, lr, lr
4506	str	r9, [sp, #20]
4507	mov	r9, lr
4508	umaal	r9, r8, r0, r6
4509	umaal	r9, r12, r1, r5
4510	umaal	r9, r10, r2, r4
4511	adcs	r9, r9, r9
4512	umaal	r9, r11, r3, r3
4513	str	r9, [sp, #24]
4514	umull	r0, r9, r0, r7
4515	umaal	r0, r8, r1, r6
4516	umaal	r0, r12, r2, r5
4517	umaal	r0, r10, r3, r4
4518	adcs	r0, r0, r0
4519	umaal	r0, r11, lr, lr
4520	# R[7] = r0
4521	umaal	r9, r8, r1, r7
4522	umaal	r9, r10, r2, r6
4523	umaal	r12, r9, r3, r5
4524	adcs	r12, r12, r12
4525	umaal	r12, r11, r4, r4
4526	# R[8] = r12
4527	umaal	r9, r8, r2, r7
4528	umaal	r10, r9, r3, r6
4529	mov	r2, lr
4530	umaal	r10, r2, r4, r5
4531	adcs	r10, r10, r10
4532	umaal	r11, r10, lr, lr
4533	# R[9] = r11
4534	umaal	r2, r8, r3, r7
4535	umaal	r2, r9, r4, r6
4536	adcs	r3, r2, r2
4537	umaal	r10, r3, r5, r5
4538	# R[10] = r10
4539	mov	r1, lr
4540	umaal	r1, r8, r4, r7
4541	umaal	r1, r9, r5, r6
4542	adcs	r4, r1, r1
4543	umaal	r3, r4, lr, lr
4544	# R[11] = r3
4545	umaal	r8, r9, r5, r7
4546	adcs	r8, r8, r8
4547	umaal	r4, r8, r6, r6
4548	# R[12] = r4
4549	mov	r5, lr
4550	umaal	r5, r9, r6, r7
4551	adcs	r5, r5, r5
4552	umaal	r8, r5, lr, lr
4553	# R[13] = r8
4554	adcs	r9, r9, r9
4555	umaal	r9, r5, r7, r7
4556	adcs	r7, r5, lr
4557	# R[14] = r9
4558	# R[15] = r7
4559	# Reduce
4560	mov	r6, #37
4561	umaal	r7, r0, r7, r6
4562	mov	r6, #19
4563	lsl	r0, r0, #1
4564	orr	r0, r0, r7, lsr #31
4565	mul	lr, r0, r6
4566	pop	{r0-r1}
4567	mov	r6, #38
4568	umaal	r0, lr, r12, r6
4569	umaal	r1, lr, r11, r6
4570	mov	r12, r3
4571	mov	r11, r4
4572	pop	{r2-r4}
4573	umaal	r2, lr, r10, r6
4574	umaal	r3, lr, r12, r6
4575	umaal	r4, lr, r11, r6
4576	mov	r12, r6
4577	pop	{r5-r6}
4578	umaal	r5, lr, r8, r12
4579#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4580	bic	r7, r7, #0x80000000
4581#else
4582	bfc	r7, #31, #1
4583#endif
4584	umaal	r6, lr, r9, r12
4585	add	r7, r7, lr
4586	# Reduce if top bit set
4587	mov	r11, #19
4588	and	r12, r11, r7, asr #31
4589	adds	r0, r0, r12
4590	adcs	r1, r1, #0
4591	adcs	r2, r2, #0
4592	adcs	r3, r3, #0
4593	adcs	r4, r4, #0
4594	adcs	r5, r5, #0
4595#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4596	bic	r7, r7, #0x80000000
4597#else
4598	bfc	r7, #31, #1
4599#endif
4600	adcs	r6, r6, #0
4601	adc	r7, r7, #0
4602	# Double
4603	adds	r0, r0, r0
4604	adcs	r1, r1, r1
4605	adcs	r2, r2, r2
4606	adcs	r3, r3, r3
4607	adcs	r4, r4, r4
4608	adcs	r5, r5, r5
4609	adcs	r6, r6, r6
4610	adc	r7, r7, r7
4611	# Reduce if top bit set
4612	mov	r11, #19
4613	and	r12, r11, r7, asr #31
4614	adds	r0, r0, r12
4615	adcs	r1, r1, #0
4616	adcs	r2, r2, #0
4617	adcs	r3, r3, #0
4618	adcs	r4, r4, #0
4619	adcs	r5, r5, #0
4620#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4621	bic	r7, r7, #0x80000000
4622#else
4623	bfc	r7, #31, #1
4624#endif
4625	adcs	r6, r6, #0
4626	adc	r7, r7, #0
4627	pop	{r12, lr}
4628	# Store
4629	stm	r12, {r0, r1, r2, r3, r4, r5, r6, r7}
4630	mov	r0, r12
4631	mov	r1, lr
4632	pop	{pc}
4633	.size	fe_sq2,.-fe_sq2
4634#endif /* WOLFSSL_ARM_ARCH && WOLFSSL_ARM_ARCH < 6 */
4635	.text
4636	.align	4
4637	.globl	fe_pow22523
4638	.type	fe_pow22523, %function
4639fe_pow22523:
4640	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4641	sub	sp, sp, #0x68
4642	# pow22523
4643	str	r0, [sp, #96]
4644	str	r1, [sp, #100]
4645	ldr	r1, [sp, #100]
4646	mov	r0, sp
4647	bl	fe_sq_op
4648	mov	r1, sp
4649	add	r0, sp, #32
4650	bl	fe_sq_op
4651	add	r1, sp, #32
4652	add	r0, sp, #32
4653	bl	fe_sq_op
4654	add	r2, sp, #32
4655	ldr	r1, [sp, #100]
4656	add	r0, sp, #32
4657	bl	fe_mul_op
4658	add	r2, sp, #32
4659	mov	r1, sp
4660	mov	r0, sp
4661	bl	fe_mul_op
4662	mov	r1, sp
4663	mov	r0, sp
4664	bl	fe_sq_op
4665	mov	r2, sp
4666	add	r1, sp, #32
4667	mov	r0, sp
4668	bl	fe_mul_op
4669	mov	r1, sp
4670	add	r0, sp, #32
4671	bl	fe_sq_op
4672	mov	r12, #4
4673L_fe_pow22523_1:
4674	add	r1, sp, #32
4675	add	r0, sp, #32
4676	push	{r12}
4677	bl	fe_sq_op
4678	pop	{r12}
4679	subs	r12, r12, #1
4680	bne	L_fe_pow22523_1
4681	mov	r2, sp
4682	add	r1, sp, #32
4683	mov	r0, sp
4684	bl	fe_mul_op
4685	mov	r1, sp
4686	add	r0, sp, #32
4687	bl	fe_sq_op
4688	mov	r12, #9
4689L_fe_pow22523_2:
4690	add	r1, sp, #32
4691	add	r0, sp, #32
4692	push	{r12}
4693	bl	fe_sq_op
4694	pop	{r12}
4695	subs	r12, r12, #1
4696	bne	L_fe_pow22523_2
4697	mov	r2, sp
4698	add	r1, sp, #32
4699	add	r0, sp, #32
4700	bl	fe_mul_op
4701	add	r1, sp, #32
4702	add	r0, sp, #0x40
4703	bl	fe_sq_op
4704	mov	r12, #19
4705L_fe_pow22523_3:
4706	add	r1, sp, #0x40
4707	add	r0, sp, #0x40
4708	push	{r12}
4709	bl	fe_sq_op
4710	pop	{r12}
4711	subs	r12, r12, #1
4712	bne	L_fe_pow22523_3
4713	add	r2, sp, #32
4714	add	r1, sp, #0x40
4715	add	r0, sp, #32
4716	bl	fe_mul_op
4717	mov	r12, #10
4718L_fe_pow22523_4:
4719	add	r1, sp, #32
4720	add	r0, sp, #32
4721	push	{r12}
4722	bl	fe_sq_op
4723	pop	{r12}
4724	subs	r12, r12, #1
4725	bne	L_fe_pow22523_4
4726	mov	r2, sp
4727	add	r1, sp, #32
4728	mov	r0, sp
4729	bl	fe_mul_op
4730	mov	r1, sp
4731	add	r0, sp, #32
4732	bl	fe_sq_op
4733	mov	r12, #49
4734L_fe_pow22523_5:
4735	add	r1, sp, #32
4736	add	r0, sp, #32
4737	push	{r12}
4738	bl	fe_sq_op
4739	pop	{r12}
4740	subs	r12, r12, #1
4741	bne	L_fe_pow22523_5
4742	mov	r2, sp
4743	add	r1, sp, #32
4744	add	r0, sp, #32
4745	bl	fe_mul_op
4746	add	r1, sp, #32
4747	add	r0, sp, #0x40
4748	bl	fe_sq_op
4749	mov	r12, #0x63
4750L_fe_pow22523_6:
4751	add	r1, sp, #0x40
4752	add	r0, sp, #0x40
4753	push	{r12}
4754	bl	fe_sq_op
4755	pop	{r12}
4756	subs	r12, r12, #1
4757	bne	L_fe_pow22523_6
4758	add	r2, sp, #32
4759	add	r1, sp, #0x40
4760	add	r0, sp, #32
4761	bl	fe_mul_op
4762	mov	r12, #50
4763L_fe_pow22523_7:
4764	add	r1, sp, #32
4765	add	r0, sp, #32
4766	push	{r12}
4767	bl	fe_sq_op
4768	pop	{r12}
4769	subs	r12, r12, #1
4770	bne	L_fe_pow22523_7
4771	mov	r2, sp
4772	add	r1, sp, #32
4773	mov	r0, sp
4774	bl	fe_mul_op
4775	mov	r12, #2
4776L_fe_pow22523_8:
4777	mov	r1, sp
4778	mov	r0, sp
4779	push	{r12}
4780	bl	fe_sq_op
4781	pop	{r12}
4782	subs	r12, r12, #1
4783	bne	L_fe_pow22523_8
4784	ldr	r2, [sp, #100]
4785	mov	r1, sp
4786	ldr	r0, [sp, #96]
4787	bl	fe_mul_op
4788	ldr	r1, [sp, #100]
4789	ldr	r0, [sp, #96]
4790	add	sp, sp, #0x68
4791	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4792	.size	fe_pow22523,.-fe_pow22523
4793	.text
4794	.align	4
4795	.globl	ge_p1p1_to_p2
4796	.type	ge_p1p1_to_p2, %function
4797ge_p1p1_to_p2:
4798	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4799	sub	sp, sp, #8
4800	str	r0, [sp]
4801	str	r1, [sp, #4]
4802	add	r2, r1, #0x60
4803	bl	fe_mul_op
4804	ldr	r0, [sp]
4805	ldr	r1, [sp, #4]
4806	add	r2, r1, #0x40
4807	add	r1, r1, #32
4808	add	r0, r0, #32
4809	bl	fe_mul_op
4810	ldr	r0, [sp]
4811	ldr	r1, [sp, #4]
4812	add	r2, r1, #0x60
4813	add	r1, r1, #0x40
4814	add	r0, r0, #0x40
4815	bl	fe_mul_op
4816	add	sp, sp, #8
4817	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4818	.size	ge_p1p1_to_p2,.-ge_p1p1_to_p2
4819	.text
4820	.align	4
4821	.globl	ge_p1p1_to_p3
4822	.type	ge_p1p1_to_p3, %function
4823ge_p1p1_to_p3:
4824	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4825	sub	sp, sp, #8
4826	str	r0, [sp]
4827	str	r1, [sp, #4]
4828	add	r2, r1, #0x60
4829	bl	fe_mul_op
4830	ldr	r0, [sp]
4831	ldr	r1, [sp, #4]
4832	add	r2, r1, #0x40
4833	add	r1, r1, #32
4834	add	r0, r0, #32
4835	bl	fe_mul_op
4836	ldr	r0, [sp]
4837	ldr	r1, [sp, #4]
4838	add	r2, r1, #0x60
4839	add	r1, r1, #0x40
4840	add	r0, r0, #0x40
4841	bl	fe_mul_op
4842	ldr	r0, [sp]
4843	ldr	r1, [sp, #4]
4844	add	r2, r1, #32
4845	add	r0, r0, #0x60
4846	bl	fe_mul_op
4847	add	sp, sp, #8
4848	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4849	.size	ge_p1p1_to_p3,.-ge_p1p1_to_p3
4850	.text
4851	.align	4
4852	.globl	ge_p2_dbl
4853	.type	ge_p2_dbl, %function
4854ge_p2_dbl:
4855	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4856	sub	sp, sp, #8
4857	str	r0, [sp]
4858	str	r1, [sp, #4]
4859	bl	fe_sq_op
4860	ldr	r0, [sp]
4861	ldr	r1, [sp, #4]
4862	add	r1, r1, #32
4863	add	r0, r0, #0x40
4864	bl	fe_sq_op
4865	ldr	r0, [sp]
4866	ldr	r1, [sp, #4]
4867	add	r2, r1, #32
4868	add	r0, r0, #32
4869	bl	fe_add_op
4870	mov	r1, r0
4871	add	r0, r0, #0x40
4872	bl	fe_sq_op
4873	ldr	r0, [sp]
4874	mov	r3, r0
4875	add	r2, r0, #0x40
4876	add	r1, r0, #0x40
4877	add	r0, r0, #32
4878	bl	fe_add_sub_op
4879	mov	r2, r0
4880	add	r1, r0, #0x40
4881	sub	r0, r0, #32
4882	bl	fe_sub_op
4883	ldr	r1, [sp, #4]
4884	add	r1, r1, #0x40
4885	add	r0, r0, #0x60
4886	bl	fe_sq2
4887	sub	r2, r0, #32
4888	mov	r1, r0
4889	bl	fe_sub_op
4890	add	sp, sp, #8
4891	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4892	.size	ge_p2_dbl,.-ge_p2_dbl
4893	.text
4894	.align	4
4895	.globl	ge_madd
4896	.type	ge_madd, %function
4897ge_madd:
4898	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4899	sub	sp, sp, #12
4900	str	r0, [sp]
4901	str	r1, [sp, #4]
4902	str	r2, [sp, #8]
4903	mov	r2, r1
4904	add	r1, r1, #32
4905	bl	fe_add_op
4906	ldr	r1, [sp, #4]
4907	mov	r2, r1
4908	add	r1, r1, #32
4909	add	r0, r0, #32
4910	bl	fe_sub_op
4911	ldr	r2, [sp, #8]
4912	sub	r1, r0, #32
4913	add	r0, r0, #32
4914	bl	fe_mul_op
4915	ldr	r0, [sp]
4916	ldr	r2, [sp, #8]
4917	add	r2, r2, #32
4918	add	r1, r0, #32
4919	add	r0, r0, #32
4920	bl	fe_mul_op
4921	ldr	r0, [sp]
4922	ldr	r1, [sp, #8]
4923	ldr	r2, [sp, #4]
4924	add	r2, r2, #0x60
4925	add	r1, r1, #0x40
4926	add	r0, r0, #0x60
4927	bl	fe_mul_op
4928	ldr	r0, [sp]
4929	add	r3, r0, #32
4930	add	r2, r0, #0x40
4931	mov	r1, r0
4932	add	r0, r0, #32
4933	bl	fe_add_sub_op
4934	ldr	r1, [sp, #4]
4935	add	r1, r1, #0x40
4936	add	r0, r0, #32
4937	# Double
4938	ldm	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
4939	adds	r4, r4, r4
4940	adcs	r5, r5, r5
4941	adcs	r6, r6, r6
4942	adcs	r7, r7, r7
4943	adcs	r8, r8, r8
4944	adcs	r9, r9, r9
4945	adcs	r10, r10, r10
4946	mov	lr, #0
4947	adcs	r11, r11, r11
4948	adc	lr, lr, #0
4949	mov	r12, #19
4950	lsl	lr, lr, #1
4951	orr	lr, lr, r11, lsr #31
4952	mul	r12, lr, r12
4953	adds	r4, r4, r12
4954	adcs	r5, r5, #0
4955	adcs	r6, r6, #0
4956	adcs	r7, r7, #0
4957	adcs	r8, r8, #0
4958	adcs	r9, r9, #0
4959#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
4960	bic	r11, r11, #0x80000000
4961#else
4962	bfc	r11, #31, #1
4963#endif
4964	adcs	r10, r10, #0
4965	adc	r11, r11, #0
4966	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
4967	# Done Double
4968	add	r3, r0, #32
4969	add	r1, r0, #32
4970	bl	fe_add_sub_op
4971	add	sp, sp, #12
4972	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4973	.size	ge_madd,.-ge_madd
4974	.text
4975	.align	4
4976	.globl	ge_msub
4977	.type	ge_msub, %function
4978ge_msub:
4979	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4980	sub	sp, sp, #12
4981	str	r0, [sp]
4982	str	r1, [sp, #4]
4983	str	r2, [sp, #8]
4984	mov	r2, r1
4985	add	r1, r1, #32
4986	bl	fe_add_op
4987	ldr	r1, [sp, #4]
4988	mov	r2, r1
4989	add	r1, r1, #32
4990	add	r0, r0, #32
4991	bl	fe_sub_op
4992	ldr	r2, [sp, #8]
4993	add	r2, r2, #32
4994	sub	r1, r0, #32
4995	add	r0, r0, #32
4996	bl	fe_mul_op
4997	ldr	r0, [sp]
4998	ldr	r2, [sp, #8]
4999	add	r1, r0, #32
5000	add	r0, r0, #32
5001	bl	fe_mul_op
5002	ldr	r0, [sp]
5003	ldr	r1, [sp, #8]
5004	ldr	r2, [sp, #4]
5005	add	r2, r2, #0x60
5006	add	r1, r1, #0x40
5007	add	r0, r0, #0x60
5008	bl	fe_mul_op
5009	ldr	r0, [sp]
5010	add	r3, r0, #32
5011	add	r2, r0, #0x40
5012	mov	r1, r0
5013	add	r0, r0, #32
5014	bl	fe_add_sub_op
5015	ldr	r1, [sp, #4]
5016	add	r1, r1, #0x40
5017	add	r0, r0, #32
5018	# Double
5019	ldm	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
5020	adds	r4, r4, r4
5021	adcs	r5, r5, r5
5022	adcs	r6, r6, r6
5023	adcs	r7, r7, r7
5024	adcs	r8, r8, r8
5025	adcs	r9, r9, r9
5026	adcs	r10, r10, r10
5027	mov	lr, #0
5028	adcs	r11, r11, r11
5029	adc	lr, lr, #0
5030	mov	r12, #19
5031	lsl	lr, lr, #1
5032	orr	lr, lr, r11, lsr #31
5033	mul	r12, lr, r12
5034	adds	r4, r4, r12
5035	adcs	r5, r5, #0
5036	adcs	r6, r6, #0
5037	adcs	r7, r7, #0
5038	adcs	r8, r8, #0
5039	adcs	r9, r9, #0
5040#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5041	bic	r11, r11, #0x80000000
5042#else
5043	bfc	r11, #31, #1
5044#endif
5045	adcs	r10, r10, #0
5046	adc	r11, r11, #0
5047	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
5048	# Done Double
5049	add	r3, r0, #32
5050	mov	r1, r0
5051	add	r0, r0, #32
5052	bl	fe_add_sub_op
5053	add	sp, sp, #12
5054	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
5055	.size	ge_msub,.-ge_msub
5056	.text
5057	.align	4
5058	.globl	ge_add
5059	.type	ge_add, %function
5060ge_add:
5061	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
5062	sub	sp, sp, #44
5063	str	r0, [sp]
5064	str	r1, [sp, #4]
5065	str	r2, [sp, #8]
5066	mov	r3, r1
5067	add	r2, r1, #32
5068	add	r1, r0, #32
5069	bl	fe_add_sub_op
5070	ldr	r2, [sp, #8]
5071	mov	r1, r0
5072	add	r0, r0, #0x40
5073	bl	fe_mul_op
5074	ldr	r0, [sp]
5075	ldr	r2, [sp, #8]
5076	add	r2, r2, #32
5077	add	r1, r0, #32
5078	add	r0, r0, #32
5079	bl	fe_mul_op
5080	ldr	r0, [sp]
5081	ldr	r1, [sp, #8]
5082	ldr	r2, [sp, #4]
5083	add	r2, r2, #0x60
5084	add	r1, r1, #0x60
5085	add	r0, r0, #0x60
5086	bl	fe_mul_op
5087	ldr	r0, [sp]
5088	ldr	r1, [sp, #4]
5089	ldr	r2, [sp, #8]
5090	add	r2, r2, #0x40
5091	add	r1, r1, #0x40
5092	bl	fe_mul_op
5093	ldr	r1, [sp]
5094	add	r0, sp, #12
5095	# Double
5096	ldm	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
5097	adds	r4, r4, r4
5098	adcs	r5, r5, r5
5099	adcs	r6, r6, r6
5100	adcs	r7, r7, r7
5101	adcs	r8, r8, r8
5102	adcs	r9, r9, r9
5103	adcs	r10, r10, r10
5104	mov	lr, #0
5105	adcs	r11, r11, r11
5106	adc	lr, lr, #0
5107	mov	r12, #19
5108	lsl	lr, lr, #1
5109	orr	lr, lr, r11, lsr #31
5110	mul	r12, lr, r12
5111	adds	r4, r4, r12
5112	adcs	r5, r5, #0
5113	adcs	r6, r6, #0
5114	adcs	r7, r7, #0
5115	adcs	r8, r8, #0
5116	adcs	r9, r9, #0
5117#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5118	bic	r11, r11, #0x80000000
5119#else
5120	bfc	r11, #31, #1
5121#endif
5122	adcs	r10, r10, #0
5123	adc	r11, r11, #0
5124	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
5125	# Done Double
5126	add	r3, r1, #32
5127	add	r2, r1, #0x40
5128	add	r0, r1, #32
5129	bl	fe_add_sub_op
5130	add	r3, r0, #0x40
5131	add	r2, sp, #12
5132	add	r1, r0, #0x40
5133	add	r0, r0, #32
5134	bl	fe_add_sub_op
5135	add	sp, sp, #44
5136	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
5137	.size	ge_add,.-ge_add
5138	.text
5139	.align	4
5140	.globl	ge_sub
5141	.type	ge_sub, %function
5142ge_sub:
5143	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
5144	sub	sp, sp, #44
5145	str	r0, [sp]
5146	str	r1, [sp, #4]
5147	str	r2, [sp, #8]
5148	mov	r3, r1
5149	add	r2, r1, #32
5150	add	r1, r0, #32
5151	bl	fe_add_sub_op
5152	ldr	r2, [sp, #8]
5153	add	r2, r2, #32
5154	mov	r1, r0
5155	add	r0, r0, #0x40
5156	bl	fe_mul_op
5157	ldr	r0, [sp]
5158	ldr	r2, [sp, #8]
5159	add	r1, r0, #32
5160	add	r0, r0, #32
5161	bl	fe_mul_op
5162	ldr	r0, [sp]
5163	ldr	r1, [sp, #8]
5164	ldr	r2, [sp, #4]
5165	add	r2, r2, #0x60
5166	add	r1, r1, #0x60
5167	add	r0, r0, #0x60
5168	bl	fe_mul_op
5169	ldr	r0, [sp]
5170	ldr	r1, [sp, #4]
5171	ldr	r2, [sp, #8]
5172	add	r2, r2, #0x40
5173	add	r1, r1, #0x40
5174	bl	fe_mul_op
5175	ldr	r1, [sp]
5176	add	r0, sp, #12
5177	# Double
5178	ldm	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
5179	adds	r4, r4, r4
5180	adcs	r5, r5, r5
5181	adcs	r6, r6, r6
5182	adcs	r7, r7, r7
5183	adcs	r8, r8, r8
5184	adcs	r9, r9, r9
5185	adcs	r10, r10, r10
5186	mov	lr, #0
5187	adcs	r11, r11, r11
5188	adc	lr, lr, #0
5189	mov	r12, #19
5190	lsl	lr, lr, #1
5191	orr	lr, lr, r11, lsr #31
5192	mul	r12, lr, r12
5193	adds	r4, r4, r12
5194	adcs	r5, r5, #0
5195	adcs	r6, r6, #0
5196	adcs	r7, r7, #0
5197	adcs	r8, r8, #0
5198	adcs	r9, r9, #0
5199#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5200	bic	r11, r11, #0x80000000
5201#else
5202	bfc	r11, #31, #1
5203#endif
5204	adcs	r10, r10, #0
5205	adc	r11, r11, #0
5206	stm	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
5207	# Done Double
5208	add	r3, r1, #32
5209	add	r2, r1, #0x40
5210	add	r0, r1, #32
5211	bl	fe_add_sub_op
5212	add	r3, r0, #0x40
5213	add	r2, sp, #12
5214	add	r1, r0, #32
5215	add	r0, r0, #0x40
5216	bl	fe_add_sub_op
5217	add	sp, sp, #44
5218	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
5219	.size	ge_sub,.-ge_sub
5220#endif /* HAVE_ED25519 || WOLFSSL_CURVE25519_USE_ED25519 */
5221#ifdef HAVE_ED25519
5222#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
5223	.text
5224	.align	4
5225	.globl	sc_reduce
5226	.type	sc_reduce, %function
5227sc_reduce:
5228	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
5229	sub	sp, sp, #56
5230	str	r0, [sp, #52]
5231	# Load bits 252-511
5232	add	r0, r0, #28
5233	ldm	r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9}
5234	lsr	lr, r9, #24
5235	lsl	r9, r9, #4
5236	orr	r9, r9, r8, lsr #28
5237	lsl	r8, r8, #4
5238	orr	r8, r8, r7, lsr #28
5239	lsl	r7, r7, #4
5240	orr	r7, r7, r6, lsr #28
5241	lsl	r6, r6, #4
5242	orr	r6, r6, r5, lsr #28
5243	lsl	r5, r5, #4
5244	orr	r5, r5, r4, lsr #28
5245	lsl	r4, r4, #4
5246	orr	r4, r4, r3, lsr #28
5247	lsl	r3, r3, #4
5248	orr	r3, r3, r2, lsr #28
5249	lsl	r2, r2, #4
5250	orr	r2, r2, r1, lsr #28
5251#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5252	bic	r9, r9, #0xf0000000
5253#else
5254	bfc	r9, #28, #4
5255#endif
5256	sub	r0, r0, #28
5257	# Add order times bits 504..511
5258#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5259	mov	r10, #19
5260	orr	r10, r10, #0xa3000000
5261	orr	r10, r10, #0xa0000
5262	orr	r10, r10, #0x2c00
5263#else
5264#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5265	mov	r10, #0x13
5266	orr	r10, r10, #0x2c00
5267#else
5268	mov	r10, #0x2c13
5269#endif
5270#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5271	orr	r10, r10, #0xa3000000
5272	orr	r10, r10, #0xa0000
5273#else
5274	movt	r10, #0xa30a
5275#endif
5276#endif
5277#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5278	mov	r11, #0xe5
5279	orr	r11, r11, #0xa7000000
5280	orr	r11, r11, #0xed0000
5281	orr	r11, r11, #0x9c00
5282#else
5283#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5284	mov	r11, #0xe5
5285	orr	r11, r11, #0x9c00
5286#else
5287	mov	r11, #0x9ce5
5288#endif
5289#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5290	orr	r11, r11, #0xa7000000
5291	orr	r11, r11, #0xed0000
5292#else
5293	movt	r11, #0xa7ed
5294#endif
5295#endif
5296	mov	r1, #0
5297	umlal	r2, r1, r10, lr
5298	adds	r3, r3, r1
5299	mov	r1, #0
5300	adc	r1, r1, #0
5301	umlal	r3, r1, r11, lr
5302#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5303	mov	r10, #41
5304	orr	r10, r10, #0x5d000000
5305	orr	r10, r10, #0x80000
5306	orr	r10, r10, #0x6300
5307#else
5308#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5309	mov	r10, #0x29
5310	orr	r10, r10, #0x6300
5311#else
5312	mov	r10, #0x6329
5313#endif
5314#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5315	orr	r10, r10, #0x5d000000
5316	orr	r10, r10, #0x80000
5317#else
5318	movt	r10, #0x5d08
5319#endif
5320#endif
5321#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5322	mov	r11, #33
5323	orr	r11, r11, #0xeb000000
5324	orr	r11, r11, #0x210000
5325	orr	r11, r11, #0x600
5326#else
5327#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5328	mov	r11, #0x21
5329	orr	r11, r11, #0x600
5330#else
5331	mov	r11, #0x621
5332#endif
5333#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5334	orr	r11, r11, #0xeb000000
5335	orr	r11, r11, #0x210000
5336#else
5337	movt	r11, #0xeb21
5338#endif
5339#endif
5340	adds	r4, r4, r1
5341	mov	r1, #0
5342	adc	r1, r1, #0
5343	umlal	r4, r1, r10, lr
5344	adds	r5, r5, r1
5345	mov	r1, #0
5346	adc	r1, r1, #0
5347	umlal	r5, r1, r11, lr
5348	adds	r6, r6, r1
5349	adcs	r7, r7, #0
5350	adcs	r8, r8, #0
5351	adc	r9, r9, #0
5352	subs	r6, r6, lr
5353	sbcs	r7, r7, #0
5354	sbcs	r8, r8, #0
5355	sbc	r9, r9, #0
5356	# Sub product of top 8 words and order
5357	mov	r12, sp
5358#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5359	mov	r1, #19
5360	orr	r1, r1, #0xa3000000
5361	orr	r1, r1, #0xa0000
5362	orr	r1, r1, #0x2c00
5363#else
5364#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5365	mov	r1, #0x13
5366	orr	r1, r1, #0x2c00
5367#else
5368	mov	r1, #0x2c13
5369#endif
5370#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5371	orr	r1, r1, #0xa3000000
5372	orr	r1, r1, #0xa0000
5373#else
5374	movt	r1, #0xa30a
5375#endif
5376#endif
5377	mov	lr, #0
5378	ldm	r0!, {r10, r11}
5379	umlal	r10, lr, r2, r1
5380	adds	r11, r11, lr
5381	mov	lr, #0
5382	adc	lr, lr, #0
5383	umlal	r11, lr, r3, r1
5384	stm	r12!, {r10, r11}
5385	ldm	r0!, {r10, r11}
5386	adds	r10, r10, lr
5387	mov	lr, #0
5388	adc	lr, lr, #0
5389	umlal	r10, lr, r4, r1
5390	adds	r11, r11, lr
5391	mov	lr, #0
5392	adc	lr, lr, #0
5393	umlal	r11, lr, r5, r1
5394	stm	r12!, {r10, r11}
5395	ldm	r0!, {r10, r11}
5396	adds	r10, r10, lr
5397	mov	lr, #0
5398	adc	lr, lr, #0
5399	umlal	r10, lr, r6, r1
5400	adds	r11, r11, lr
5401	mov	lr, #0
5402	adc	lr, lr, #0
5403	umlal	r11, lr, r7, r1
5404	stm	r12!, {r10, r11}
5405	ldm	r0!, {r10, r11}
5406	adds	r10, r10, lr
5407	mov	lr, #0
5408	adc	lr, lr, #0
5409	umlal	r10, lr, r8, r1
5410#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5411	bic	r11, r11, #0xf0000000
5412#else
5413	bfc	r11, #28, #4
5414#endif
5415	adds	r11, r11, lr
5416	mov	lr, #0
5417	adc	lr, lr, #0
5418	umlal	r11, lr, r9, r1
5419	stm	r12!, {r10, r11, lr}
5420	sub	r0, r0, #16
5421	sub	r12, r12, #32
5422#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5423	mov	r1, #0xe5
5424	orr	r1, r1, #0xa7000000
5425	orr	r1, r1, #0xed0000
5426	orr	r1, r1, #0x9c00
5427#else
5428#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5429	mov	r1, #0xe5
5430	orr	r1, r1, #0x9c00
5431#else
5432	mov	r1, #0x9ce5
5433#endif
5434#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5435	orr	r1, r1, #0xa7000000
5436	orr	r1, r1, #0xed0000
5437#else
5438	movt	r1, #0xa7ed
5439#endif
5440#endif
5441	mov	lr, #0
5442	ldm	r12, {r10, r11}
5443	umlal	r10, lr, r2, r1
5444	adds	r11, r11, lr
5445	mov	lr, #0
5446	adc	lr, lr, #0
5447	umlal	r11, lr, r3, r1
5448	stm	r12!, {r10, r11}
5449	ldm	r12, {r10, r11}
5450	adds	r10, r10, lr
5451	mov	lr, #0
5452	adc	lr, lr, #0
5453	umlal	r10, lr, r4, r1
5454	adds	r11, r11, lr
5455	mov	lr, #0
5456	adc	lr, lr, #0
5457	umlal	r11, lr, r5, r1
5458	stm	r12!, {r10, r11}
5459	ldm	r12, {r10, r11}
5460	adds	r10, r10, lr
5461	mov	lr, #0
5462	adc	lr, lr, #0
5463	umlal	r10, lr, r6, r1
5464	adds	r11, r11, lr
5465	mov	lr, #0
5466	adc	lr, lr, #0
5467	umlal	r11, lr, r7, r1
5468	stm	r12!, {r10, r11}
5469	ldm	r12, {r10, r11}
5470	adds	r10, r10, lr
5471	mov	lr, #0
5472	adc	lr, lr, #0
5473	umlal	r10, lr, r8, r1
5474	adds	r11, r11, lr
5475	mov	lr, #0
5476	adc	lr, lr, #0
5477	umlal	r11, lr, r9, r1
5478	stm	r12!, {r10, r11, lr}
5479	sub	r12, r12, #32
5480#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5481	mov	r1, #41
5482	orr	r1, r1, #0x5d000000
5483	orr	r1, r1, #0x80000
5484	orr	r1, r1, #0x6300
5485#else
5486#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5487	mov	r1, #0x29
5488	orr	r1, r1, #0x6300
5489#else
5490	mov	r1, #0x6329
5491#endif
5492#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5493	orr	r1, r1, #0x5d000000
5494	orr	r1, r1, #0x80000
5495#else
5496	movt	r1, #0x5d08
5497#endif
5498#endif
5499	mov	lr, #0
5500	ldm	r12, {r10, r11}
5501	umlal	r10, lr, r2, r1
5502	adds	r11, r11, lr
5503	mov	lr, #0
5504	adc	lr, lr, #0
5505	umlal	r11, lr, r3, r1
5506	stm	r12!, {r10, r11}
5507	ldm	r12, {r10, r11}
5508	adds	r10, r10, lr
5509	mov	lr, #0
5510	adc	lr, lr, #0
5511	umlal	r10, lr, r4, r1
5512	adds	r11, r11, lr
5513	mov	lr, #0
5514	adc	lr, lr, #0
5515	umlal	r11, lr, r5, r1
5516	stm	r12!, {r10, r11}
5517	ldm	r12, {r10, r11}
5518	adds	r10, r10, lr
5519	mov	lr, #0
5520	adc	lr, lr, #0
5521	umlal	r10, lr, r6, r1
5522	adds	r11, r11, lr
5523	mov	lr, #0
5524	adc	lr, lr, #0
5525	umlal	r11, lr, r7, r1
5526	stm	r12!, {r10, r11}
5527	ldm	r12, {r10, r11}
5528	adds	r10, r10, lr
5529	mov	lr, #0
5530	adc	lr, lr, #0
5531	umlal	r10, lr, r8, r1
5532	adds	r11, r11, lr
5533	mov	lr, #0
5534	adc	lr, lr, #0
5535	umlal	r11, lr, r9, r1
5536	stm	r12!, {r10, r11, lr}
5537	sub	r12, r12, #32
5538#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5539	mov	r1, #33
5540	orr	r1, r1, #0xeb000000
5541	orr	r1, r1, #0x210000
5542	orr	r1, r1, #0x600
5543#else
5544#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5545	mov	r1, #0x21
5546	orr	r1, r1, #0x600
5547#else
5548	mov	r1, #0x621
5549#endif
5550#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5551	orr	r1, r1, #0xeb000000
5552	orr	r1, r1, #0x210000
5553#else
5554	movt	r1, #0xeb21
5555#endif
5556#endif
5557	mov	lr, #0
5558	ldm	r12, {r10, r11}
5559	umlal	r10, lr, r2, r1
5560	adds	r11, r11, lr
5561	mov	lr, #0
5562	adc	lr, lr, #0
5563	umlal	r11, lr, r3, r1
5564	stm	r12!, {r10, r11}
5565	ldm	r12, {r10, r11}
5566	adds	r10, r10, lr
5567	mov	lr, #0
5568	adc	lr, lr, #0
5569	umlal	r10, lr, r4, r1
5570	adds	r11, r11, lr
5571	mov	lr, #0
5572	adc	lr, lr, #0
5573	umlal	r11, lr, r5, r1
5574	stm	r12!, {r10, r11}
5575	ldm	r12, {r10, r11}
5576	adds	r10, r10, lr
5577	mov	lr, #0
5578	adc	lr, lr, #0
5579	umlal	r10, lr, r6, r1
5580	adds	r11, r11, lr
5581	mov	lr, #0
5582	adc	lr, lr, #0
5583	umlal	r11, lr, r7, r1
5584	stm	r12!, {r10, r11}
5585	ldm	r12, {r10, r11}
5586	adds	r10, r10, lr
5587	mov	lr, #0
5588	adc	lr, lr, #0
5589	umlal	r10, lr, r8, r1
5590	adds	r11, r11, lr
5591	mov	lr, #0
5592	adc	lr, lr, #0
5593	umlal	r11, lr, r9, r1
5594	stm	r12!, {r10, r11, lr}
5595	sub	r12, r12, #32
5596	# Subtract at 4 * 32
5597	ldm	r12, {r10, r11}
5598	subs	r10, r10, r2
5599	sbcs	r11, r11, r3
5600	stm	r12!, {r10, r11}
5601	ldm	r12, {r10, r11}
5602	sbcs	r10, r10, r4
5603	sbcs	r11, r11, r5
5604	stm	r12!, {r10, r11}
5605	ldm	r12, {r10, r11}
5606	sbcs	r10, r10, r6
5607	sbcs	r11, r11, r7
5608	stm	r12!, {r10, r11}
5609	ldm	r12, {r10, r11}
5610	sbcs	r10, r10, r8
5611	sbc	r11, r11, r9
5612	stm	r12!, {r10, r11}
5613	sub	r12, r12, #36
5614	asr	lr, r11, #25
5615	# Conditionally subtract order starting at bit 125
5616	mov	r1, #0xa0000000
5617#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5618	mov	r2, #0x7d
5619	orr	r2, r2, #0x4b000000
5620	orr	r2, r2, #0x9e0000
5621	orr	r2, r2, #0xba00
5622#else
5623#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5624	mov	r2, #0x7d
5625	orr	r2, r2, #0xba00
5626#else
5627	mov	r2, #0xba7d
5628#endif
5629#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5630	orr	r2, r2, #0x4b000000
5631	orr	r2, r2, #0x9e0000
5632#else
5633	movt	r2, #0x4b9e
5634#endif
5635#endif
5636#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5637	mov	r3, #0x63
5638	orr	r3, r3, #0xcb000000
5639	orr	r3, r3, #0x20000
5640	orr	r3, r3, #0x4c00
5641#else
5642#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5643	mov	r3, #0x63
5644	orr	r3, r3, #0x4c00
5645#else
5646	mov	r3, #0x4c63
5647#endif
5648#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5649	orr	r3, r3, #0xcb000000
5650	orr	r3, r3, #0x20000
5651#else
5652	movt	r3, #0xcb02
5653#endif
5654#endif
5655#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5656	mov	r4, #0x9a
5657	orr	r4, r4, #0xd4000000
5658	orr	r4, r4, #0x5e0000
5659	orr	r4, r4, #0xf300
5660#else
5661#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5662	mov	r4, #0x9a
5663	orr	r4, r4, #0xf300
5664#else
5665	mov	r4, #0xf39a
5666#endif
5667#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5668	orr	r4, r4, #0xd4000000
5669	orr	r4, r4, #0x5e0000
5670#else
5671	movt	r4, #0xd45e
5672#endif
5673#endif
5674#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5675	mov	r5, #59
5676	orr	r5, r5, #0x2000000
5677	orr	r5, r5, #0x9b0000
5678	orr	r5, r5, #0xdf00
5679#else
5680#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5681	mov	r5, #0x3b
5682	orr	r5, r5, #0xdf00
5683#else
5684	mov	r5, #0xdf3b
5685#endif
5686#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5687	orr	r5, r5, #0x2000000
5688	orr	r5, r5, #0x9b0000
5689#else
5690	movt	r5, #0x29b
5691#endif
5692#endif
5693	mov	r9, #0x2000000
5694	and	r1, r1, lr
5695	and	r2, r2, lr
5696	and	r3, r3, lr
5697	and	r4, r4, lr
5698	and	r5, r5, lr
5699	and	r9, r9, lr
5700	ldm	r12, {r10, r11}
5701	adds	r10, r10, r1
5702	adcs	r11, r11, r2
5703	stm	r12!, {r10, r11}
5704	ldm	r12, {r10, r11}
5705	adcs	r10, r10, r3
5706	adcs	r11, r11, r4
5707	stm	r12!, {r10, r11}
5708	ldm	r12, {r10, r11}
5709	adcs	r10, r10, r5
5710	adcs	r11, r11, #0
5711	stm	r12!, {r10, r11}
5712	ldm	r12, {r10, r11}
5713	adcs	r10, r10, #0
5714	adcs	r11, r11, #0
5715	stm	r12!, {r10, r11}
5716	ldm	r12, {r10}
5717	adcs	r10, r10, #0
5718	stm	r12!, {r10}
5719	sub	r0, r0, #16
5720	mov	r12, sp
5721	# Load bits 252-376
5722	add	r12, r12, #28
5723	ldm	r12, {r1, r2, r3, r4, r5}
5724	lsl	r5, r5, #4
5725	orr	r5, r5, r4, lsr #28
5726	lsl	r4, r4, #4
5727	orr	r4, r4, r3, lsr #28
5728	lsl	r3, r3, #4
5729	orr	r3, r3, r2, lsr #28
5730	lsl	r2, r2, #4
5731	orr	r2, r2, r1, lsr #28
5732#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5733	bic	r5, r5, #0xe0000000
5734#else
5735	bfc	r5, #29, #3
5736#endif
5737	sub	r12, r12, #28
5738	# Sub product of top 4 words and order
5739	mov	r0, sp
5740	#   * -5cf5d3ed
5741#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5742	mov	r1, #19
5743	orr	r1, r1, #0xa3000000
5744	orr	r1, r1, #0xa0000
5745	orr	r1, r1, #0x2c00
5746#else
5747#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5748	mov	r1, #0x13
5749	orr	r1, r1, #0x2c00
5750#else
5751	mov	r1, #0x2c13
5752#endif
5753#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5754	orr	r1, r1, #0xa3000000
5755	orr	r1, r1, #0xa0000
5756#else
5757	movt	r1, #0xa30a
5758#endif
5759#endif
5760	mov	lr, #0
5761	ldm	r0, {r6, r7, r8, r9}
5762	umlal	r6, lr, r2, r1
5763	adds	r7, r7, lr
5764	mov	lr, #0
5765	adc	lr, lr, #0
5766	umlal	r7, lr, r3, r1
5767	adds	r8, r8, lr
5768	mov	lr, #0
5769	adc	lr, lr, #0
5770	umlal	r8, lr, r4, r1
5771	adds	r9, r9, lr
5772	mov	lr, #0
5773	adc	lr, lr, #0
5774	umlal	r9, lr, r5, r1
5775	stm	r0, {r6, r7, r8, r9}
5776	add	r0, r0, #4
5777	#   * -5812631b
5778#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5779	mov	r1, #0xe5
5780	orr	r1, r1, #0xa7000000
5781	orr	r1, r1, #0xed0000
5782	orr	r1, r1, #0x9c00
5783#else
5784#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5785	mov	r1, #0xe5
5786	orr	r1, r1, #0x9c00
5787#else
5788	mov	r1, #0x9ce5
5789#endif
5790#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5791	orr	r1, r1, #0xa7000000
5792	orr	r1, r1, #0xed0000
5793#else
5794	movt	r1, #0xa7ed
5795#endif
5796#endif
5797	mov	r10, #0
5798	ldm	r0, {r6, r7, r8, r9}
5799	umlal	r6, r10, r2, r1
5800	adds	r7, r7, r10
5801	mov	r10, #0
5802	adc	r10, r10, #0
5803	umlal	r7, r10, r3, r1
5804	adds	r8, r8, r10
5805	mov	r10, #0
5806	adc	r10, r10, #0
5807	umlal	r8, r10, r4, r1
5808	adds	r9, r9, r10
5809	mov	r10, #0
5810	adc	r10, r10, #0
5811	umlal	r9, r10, r5, r1
5812	stm	r0, {r6, r7, r8, r9}
5813	add	r0, r0, #4
5814	#   * -a2f79cd7
5815#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5816	mov	r1, #41
5817	orr	r1, r1, #0x5d000000
5818	orr	r1, r1, #0x80000
5819	orr	r1, r1, #0x6300
5820#else
5821#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5822	mov	r1, #0x29
5823	orr	r1, r1, #0x6300
5824#else
5825	mov	r1, #0x6329
5826#endif
5827#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5828	orr	r1, r1, #0x5d000000
5829	orr	r1, r1, #0x80000
5830#else
5831	movt	r1, #0x5d08
5832#endif
5833#endif
5834	mov	r11, #0
5835	ldm	r0, {r6, r7, r8, r9}
5836	umlal	r6, r11, r2, r1
5837	adds	r7, r7, r11
5838	mov	r11, #0
5839	adc	r11, r11, #0
5840	umlal	r7, r11, r3, r1
5841	adds	r8, r8, r11
5842	mov	r11, #0
5843	adc	r11, r11, #0
5844	umlal	r8, r11, r4, r1
5845	adds	r9, r9, r11
5846	mov	r11, #0
5847	adc	r11, r11, #0
5848	umlal	r9, r11, r5, r1
5849	stm	r0, {r6, r7, r8, r9}
5850	add	r0, r0, #4
5851	#   * -14def9df
5852#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5853	mov	r1, #33
5854	orr	r1, r1, #0xeb000000
5855	orr	r1, r1, #0x210000
5856	orr	r1, r1, #0x600
5857#else
5858#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5859	mov	r1, #0x21
5860	orr	r1, r1, #0x600
5861#else
5862	mov	r1, #0x621
5863#endif
5864#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5865	orr	r1, r1, #0xeb000000
5866	orr	r1, r1, #0x210000
5867#else
5868	movt	r1, #0xeb21
5869#endif
5870#endif
5871	mov	r12, #0
5872	ldm	r0, {r6, r7, r8, r9}
5873	umlal	r6, r12, r2, r1
5874	adds	r7, r7, r12
5875	mov	r12, #0
5876	adc	r12, r12, #0
5877	umlal	r7, r12, r3, r1
5878	adds	r8, r8, r12
5879	mov	r12, #0
5880	adc	r12, r12, #0
5881	umlal	r8, r12, r4, r1
5882	adds	r9, r9, r12
5883	mov	r12, #0
5884	adc	r12, r12, #0
5885	umlal	r9, r12, r5, r1
5886	stm	r0, {r6, r7, r8, r9}
5887	add	r0, r0, #4
5888	# Add overflows at 4 * 32
5889	ldm	r0, {r6, r7, r8, r9}
5890#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5891	bic	r9, r9, #0xf0000000
5892#else
5893	bfc	r9, #28, #4
5894#endif
5895	adds	r6, r6, lr
5896	adcs	r7, r7, r10
5897	adcs	r8, r8, r11
5898	adc	r9, r9, r12
5899	# Subtract top at 4 * 32
5900	subs	r6, r6, r2
5901	sbcs	r7, r7, r3
5902	sbcs	r8, r8, r4
5903	sbcs	r9, r9, r5
5904	sbc	r1, r1, r1
5905	sub	r0, r0, #16
5906	ldm	r0, {r2, r3, r4, r5}
5907#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5908	mov	r10, #0xed
5909	orr	r10, r10, #0x5c000000
5910	orr	r10, r10, #0xf50000
5911	orr	r10, r10, #0xd300
5912#else
5913#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5914	mov	r10, #0xed
5915	orr	r10, r10, #0xd300
5916#else
5917	mov	r10, #0xd3ed
5918#endif
5919#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5920	orr	r10, r10, #0x5c000000
5921	orr	r10, r10, #0xf50000
5922#else
5923	movt	r10, #0x5cf5
5924#endif
5925#endif
5926#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5927	mov	r11, #26
5928	orr	r11, r11, #0x58000000
5929	orr	r11, r11, #0x120000
5930	orr	r11, r11, #0x6300
5931#else
5932#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5933	mov	r11, #0x1a
5934	orr	r11, r11, #0x6300
5935#else
5936	mov	r11, #0x631a
5937#endif
5938#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5939	orr	r11, r11, #0x58000000
5940	orr	r11, r11, #0x120000
5941#else
5942	movt	r11, #0x5812
5943#endif
5944#endif
5945#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5946	mov	r12, #0xd6
5947	orr	r12, r12, #0xa2000000
5948	orr	r12, r12, #0xf70000
5949	orr	r12, r12, #0x9c00
5950#else
5951#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5952	mov	r12, #0xd6
5953	orr	r12, r12, #0x9c00
5954#else
5955	mov	r12, #0x9cd6
5956#endif
5957#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5958	orr	r12, r12, #0xa2000000
5959	orr	r12, r12, #0xf70000
5960#else
5961	movt	r12, #0xa2f7
5962#endif
5963#endif
5964#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5965	mov	lr, #0xde
5966	orr	lr, lr, #0x14000000
5967	orr	lr, lr, #0xde0000
5968	orr	lr, lr, #0xf900
5969#else
5970#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5971	mov	lr, #0xde
5972	orr	lr, lr, #0xf900
5973#else
5974	mov	lr, #0xf9de
5975#endif
5976#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5977	orr	lr, lr, #0x14000000
5978	orr	lr, lr, #0xde0000
5979#else
5980	movt	lr, #0x14de
5981#endif
5982#endif
5983	and	r10, r10, r1
5984	and	r11, r11, r1
5985	and	r12, r12, r1
5986	and	lr, lr, r1
5987	adds	r2, r2, r10
5988	adcs	r3, r3, r11
5989	adcs	r4, r4, r12
5990	adcs	r5, r5, lr
5991	adcs	r6, r6, #0
5992	adcs	r7, r7, #0
5993	and	r1, r1, #0x10000000
5994	adcs	r8, r8, #0
5995	adc	r9, r9, r1
5996#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
5997	bic	r9, r9, #0xf0000000
5998#else
5999	bfc	r9, #28, #4
6000#endif
6001	# Store result
6002	ldr	r0, [sp, #52]
6003	stm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
6004	add	sp, sp, #56
6005	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
6006	.size	sc_reduce,.-sc_reduce
6007#else
6008	.text
6009	.align	4
6010	.globl	sc_reduce
6011	.type	sc_reduce, %function
6012sc_reduce:
6013	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
6014	sub	sp, sp, #56
6015	str	r0, [sp, #52]
6016	# Load bits 252-511
6017	add	r0, r0, #28
6018	ldm	r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9}
6019	lsr	lr, r9, #24
6020	lsl	r9, r9, #4
6021	orr	r9, r9, r8, lsr #28
6022	lsl	r8, r8, #4
6023	orr	r8, r8, r7, lsr #28
6024	lsl	r7, r7, #4
6025	orr	r7, r7, r6, lsr #28
6026	lsl	r6, r6, #4
6027	orr	r6, r6, r5, lsr #28
6028	lsl	r5, r5, #4
6029	orr	r5, r5, r4, lsr #28
6030	lsl	r4, r4, #4
6031	orr	r4, r4, r3, lsr #28
6032	lsl	r3, r3, #4
6033	orr	r3, r3, r2, lsr #28
6034	lsl	r2, r2, #4
6035	orr	r2, r2, r1, lsr #28
6036#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6037	bic	r9, r9, #0xf0000000
6038#else
6039	bfc	r9, #28, #4
6040#endif
6041	sub	r0, r0, #28
6042	# Add order times bits 504..511
6043#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6044	mov	r10, #19
6045	orr	r10, r10, #0xa3000000
6046	orr	r10, r10, #0xa0000
6047	orr	r10, r10, #0x2c00
6048#else
6049#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6050	mov	r10, #0x13
6051	orr	r10, r10, #0x2c00
6052#else
6053	mov	r10, #0x2c13
6054#endif
6055#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6056	orr	r10, r10, #0xa3000000
6057	orr	r10, r10, #0xa0000
6058#else
6059	movt	r10, #0xa30a
6060#endif
6061#endif
6062#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6063	mov	r11, #0xe5
6064	orr	r11, r11, #0xa7000000
6065	orr	r11, r11, #0xed0000
6066	orr	r11, r11, #0x9c00
6067#else
6068#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6069	mov	r11, #0xe5
6070	orr	r11, r11, #0x9c00
6071#else
6072	mov	r11, #0x9ce5
6073#endif
6074#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6075	orr	r11, r11, #0xa7000000
6076	orr	r11, r11, #0xed0000
6077#else
6078	movt	r11, #0xa7ed
6079#endif
6080#endif
6081	mov	r1, #0
6082	umlal	r2, r1, r10, lr
6083	umaal	r3, r1, r11, lr
6084#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6085	mov	r10, #41
6086	orr	r10, r10, #0x5d000000
6087	orr	r10, r10, #0x80000
6088	orr	r10, r10, #0x6300
6089#else
6090#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6091	mov	r10, #0x29
6092	orr	r10, r10, #0x6300
6093#else
6094	mov	r10, #0x6329
6095#endif
6096#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6097	orr	r10, r10, #0x5d000000
6098	orr	r10, r10, #0x80000
6099#else
6100	movt	r10, #0x5d08
6101#endif
6102#endif
6103#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6104	mov	r11, #33
6105	orr	r11, r11, #0xeb000000
6106	orr	r11, r11, #0x210000
6107	orr	r11, r11, #0x600
6108#else
6109#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6110	mov	r11, #0x21
6111	orr	r11, r11, #0x600
6112#else
6113	mov	r11, #0x621
6114#endif
6115#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6116	orr	r11, r11, #0xeb000000
6117	orr	r11, r11, #0x210000
6118#else
6119	movt	r11, #0xeb21
6120#endif
6121#endif
6122	umaal	r4, r1, r10, lr
6123	umaal	r5, r1, r11, lr
6124	adds	r6, r6, r1
6125	adcs	r7, r7, #0
6126	adcs	r8, r8, #0
6127	adc	r9, r9, #0
6128	subs	r6, r6, lr
6129	sbcs	r7, r7, #0
6130	sbcs	r8, r8, #0
6131	sbc	r9, r9, #0
6132	# Sub product of top 8 words and order
6133	mov	r12, sp
6134#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6135	mov	r1, #19
6136	orr	r1, r1, #0xa3000000
6137	orr	r1, r1, #0xa0000
6138	orr	r1, r1, #0x2c00
6139#else
6140#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6141	mov	r1, #0x13
6142	orr	r1, r1, #0x2c00
6143#else
6144	mov	r1, #0x2c13
6145#endif
6146#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6147	orr	r1, r1, #0xa3000000
6148	orr	r1, r1, #0xa0000
6149#else
6150	movt	r1, #0xa30a
6151#endif
6152#endif
6153	mov	lr, #0
6154	ldm	r0!, {r10, r11}
6155	umlal	r10, lr, r2, r1
6156	umaal	r11, lr, r3, r1
6157	stm	r12!, {r10, r11}
6158	ldm	r0!, {r10, r11}
6159	umaal	r10, lr, r4, r1
6160	umaal	r11, lr, r5, r1
6161	stm	r12!, {r10, r11}
6162	ldm	r0!, {r10, r11}
6163	umaal	r10, lr, r6, r1
6164	umaal	r11, lr, r7, r1
6165	stm	r12!, {r10, r11}
6166	ldm	r0!, {r10, r11}
6167	umaal	r10, lr, r8, r1
6168#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6169	bic	r11, r11, #0xf0000000
6170#else
6171	bfc	r11, #28, #4
6172#endif
6173	umaal	r11, lr, r9, r1
6174	stm	r12!, {r10, r11, lr}
6175	sub	r0, r0, #16
6176	sub	r12, r12, #32
6177#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6178	mov	r1, #0xe5
6179	orr	r1, r1, #0xa7000000
6180	orr	r1, r1, #0xed0000
6181	orr	r1, r1, #0x9c00
6182#else
6183#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6184	mov	r1, #0xe5
6185	orr	r1, r1, #0x9c00
6186#else
6187	mov	r1, #0x9ce5
6188#endif
6189#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6190	orr	r1, r1, #0xa7000000
6191	orr	r1, r1, #0xed0000
6192#else
6193	movt	r1, #0xa7ed
6194#endif
6195#endif
6196	mov	lr, #0
6197	ldm	r12, {r10, r11}
6198	umlal	r10, lr, r2, r1
6199	umaal	r11, lr, r3, r1
6200	stm	r12!, {r10, r11}
6201	ldm	r12, {r10, r11}
6202	umaal	r10, lr, r4, r1
6203	umaal	r11, lr, r5, r1
6204	stm	r12!, {r10, r11}
6205	ldm	r12, {r10, r11}
6206	umaal	r10, lr, r6, r1
6207	umaal	r11, lr, r7, r1
6208	stm	r12!, {r10, r11}
6209	ldm	r12, {r10, r11}
6210	umaal	r10, lr, r8, r1
6211	umaal	r11, lr, r9, r1
6212	stm	r12!, {r10, r11, lr}
6213	sub	r12, r12, #32
6214#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6215	mov	r1, #41
6216	orr	r1, r1, #0x5d000000
6217	orr	r1, r1, #0x80000
6218	orr	r1, r1, #0x6300
6219#else
6220#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6221	mov	r1, #0x29
6222	orr	r1, r1, #0x6300
6223#else
6224	mov	r1, #0x6329
6225#endif
6226#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6227	orr	r1, r1, #0x5d000000
6228	orr	r1, r1, #0x80000
6229#else
6230	movt	r1, #0x5d08
6231#endif
6232#endif
6233	mov	lr, #0
6234	ldm	r12, {r10, r11}
6235	umlal	r10, lr, r2, r1
6236	umaal	r11, lr, r3, r1
6237	stm	r12!, {r10, r11}
6238	ldm	r12, {r10, r11}
6239	umaal	r10, lr, r4, r1
6240	umaal	r11, lr, r5, r1
6241	stm	r12!, {r10, r11}
6242	ldm	r12, {r10, r11}
6243	umaal	r10, lr, r6, r1
6244	umaal	r11, lr, r7, r1
6245	stm	r12!, {r10, r11}
6246	ldm	r12, {r10, r11}
6247	umaal	r10, lr, r8, r1
6248	umaal	r11, lr, r9, r1
6249	stm	r12!, {r10, r11, lr}
6250	sub	r12, r12, #32
6251#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6252	mov	r1, #33
6253	orr	r1, r1, #0xeb000000
6254	orr	r1, r1, #0x210000
6255	orr	r1, r1, #0x600
6256#else
6257#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6258	mov	r1, #0x21
6259	orr	r1, r1, #0x600
6260#else
6261	mov	r1, #0x621
6262#endif
6263#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6264	orr	r1, r1, #0xeb000000
6265	orr	r1, r1, #0x210000
6266#else
6267	movt	r1, #0xeb21
6268#endif
6269#endif
6270	mov	lr, #0
6271	ldm	r12, {r10, r11}
6272	umlal	r10, lr, r2, r1
6273	umaal	r11, lr, r3, r1
6274	stm	r12!, {r10, r11}
6275	ldm	r12, {r10, r11}
6276	umaal	r10, lr, r4, r1
6277	umaal	r11, lr, r5, r1
6278	stm	r12!, {r10, r11}
6279	ldm	r12, {r10, r11}
6280	umaal	r10, lr, r6, r1
6281	umaal	r11, lr, r7, r1
6282	stm	r12!, {r10, r11}
6283	ldm	r12, {r10, r11}
6284	umaal	r10, lr, r8, r1
6285	umaal	r11, lr, r9, r1
6286	stm	r12!, {r10, r11, lr}
6287	sub	r12, r12, #32
6288	# Subtract at 4 * 32
6289	ldm	r12, {r10, r11}
6290	subs	r10, r10, r2
6291	sbcs	r11, r11, r3
6292	stm	r12!, {r10, r11}
6293	ldm	r12, {r10, r11}
6294	sbcs	r10, r10, r4
6295	sbcs	r11, r11, r5
6296	stm	r12!, {r10, r11}
6297	ldm	r12, {r10, r11}
6298	sbcs	r10, r10, r6
6299	sbcs	r11, r11, r7
6300	stm	r12!, {r10, r11}
6301	ldm	r12, {r10, r11}
6302	sbcs	r10, r10, r8
6303	sbc	r11, r11, r9
6304	stm	r12!, {r10, r11}
6305	sub	r12, r12, #36
6306	asr	lr, r11, #25
6307	# Conditionally subtract order starting at bit 125
6308	mov	r1, #0xa0000000
6309#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6310	mov	r2, #0x7d
6311	orr	r2, r2, #0x4b000000
6312	orr	r2, r2, #0x9e0000
6313	orr	r2, r2, #0xba00
6314#else
6315#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6316	mov	r2, #0x7d
6317	orr	r2, r2, #0xba00
6318#else
6319	mov	r2, #0xba7d
6320#endif
6321#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6322	orr	r2, r2, #0x4b000000
6323	orr	r2, r2, #0x9e0000
6324#else
6325	movt	r2, #0x4b9e
6326#endif
6327#endif
6328#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6329	mov	r3, #0x63
6330	orr	r3, r3, #0xcb000000
6331	orr	r3, r3, #0x20000
6332	orr	r3, r3, #0x4c00
6333#else
6334#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6335	mov	r3, #0x63
6336	orr	r3, r3, #0x4c00
6337#else
6338	mov	r3, #0x4c63
6339#endif
6340#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6341	orr	r3, r3, #0xcb000000
6342	orr	r3, r3, #0x20000
6343#else
6344	movt	r3, #0xcb02
6345#endif
6346#endif
6347#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6348	mov	r4, #0x9a
6349	orr	r4, r4, #0xd4000000
6350	orr	r4, r4, #0x5e0000
6351	orr	r4, r4, #0xf300
6352#else
6353#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6354	mov	r4, #0x9a
6355	orr	r4, r4, #0xf300
6356#else
6357	mov	r4, #0xf39a
6358#endif
6359#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6360	orr	r4, r4, #0xd4000000
6361	orr	r4, r4, #0x5e0000
6362#else
6363	movt	r4, #0xd45e
6364#endif
6365#endif
6366#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6367	mov	r5, #59
6368	orr	r5, r5, #0x2000000
6369	orr	r5, r5, #0x9b0000
6370	orr	r5, r5, #0xdf00
6371#else
6372#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6373	mov	r5, #0x3b
6374	orr	r5, r5, #0xdf00
6375#else
6376	mov	r5, #0xdf3b
6377#endif
6378#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6379	orr	r5, r5, #0x2000000
6380	orr	r5, r5, #0x9b0000
6381#else
6382	movt	r5, #0x29b
6383#endif
6384#endif
6385	mov	r9, #0x2000000
6386	and	r1, r1, lr
6387	and	r2, r2, lr
6388	and	r3, r3, lr
6389	and	r4, r4, lr
6390	and	r5, r5, lr
6391	and	r9, r9, lr
6392	ldm	r12, {r10, r11}
6393	adds	r10, r10, r1
6394	adcs	r11, r11, r2
6395	stm	r12!, {r10, r11}
6396	ldm	r12, {r10, r11}
6397	adcs	r10, r10, r3
6398	adcs	r11, r11, r4
6399	stm	r12!, {r10, r11}
6400	ldm	r12, {r10, r11}
6401	adcs	r10, r10, r5
6402	adcs	r11, r11, #0
6403	stm	r12!, {r10, r11}
6404	ldm	r12, {r10, r11}
6405	adcs	r10, r10, #0
6406	adcs	r11, r11, #0
6407	stm	r12!, {r10, r11}
6408	ldm	r12, {r10}
6409	adcs	r10, r10, #0
6410	stm	r12!, {r10}
6411	sub	r0, r0, #16
6412	mov	r12, sp
6413	# Load bits 252-376
6414	add	r12, r12, #28
6415	ldm	r12, {r1, r2, r3, r4, r5}
6416	lsl	r5, r5, #4
6417	orr	r5, r5, r4, lsr #28
6418	lsl	r4, r4, #4
6419	orr	r4, r4, r3, lsr #28
6420	lsl	r3, r3, #4
6421	orr	r3, r3, r2, lsr #28
6422	lsl	r2, r2, #4
6423	orr	r2, r2, r1, lsr #28
6424#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6425	bic	r5, r5, #0xe0000000
6426#else
6427	bfc	r5, #29, #3
6428#endif
6429	sub	r12, r12, #28
6430	# Sub product of top 4 words and order
6431	mov	r0, sp
6432	#   * -5cf5d3ed
6433#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6434	mov	r1, #19
6435	orr	r1, r1, #0xa3000000
6436	orr	r1, r1, #0xa0000
6437	orr	r1, r1, #0x2c00
6438#else
6439#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6440	mov	r1, #0x13
6441	orr	r1, r1, #0x2c00
6442#else
6443	mov	r1, #0x2c13
6444#endif
6445#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6446	orr	r1, r1, #0xa3000000
6447	orr	r1, r1, #0xa0000
6448#else
6449	movt	r1, #0xa30a
6450#endif
6451#endif
6452	mov	lr, #0
6453	ldm	r0, {r6, r7, r8, r9}
6454	umlal	r6, lr, r2, r1
6455	umaal	r7, lr, r3, r1
6456	umaal	r8, lr, r4, r1
6457	umaal	r9, lr, r5, r1
6458	stm	r0, {r6, r7, r8, r9}
6459	add	r0, r0, #4
6460	#   * -5812631b
6461#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6462	mov	r1, #0xe5
6463	orr	r1, r1, #0xa7000000
6464	orr	r1, r1, #0xed0000
6465	orr	r1, r1, #0x9c00
6466#else
6467#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6468	mov	r1, #0xe5
6469	orr	r1, r1, #0x9c00
6470#else
6471	mov	r1, #0x9ce5
6472#endif
6473#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6474	orr	r1, r1, #0xa7000000
6475	orr	r1, r1, #0xed0000
6476#else
6477	movt	r1, #0xa7ed
6478#endif
6479#endif
6480	mov	r10, #0
6481	ldm	r0, {r6, r7, r8, r9}
6482	umlal	r6, r10, r2, r1
6483	umaal	r7, r10, r3, r1
6484	umaal	r8, r10, r4, r1
6485	umaal	r9, r10, r5, r1
6486	stm	r0, {r6, r7, r8, r9}
6487	add	r0, r0, #4
6488	#   * -a2f79cd7
6489#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6490	mov	r1, #41
6491	orr	r1, r1, #0x5d000000
6492	orr	r1, r1, #0x80000
6493	orr	r1, r1, #0x6300
6494#else
6495#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6496	mov	r1, #0x29
6497	orr	r1, r1, #0x6300
6498#else
6499	mov	r1, #0x6329
6500#endif
6501#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6502	orr	r1, r1, #0x5d000000
6503	orr	r1, r1, #0x80000
6504#else
6505	movt	r1, #0x5d08
6506#endif
6507#endif
6508	mov	r11, #0
6509	ldm	r0, {r6, r7, r8, r9}
6510	umlal	r6, r11, r2, r1
6511	umaal	r7, r11, r3, r1
6512	umaal	r8, r11, r4, r1
6513	umaal	r9, r11, r5, r1
6514	stm	r0, {r6, r7, r8, r9}
6515	add	r0, r0, #4
6516	#   * -14def9df
6517#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6518	mov	r1, #33
6519	orr	r1, r1, #0xeb000000
6520	orr	r1, r1, #0x210000
6521	orr	r1, r1, #0x600
6522#else
6523#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6524	mov	r1, #0x21
6525	orr	r1, r1, #0x600
6526#else
6527	mov	r1, #0x621
6528#endif
6529#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6530	orr	r1, r1, #0xeb000000
6531	orr	r1, r1, #0x210000
6532#else
6533	movt	r1, #0xeb21
6534#endif
6535#endif
6536	mov	r12, #0
6537	ldm	r0, {r6, r7, r8, r9}
6538	umlal	r6, r12, r2, r1
6539	umaal	r7, r12, r3, r1
6540	umaal	r8, r12, r4, r1
6541	umaal	r9, r12, r5, r1
6542	stm	r0, {r6, r7, r8, r9}
6543	add	r0, r0, #4
6544	# Add overflows at 4 * 32
6545	ldm	r0, {r6, r7, r8, r9}
6546#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6547	bic	r9, r9, #0xf0000000
6548#else
6549	bfc	r9, #28, #4
6550#endif
6551	adds	r6, r6, lr
6552	adcs	r7, r7, r10
6553	adcs	r8, r8, r11
6554	adc	r9, r9, r12
6555	# Subtract top at 4 * 32
6556	subs	r6, r6, r2
6557	sbcs	r7, r7, r3
6558	sbcs	r8, r8, r4
6559	sbcs	r9, r9, r5
6560	sbc	r1, r1, r1
6561	sub	r0, r0, #16
6562	ldm	r0, {r2, r3, r4, r5}
6563#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6564	mov	r10, #0xed
6565	orr	r10, r10, #0x5c000000
6566	orr	r10, r10, #0xf50000
6567	orr	r10, r10, #0xd300
6568#else
6569#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6570	mov	r10, #0xed
6571	orr	r10, r10, #0xd300
6572#else
6573	mov	r10, #0xd3ed
6574#endif
6575#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6576	orr	r10, r10, #0x5c000000
6577	orr	r10, r10, #0xf50000
6578#else
6579	movt	r10, #0x5cf5
6580#endif
6581#endif
6582#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6583	mov	r11, #26
6584	orr	r11, r11, #0x58000000
6585	orr	r11, r11, #0x120000
6586	orr	r11, r11, #0x6300
6587#else
6588#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6589	mov	r11, #0x1a
6590	orr	r11, r11, #0x6300
6591#else
6592	mov	r11, #0x631a
6593#endif
6594#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6595	orr	r11, r11, #0x58000000
6596	orr	r11, r11, #0x120000
6597#else
6598	movt	r11, #0x5812
6599#endif
6600#endif
6601#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6602	mov	r12, #0xd6
6603	orr	r12, r12, #0xa2000000
6604	orr	r12, r12, #0xf70000
6605	orr	r12, r12, #0x9c00
6606#else
6607#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6608	mov	r12, #0xd6
6609	orr	r12, r12, #0x9c00
6610#else
6611	mov	r12, #0x9cd6
6612#endif
6613#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6614	orr	r12, r12, #0xa2000000
6615	orr	r12, r12, #0xf70000
6616#else
6617	movt	r12, #0xa2f7
6618#endif
6619#endif
6620#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6621	mov	lr, #0xde
6622	orr	lr, lr, #0x14000000
6623	orr	lr, lr, #0xde0000
6624	orr	lr, lr, #0xf900
6625#else
6626#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6627	mov	lr, #0xde
6628	orr	lr, lr, #0xf900
6629#else
6630	mov	lr, #0xf9de
6631#endif
6632#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6633	orr	lr, lr, #0x14000000
6634	orr	lr, lr, #0xde0000
6635#else
6636	movt	lr, #0x14de
6637#endif
6638#endif
6639	and	r10, r10, r1
6640	and	r11, r11, r1
6641	and	r12, r12, r1
6642	and	lr, lr, r1
6643	adds	r2, r2, r10
6644	adcs	r3, r3, r11
6645	adcs	r4, r4, r12
6646	adcs	r5, r5, lr
6647	adcs	r6, r6, #0
6648	adcs	r7, r7, #0
6649	and	r1, r1, #0x10000000
6650	adcs	r8, r8, #0
6651	adc	r9, r9, r1
6652#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
6653	bic	r9, r9, #0xf0000000
6654#else
6655	bfc	r9, #28, #4
6656#endif
6657	# Store result
6658	ldr	r0, [sp, #52]
6659	stm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
6660	add	sp, sp, #56
6661	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
6662	.size	sc_reduce,.-sc_reduce
6663#endif /* WOLFSSL_ARM_ARCH && WOLFSSL_ARM_ARCH < 6 */
6664#ifdef HAVE_ED25519_SIGN
6665#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 6)
6666	.text
6667	.align	4
6668	.globl	sc_muladd
6669	.type	sc_muladd, %function
6670sc_muladd:
6671	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
6672	sub	sp, sp, #0x50
6673	add	lr, sp, #0x44
6674	stm	lr, {r0, r1, r3}
6675	mov	r0, #0
6676	ldr	r12, [r1]
6677	# A[0] * B[0]
6678	ldr	lr, [r2]
6679	umull	r3, r4, r12, lr
6680	# A[0] * B[2]
6681	ldr	lr, [r2, #8]
6682	umull	r5, r6, r12, lr
6683	# A[0] * B[4]
6684	ldr	lr, [r2, #16]
6685	umull	r7, r8, r12, lr
6686	# A[0] * B[6]
6687	ldr	lr, [r2, #24]
6688	umull	r9, r10, r12, lr
6689	str	r3, [sp]
6690	# A[0] * B[1]
6691	ldr	lr, [r2, #4]
6692	mov	r11, r0
6693	umlal	r4, r11, r12, lr
6694	adds	r5, r5, r11
6695	# A[0] * B[3]
6696	ldr	lr, [r2, #12]
6697	adcs	r6, r6, #0
6698	adc	r11, r0, #0
6699	umlal	r6, r11, r12, lr
6700	adds	r7, r7, r11
6701	# A[0] * B[5]
6702	ldr	lr, [r2, #20]
6703	adcs	r8, r8, #0
6704	adc	r11, r0, #0
6705	umlal	r8, r11, r12, lr
6706	adds	r9, r9, r11
6707	# A[0] * B[7]
6708	ldr	lr, [r2, #28]
6709	adcs	r10, r10, #0
6710	adc	r3, r0, #0
6711	umlal	r10, r3, r12, lr
6712	# A[1] * B[0]
6713	ldr	r12, [r1, #4]
6714	ldr	lr, [r2]
6715	mov	r11, #0
6716	umlal	r4, r11, r12, lr
6717	str	r4, [sp, #4]
6718	adds	r5, r5, r11
6719	# A[1] * B[1]
6720	ldr	lr, [r2, #4]
6721	adc	r11, r0, #0
6722	umlal	r5, r11, r12, lr
6723	adds	r6, r6, r11
6724	# A[1] * B[2]
6725	ldr	lr, [r2, #8]
6726	adc	r11, r0, #0
6727	umlal	r6, r11, r12, lr
6728	adds	r7, r7, r11
6729	# A[1] * B[3]
6730	ldr	lr, [r2, #12]
6731	adc	r11, r0, #0
6732	umlal	r7, r11, r12, lr
6733	adds	r8, r8, r11
6734	# A[1] * B[4]
6735	ldr	lr, [r2, #16]
6736	adc	r11, r0, #0
6737	umlal	r8, r11, r12, lr
6738	adds	r9, r9, r11
6739	# A[1] * B[5]
6740	ldr	lr, [r2, #20]
6741	adc	r11, r0, #0
6742	umlal	r9, r11, r12, lr
6743	adds	r10, r10, r11
6744	# A[1] * B[6]
6745	ldr	lr, [r2, #24]
6746	adc	r11, r0, #0
6747	umlal	r10, r11, r12, lr
6748	adds	r3, r3, r11
6749	# A[1] * B[7]
6750	ldr	lr, [r2, #28]
6751	adc	r4, r0, #0
6752	umlal	r3, r4, r12, lr
6753	# A[2] * B[0]
6754	ldr	r12, [r1, #8]
6755	ldr	lr, [r2]
6756	mov	r11, #0
6757	umlal	r5, r11, r12, lr
6758	str	r5, [sp, #8]
6759	adds	r6, r6, r11
6760	# A[2] * B[1]
6761	ldr	lr, [r2, #4]
6762	adc	r11, r0, #0
6763	umlal	r6, r11, r12, lr
6764	adds	r7, r7, r11
6765	# A[2] * B[2]
6766	ldr	lr, [r2, #8]
6767	adc	r11, r0, #0
6768	umlal	r7, r11, r12, lr
6769	adds	r8, r8, r11
6770	# A[2] * B[3]
6771	ldr	lr, [r2, #12]
6772	adc	r11, r0, #0
6773	umlal	r8, r11, r12, lr
6774	adds	r9, r9, r11
6775	# A[2] * B[4]
6776	ldr	lr, [r2, #16]
6777	adc	r11, r0, #0
6778	umlal	r9, r11, r12, lr
6779	adds	r10, r10, r11
6780	# A[2] * B[5]
6781	ldr	lr, [r2, #20]
6782	adc	r11, r0, #0
6783	umlal	r10, r11, r12, lr
6784	adds	r3, r3, r11
6785	# A[2] * B[6]
6786	ldr	lr, [r2, #24]
6787	adc	r11, r0, #0
6788	umlal	r3, r11, r12, lr
6789	adds	r4, r4, r11
6790	# A[2] * B[7]
6791	ldr	lr, [r2, #28]
6792	adc	r5, r0, #0
6793	umlal	r4, r5, r12, lr
6794	# A[3] * B[0]
6795	ldr	r12, [r1, #12]
6796	ldr	lr, [r2]
6797	mov	r11, #0
6798	umlal	r6, r11, r12, lr
6799	str	r6, [sp, #12]
6800	adds	r7, r7, r11
6801	# A[3] * B[1]
6802	ldr	lr, [r2, #4]
6803	adc	r11, r0, #0
6804	umlal	r7, r11, r12, lr
6805	adds	r8, r8, r11
6806	# A[3] * B[2]
6807	ldr	lr, [r2, #8]
6808	adc	r11, r0, #0
6809	umlal	r8, r11, r12, lr
6810	adds	r9, r9, r11
6811	# A[3] * B[3]
6812	ldr	lr, [r2, #12]
6813	adc	r11, r0, #0
6814	umlal	r9, r11, r12, lr
6815	adds	r10, r10, r11
6816	# A[3] * B[4]
6817	ldr	lr, [r2, #16]
6818	adc	r11, r0, #0
6819	umlal	r10, r11, r12, lr
6820	adds	r3, r3, r11
6821	# A[3] * B[5]
6822	ldr	lr, [r2, #20]
6823	adc	r11, r0, #0
6824	umlal	r3, r11, r12, lr
6825	adds	r4, r4, r11
6826	# A[3] * B[6]
6827	ldr	lr, [r2, #24]
6828	adc	r11, r0, #0
6829	umlal	r4, r11, r12, lr
6830	adds	r5, r5, r11
6831	# A[3] * B[7]
6832	ldr	lr, [r2, #28]
6833	adc	r6, r0, #0
6834	umlal	r5, r6, r12, lr
6835	# A[4] * B[0]
6836	ldr	r12, [r1, #16]
6837	ldr	lr, [r2]
6838	mov	r11, #0
6839	umlal	r7, r11, r12, lr
6840	str	r7, [sp, #16]
6841	adds	r8, r8, r11
6842	# A[4] * B[1]
6843	ldr	lr, [r2, #4]
6844	adc	r11, r0, #0
6845	umlal	r8, r11, r12, lr
6846	adds	r9, r9, r11
6847	# A[4] * B[2]
6848	ldr	lr, [r2, #8]
6849	adc	r11, r0, #0
6850	umlal	r9, r11, r12, lr
6851	adds	r10, r10, r11
6852	# A[4] * B[3]
6853	ldr	lr, [r2, #12]
6854	adc	r11, r0, #0
6855	umlal	r10, r11, r12, lr
6856	adds	r3, r3, r11
6857	# A[4] * B[4]
6858	ldr	lr, [r2, #16]
6859	adc	r11, r0, #0
6860	umlal	r3, r11, r12, lr
6861	adds	r4, r4, r11
6862	# A[4] * B[5]
6863	ldr	lr, [r2, #20]
6864	adc	r11, r0, #0
6865	umlal	r4, r11, r12, lr
6866	adds	r5, r5, r11
6867	# A[4] * B[6]
6868	ldr	lr, [r2, #24]
6869	adc	r11, r0, #0
6870	umlal	r5, r11, r12, lr
6871	adds	r6, r6, r11
6872	# A[4] * B[7]
6873	ldr	lr, [r2, #28]
6874	adc	r7, r0, #0
6875	umlal	r6, r7, r12, lr
6876	# A[5] * B[0]
6877	ldr	r12, [r1, #20]
6878	ldr	lr, [r2]
6879	mov	r11, #0
6880	umlal	r8, r11, r12, lr
6881	str	r8, [sp, #20]
6882	adds	r9, r9, r11
6883	# A[5] * B[1]
6884	ldr	lr, [r2, #4]
6885	adc	r11, r0, #0
6886	umlal	r9, r11, r12, lr
6887	adds	r10, r10, r11
6888	# A[5] * B[2]
6889	ldr	lr, [r2, #8]
6890	adc	r11, r0, #0
6891	umlal	r10, r11, r12, lr
6892	adds	r3, r3, r11
6893	# A[5] * B[3]
6894	ldr	lr, [r2, #12]
6895	adc	r11, r0, #0
6896	umlal	r3, r11, r12, lr
6897	adds	r4, r4, r11
6898	# A[5] * B[4]
6899	ldr	lr, [r2, #16]
6900	adc	r11, r0, #0
6901	umlal	r4, r11, r12, lr
6902	adds	r5, r5, r11
6903	# A[5] * B[5]
6904	ldr	lr, [r2, #20]
6905	adc	r11, r0, #0
6906	umlal	r5, r11, r12, lr
6907	adds	r6, r6, r11
6908	# A[5] * B[6]
6909	ldr	lr, [r2, #24]
6910	adc	r11, r0, #0
6911	umlal	r6, r11, r12, lr
6912	adds	r7, r7, r11
6913	# A[5] * B[7]
6914	ldr	lr, [r2, #28]
6915	adc	r8, r0, #0
6916	umlal	r7, r8, r12, lr
6917	# A[6] * B[0]
6918	ldr	r12, [r1, #24]
6919	ldr	lr, [r2]
6920	mov	r11, #0
6921	umlal	r9, r11, r12, lr
6922	str	r9, [sp, #24]
6923	adds	r10, r10, r11
6924	# A[6] * B[1]
6925	ldr	lr, [r2, #4]
6926	adc	r11, r0, #0
6927	umlal	r10, r11, r12, lr
6928	adds	r3, r3, r11
6929	# A[6] * B[2]
6930	ldr	lr, [r2, #8]
6931	adc	r11, r0, #0
6932	umlal	r3, r11, r12, lr
6933	adds	r4, r4, r11
6934	# A[6] * B[3]
6935	ldr	lr, [r2, #12]
6936	adc	r11, r0, #0
6937	umlal	r4, r11, r12, lr
6938	adds	r5, r5, r11
6939	# A[6] * B[4]
6940	ldr	lr, [r2, #16]
6941	adc	r11, r0, #0
6942	umlal	r5, r11, r12, lr
6943	adds	r6, r6, r11
6944	# A[6] * B[5]
6945	ldr	lr, [r2, #20]
6946	adc	r11, r0, #0
6947	umlal	r6, r11, r12, lr
6948	adds	r7, r7, r11
6949	# A[6] * B[6]
6950	ldr	lr, [r2, #24]
6951	adc	r11, r0, #0
6952	umlal	r7, r11, r12, lr
6953	adds	r8, r8, r11
6954	# A[6] * B[7]
6955	ldr	lr, [r2, #28]
6956	adc	r9, r0, #0
6957	umlal	r8, r9, r12, lr
6958	# A[7] * B[0]
6959	ldr	r12, [r1, #28]
6960	ldr	lr, [r2]
6961	mov	r11, #0
6962	umlal	r10, r11, r12, lr
6963	str	r10, [sp, #28]
6964	adds	r3, r3, r11
6965	# A[7] * B[1]
6966	ldr	lr, [r2, #4]
6967	adc	r11, r0, #0
6968	umlal	r3, r11, r12, lr
6969	adds	r4, r4, r11
6970	# A[7] * B[2]
6971	ldr	lr, [r2, #8]
6972	adc	r11, r0, #0
6973	umlal	r4, r11, r12, lr
6974	adds	r5, r5, r11
6975	# A[7] * B[3]
6976	ldr	lr, [r2, #12]
6977	adc	r11, r0, #0
6978	umlal	r5, r11, r12, lr
6979	adds	r6, r6, r11
6980	# A[7] * B[4]
6981	ldr	lr, [r2, #16]
6982	adc	r11, r0, #0
6983	umlal	r6, r11, r12, lr
6984	adds	r7, r7, r11
6985	# A[7] * B[5]
6986	ldr	lr, [r2, #20]
6987	adc	r11, r0, #0
6988	umlal	r7, r11, r12, lr
6989	adds	r8, r8, r11
6990	# A[7] * B[6]
6991	ldr	lr, [r2, #24]
6992	adc	r11, r0, #0
6993	umlal	r8, r11, r12, lr
6994	adds	r9, r9, r11
6995	# A[7] * B[7]
6996	ldr	lr, [r2, #28]
6997	adc	r10, r0, #0
6998	umlal	r9, r10, r12, lr
6999	add	lr, sp, #32
7000	stm	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
7001	mov	r0, sp
7002	# Add c to a * b
7003	ldr	lr, [sp, #76]
7004	ldm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
7005	ldm	lr!, {r1, r10, r11, r12}
7006	adds	r2, r2, r1
7007	adcs	r3, r3, r10
7008	adcs	r4, r4, r11
7009	adcs	r5, r5, r12
7010	ldm	lr!, {r1, r10, r11, r12}
7011	adcs	r6, r6, r1
7012	adcs	r7, r7, r10
7013	adcs	r8, r8, r11
7014	adcs	r9, r9, r12
7015	mov	r1, r9
7016	stm	r0!, {r2, r3, r4, r5, r6, r7, r8, r9}
7017	ldm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
7018	adcs	r2, r2, #0
7019	adcs	r3, r3, #0
7020	adcs	r4, r4, #0
7021	adcs	r5, r5, #0
7022	adcs	r6, r6, #0
7023	adcs	r7, r7, #0
7024	adcs	r8, r8, #0
7025	adc	r9, r9, #0
7026	sub	r0, r0, #32
7027	# Get 252..503 and 504..507
7028	lsr	lr, r9, #24
7029	lsl	r9, r9, #4
7030	orr	r9, r9, r8, lsr #28
7031	lsl	r8, r8, #4
7032	orr	r8, r8, r7, lsr #28
7033	lsl	r7, r7, #4
7034	orr	r7, r7, r6, lsr #28
7035	lsl	r6, r6, #4
7036	orr	r6, r6, r5, lsr #28
7037	lsl	r5, r5, #4
7038	orr	r5, r5, r4, lsr #28
7039	lsl	r4, r4, #4
7040	orr	r4, r4, r3, lsr #28
7041	lsl	r3, r3, #4
7042	orr	r3, r3, r2, lsr #28
7043	lsl	r2, r2, #4
7044	orr	r2, r2, r1, lsr #28
7045#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7046	bic	r9, r9, #0xf0000000
7047#else
7048	bfc	r9, #28, #4
7049#endif
7050	# Add order times bits 504..507
7051#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7052	mov	r10, #19
7053	orr	r10, r10, #0xa3000000
7054	orr	r10, r10, #0xa0000
7055	orr	r10, r10, #0x2c00
7056#else
7057#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7058	mov	r10, #0x13
7059	orr	r10, r10, #0x2c00
7060#else
7061	mov	r10, #0x2c13
7062#endif
7063#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7064	orr	r10, r10, #0xa3000000
7065	orr	r10, r10, #0xa0000
7066#else
7067	movt	r10, #0xa30a
7068#endif
7069#endif
7070#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7071	mov	r11, #0xe5
7072	orr	r11, r11, #0xa7000000
7073	orr	r11, r11, #0xed0000
7074	orr	r11, r11, #0x9c00
7075#else
7076#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7077	mov	r11, #0xe5
7078	orr	r11, r11, #0x9c00
7079#else
7080	mov	r11, #0x9ce5
7081#endif
7082#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7083	orr	r11, r11, #0xa7000000
7084	orr	r11, r11, #0xed0000
7085#else
7086	movt	r11, #0xa7ed
7087#endif
7088#endif
7089	mov	r1, #0
7090	umlal	r2, r1, r10, lr
7091	adds	r3, r3, r1
7092	mov	r1, #0
7093	adc	r1, r1, #0
7094	umlal	r3, r1, r11, lr
7095#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7096	mov	r10, #41
7097	orr	r10, r10, #0x5d000000
7098	orr	r10, r10, #0x80000
7099	orr	r10, r10, #0x6300
7100#else
7101#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7102	mov	r10, #0x29
7103	orr	r10, r10, #0x6300
7104#else
7105	mov	r10, #0x6329
7106#endif
7107#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7108	orr	r10, r10, #0x5d000000
7109	orr	r10, r10, #0x80000
7110#else
7111	movt	r10, #0x5d08
7112#endif
7113#endif
7114#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7115	mov	r11, #33
7116	orr	r11, r11, #0xeb000000
7117	orr	r11, r11, #0x210000
7118	orr	r11, r11, #0x600
7119#else
7120#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7121	mov	r11, #0x21
7122	orr	r11, r11, #0x600
7123#else
7124	mov	r11, #0x621
7125#endif
7126#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7127	orr	r11, r11, #0xeb000000
7128	orr	r11, r11, #0x210000
7129#else
7130	movt	r11, #0xeb21
7131#endif
7132#endif
7133	adds	r4, r4, r1
7134	mov	r1, #0
7135	adc	r1, r1, #0
7136	umlal	r4, r1, r10, lr
7137	adds	r5, r5, r1
7138	mov	r1, #0
7139	adc	r1, r1, #0
7140	umlal	r5, r1, r11, lr
7141	adds	r6, r6, r1
7142	adcs	r7, r7, #0
7143	adcs	r8, r8, #0
7144	adc	r9, r9, #0
7145	subs	r6, r6, lr
7146	sbcs	r7, r7, #0
7147	sbcs	r8, r8, #0
7148	sbc	r9, r9, #0
7149	# Sub product of top 8 words and order
7150	mov	r12, sp
7151#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7152	mov	r1, #19
7153	orr	r1, r1, #0xa3000000
7154	orr	r1, r1, #0xa0000
7155	orr	r1, r1, #0x2c00
7156#else
7157#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7158	mov	r1, #0x13
7159	orr	r1, r1, #0x2c00
7160#else
7161	mov	r1, #0x2c13
7162#endif
7163#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7164	orr	r1, r1, #0xa3000000
7165	orr	r1, r1, #0xa0000
7166#else
7167	movt	r1, #0xa30a
7168#endif
7169#endif
7170	mov	lr, #0
7171	ldm	r0!, {r10, r11}
7172	umlal	r10, lr, r2, r1
7173	adds	r11, r11, lr
7174	mov	lr, #0
7175	adc	lr, lr, #0
7176	umlal	r11, lr, r3, r1
7177	stm	r12!, {r10, r11}
7178	ldm	r0!, {r10, r11}
7179	adds	r10, r10, lr
7180	mov	lr, #0
7181	adc	lr, lr, #0
7182	umlal	r10, lr, r4, r1
7183	adds	r11, r11, lr
7184	mov	lr, #0
7185	adc	lr, lr, #0
7186	umlal	r11, lr, r5, r1
7187	stm	r12!, {r10, r11}
7188	ldm	r0!, {r10, r11}
7189	adds	r10, r10, lr
7190	mov	lr, #0
7191	adc	lr, lr, #0
7192	umlal	r10, lr, r6, r1
7193	adds	r11, r11, lr
7194	mov	lr, #0
7195	adc	lr, lr, #0
7196	umlal	r11, lr, r7, r1
7197	stm	r12!, {r10, r11}
7198	ldm	r0!, {r10, r11}
7199	adds	r10, r10, lr
7200	mov	lr, #0
7201	adc	lr, lr, #0
7202	umlal	r10, lr, r8, r1
7203#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7204	bic	r11, r11, #0xf0000000
7205#else
7206	bfc	r11, #28, #4
7207#endif
7208	adds	r11, r11, lr
7209	mov	lr, #0
7210	adc	lr, lr, #0
7211	umlal	r11, lr, r9, r1
7212	stm	r12!, {r10, r11, lr}
7213	sub	r0, r0, #16
7214	sub	r12, r12, #32
7215#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7216	mov	r1, #0xe5
7217	orr	r1, r1, #0xa7000000
7218	orr	r1, r1, #0xed0000
7219	orr	r1, r1, #0x9c00
7220#else
7221#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7222	mov	r1, #0xe5
7223	orr	r1, r1, #0x9c00
7224#else
7225	mov	r1, #0x9ce5
7226#endif
7227#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7228	orr	r1, r1, #0xa7000000
7229	orr	r1, r1, #0xed0000
7230#else
7231	movt	r1, #0xa7ed
7232#endif
7233#endif
7234	mov	lr, #0
7235	ldm	r12, {r10, r11}
7236	umlal	r10, lr, r2, r1
7237	adds	r11, r11, lr
7238	mov	lr, #0
7239	adc	lr, lr, #0
7240	umlal	r11, lr, r3, r1
7241	stm	r12!, {r10, r11}
7242	ldm	r12, {r10, r11}
7243	adds	r10, r10, lr
7244	mov	lr, #0
7245	adc	lr, lr, #0
7246	umlal	r10, lr, r4, r1
7247	adds	r11, r11, lr
7248	mov	lr, #0
7249	adc	lr, lr, #0
7250	umlal	r11, lr, r5, r1
7251	stm	r12!, {r10, r11}
7252	ldm	r12, {r10, r11}
7253	adds	r10, r10, lr
7254	mov	lr, #0
7255	adc	lr, lr, #0
7256	umlal	r10, lr, r6, r1
7257	adds	r11, r11, lr
7258	mov	lr, #0
7259	adc	lr, lr, #0
7260	umlal	r11, lr, r7, r1
7261	stm	r12!, {r10, r11}
7262	ldm	r12, {r10, r11}
7263	adds	r10, r10, lr
7264	mov	lr, #0
7265	adc	lr, lr, #0
7266	umlal	r10, lr, r8, r1
7267	adds	r11, r11, lr
7268	mov	lr, #0
7269	adc	lr, lr, #0
7270	umlal	r11, lr, r9, r1
7271	stm	r12!, {r10, r11, lr}
7272	sub	r12, r12, #32
7273#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7274	mov	r1, #41
7275	orr	r1, r1, #0x5d000000
7276	orr	r1, r1, #0x80000
7277	orr	r1, r1, #0x6300
7278#else
7279#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7280	mov	r1, #0x29
7281	orr	r1, r1, #0x6300
7282#else
7283	mov	r1, #0x6329
7284#endif
7285#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7286	orr	r1, r1, #0x5d000000
7287	orr	r1, r1, #0x80000
7288#else
7289	movt	r1, #0x5d08
7290#endif
7291#endif
7292	mov	lr, #0
7293	ldm	r12, {r10, r11}
7294	umlal	r10, lr, r2, r1
7295	adds	r11, r11, lr
7296	mov	lr, #0
7297	adc	lr, lr, #0
7298	umlal	r11, lr, r3, r1
7299	stm	r12!, {r10, r11}
7300	ldm	r12, {r10, r11}
7301	adds	r10, r10, lr
7302	mov	lr, #0
7303	adc	lr, lr, #0
7304	umlal	r10, lr, r4, r1
7305	adds	r11, r11, lr
7306	mov	lr, #0
7307	adc	lr, lr, #0
7308	umlal	r11, lr, r5, r1
7309	stm	r12!, {r10, r11}
7310	ldm	r12, {r10, r11}
7311	adds	r10, r10, lr
7312	mov	lr, #0
7313	adc	lr, lr, #0
7314	umlal	r10, lr, r6, r1
7315	adds	r11, r11, lr
7316	mov	lr, #0
7317	adc	lr, lr, #0
7318	umlal	r11, lr, r7, r1
7319	stm	r12!, {r10, r11}
7320	ldm	r12, {r10, r11}
7321	adds	r10, r10, lr
7322	mov	lr, #0
7323	adc	lr, lr, #0
7324	umlal	r10, lr, r8, r1
7325	adds	r11, r11, lr
7326	mov	lr, #0
7327	adc	lr, lr, #0
7328	umlal	r11, lr, r9, r1
7329	stm	r12!, {r10, r11, lr}
7330	sub	r12, r12, #32
7331#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7332	mov	r1, #33
7333	orr	r1, r1, #0xeb000000
7334	orr	r1, r1, #0x210000
7335	orr	r1, r1, #0x600
7336#else
7337#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7338	mov	r1, #0x21
7339	orr	r1, r1, #0x600
7340#else
7341	mov	r1, #0x621
7342#endif
7343#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7344	orr	r1, r1, #0xeb000000
7345	orr	r1, r1, #0x210000
7346#else
7347	movt	r1, #0xeb21
7348#endif
7349#endif
7350	mov	lr, #0
7351	ldm	r12, {r10, r11}
7352	umlal	r10, lr, r2, r1
7353	adds	r11, r11, lr
7354	mov	lr, #0
7355	adc	lr, lr, #0
7356	umlal	r11, lr, r3, r1
7357	stm	r12!, {r10, r11}
7358	ldm	r12, {r10, r11}
7359	adds	r10, r10, lr
7360	mov	lr, #0
7361	adc	lr, lr, #0
7362	umlal	r10, lr, r4, r1
7363	adds	r11, r11, lr
7364	mov	lr, #0
7365	adc	lr, lr, #0
7366	umlal	r11, lr, r5, r1
7367	stm	r12!, {r10, r11}
7368	ldm	r12, {r10, r11}
7369	adds	r10, r10, lr
7370	mov	lr, #0
7371	adc	lr, lr, #0
7372	umlal	r10, lr, r6, r1
7373	adds	r11, r11, lr
7374	mov	lr, #0
7375	adc	lr, lr, #0
7376	umlal	r11, lr, r7, r1
7377	stm	r12!, {r10, r11}
7378	ldm	r12, {r10, r11}
7379	adds	r10, r10, lr
7380	mov	lr, #0
7381	adc	lr, lr, #0
7382	umlal	r10, lr, r8, r1
7383	adds	r11, r11, lr
7384	mov	lr, #0
7385	adc	lr, lr, #0
7386	umlal	r11, lr, r9, r1
7387	stm	r12!, {r10, r11, lr}
7388	sub	r12, r12, #32
7389	# Subtract at 4 * 32
7390	ldm	r12, {r10, r11}
7391	subs	r10, r10, r2
7392	sbcs	r11, r11, r3
7393	stm	r12!, {r10, r11}
7394	ldm	r12, {r10, r11}
7395	sbcs	r10, r10, r4
7396	sbcs	r11, r11, r5
7397	stm	r12!, {r10, r11}
7398	ldm	r12, {r10, r11}
7399	sbcs	r10, r10, r6
7400	sbcs	r11, r11, r7
7401	stm	r12!, {r10, r11}
7402	ldm	r12, {r10, r11}
7403	sbcs	r10, r10, r8
7404	sbc	r11, r11, r9
7405	stm	r12!, {r10, r11}
7406	sub	r12, r12, #36
7407	asr	lr, r11, #25
7408	# Conditionally subtract order starting at bit 125
7409	mov	r1, #0xa0000000
7410#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7411	mov	r2, #0x7d
7412	orr	r2, r2, #0x4b000000
7413	orr	r2, r2, #0x9e0000
7414	orr	r2, r2, #0xba00
7415#else
7416#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7417	mov	r2, #0x7d
7418	orr	r2, r2, #0xba00
7419#else
7420	mov	r2, #0xba7d
7421#endif
7422#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7423	orr	r2, r2, #0x4b000000
7424	orr	r2, r2, #0x9e0000
7425#else
7426	movt	r2, #0x4b9e
7427#endif
7428#endif
7429#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7430	mov	r3, #0x63
7431	orr	r3, r3, #0xcb000000
7432	orr	r3, r3, #0x20000
7433	orr	r3, r3, #0x4c00
7434#else
7435#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7436	mov	r3, #0x63
7437	orr	r3, r3, #0x4c00
7438#else
7439	mov	r3, #0x4c63
7440#endif
7441#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7442	orr	r3, r3, #0xcb000000
7443	orr	r3, r3, #0x20000
7444#else
7445	movt	r3, #0xcb02
7446#endif
7447#endif
7448#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7449	mov	r4, #0x9a
7450	orr	r4, r4, #0xd4000000
7451	orr	r4, r4, #0x5e0000
7452	orr	r4, r4, #0xf300
7453#else
7454#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7455	mov	r4, #0x9a
7456	orr	r4, r4, #0xf300
7457#else
7458	mov	r4, #0xf39a
7459#endif
7460#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7461	orr	r4, r4, #0xd4000000
7462	orr	r4, r4, #0x5e0000
7463#else
7464	movt	r4, #0xd45e
7465#endif
7466#endif
7467#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7468	mov	r5, #59
7469	orr	r5, r5, #0x2000000
7470	orr	r5, r5, #0x9b0000
7471	orr	r5, r5, #0xdf00
7472#else
7473#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7474	mov	r5, #0x3b
7475	orr	r5, r5, #0xdf00
7476#else
7477	mov	r5, #0xdf3b
7478#endif
7479#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7480	orr	r5, r5, #0x2000000
7481	orr	r5, r5, #0x9b0000
7482#else
7483	movt	r5, #0x29b
7484#endif
7485#endif
7486	mov	r9, #0x2000000
7487	and	r1, r1, lr
7488	and	r2, r2, lr
7489	and	r3, r3, lr
7490	and	r4, r4, lr
7491	and	r5, r5, lr
7492	and	r9, r9, lr
7493	ldm	r12, {r10, r11}
7494	adds	r10, r10, r1
7495	adcs	r11, r11, r2
7496	stm	r12!, {r10, r11}
7497	ldm	r12, {r10, r11}
7498	adcs	r10, r10, r3
7499	adcs	r11, r11, r4
7500	stm	r12!, {r10, r11}
7501	ldm	r12, {r10, r11}
7502	adcs	r10, r10, r5
7503	adcs	r11, r11, #0
7504	stm	r12!, {r10, r11}
7505	ldm	r12, {r10, r11}
7506	adcs	r10, r10, #0
7507	adcs	r11, r11, #0
7508	stm	r12!, {r10, r11}
7509	ldm	r12, {r10}
7510	adcs	r10, r10, #0
7511	stm	r12!, {r10}
7512	sub	r0, r0, #16
7513	mov	r12, sp
7514	# Load bits 252-376
7515	add	r12, r12, #28
7516	ldm	r12, {r1, r2, r3, r4, r5}
7517	lsl	r5, r5, #4
7518	orr	r5, r5, r4, lsr #28
7519	lsl	r4, r4, #4
7520	orr	r4, r4, r3, lsr #28
7521	lsl	r3, r3, #4
7522	orr	r3, r3, r2, lsr #28
7523	lsl	r2, r2, #4
7524	orr	r2, r2, r1, lsr #28
7525#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7526	bic	r5, r5, #0xe0000000
7527#else
7528	bfc	r5, #29, #3
7529#endif
7530	sub	r12, r12, #28
7531	# Sub product of top 4 words and order
7532	mov	r0, sp
7533	#   * -5cf5d3ed
7534#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7535	mov	r1, #19
7536	orr	r1, r1, #0xa3000000
7537	orr	r1, r1, #0xa0000
7538	orr	r1, r1, #0x2c00
7539#else
7540#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7541	mov	r1, #0x13
7542	orr	r1, r1, #0x2c00
7543#else
7544	mov	r1, #0x2c13
7545#endif
7546#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7547	orr	r1, r1, #0xa3000000
7548	orr	r1, r1, #0xa0000
7549#else
7550	movt	r1, #0xa30a
7551#endif
7552#endif
7553	mov	lr, #0
7554	ldm	r0, {r6, r7, r8, r9}
7555	umlal	r6, lr, r2, r1
7556	adds	r7, r7, lr
7557	mov	lr, #0
7558	adc	lr, lr, #0
7559	umlal	r7, lr, r3, r1
7560	adds	r8, r8, lr
7561	mov	lr, #0
7562	adc	lr, lr, #0
7563	umlal	r8, lr, r4, r1
7564	adds	r9, r9, lr
7565	mov	lr, #0
7566	adc	lr, lr, #0
7567	umlal	r9, lr, r5, r1
7568	stm	r0, {r6, r7, r8, r9}
7569	add	r0, r0, #4
7570	#   * -5812631b
7571#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7572	mov	r1, #0xe5
7573	orr	r1, r1, #0xa7000000
7574	orr	r1, r1, #0xed0000
7575	orr	r1, r1, #0x9c00
7576#else
7577#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7578	mov	r1, #0xe5
7579	orr	r1, r1, #0x9c00
7580#else
7581	mov	r1, #0x9ce5
7582#endif
7583#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7584	orr	r1, r1, #0xa7000000
7585	orr	r1, r1, #0xed0000
7586#else
7587	movt	r1, #0xa7ed
7588#endif
7589#endif
7590	mov	r10, #0
7591	ldm	r0, {r6, r7, r8, r9}
7592	umlal	r6, r10, r2, r1
7593	adds	r7, r7, r10
7594	mov	r10, #0
7595	adc	r10, r10, #0
7596	umlal	r7, r10, r3, r1
7597	adds	r8, r8, r10
7598	mov	r10, #0
7599	adc	r10, r10, #0
7600	umlal	r8, r10, r4, r1
7601	adds	r9, r9, r10
7602	mov	r10, #0
7603	adc	r10, r10, #0
7604	umlal	r9, r10, r5, r1
7605	stm	r0, {r6, r7, r8, r9}
7606	add	r0, r0, #4
7607	#   * -a2f79cd7
7608#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7609	mov	r1, #41
7610	orr	r1, r1, #0x5d000000
7611	orr	r1, r1, #0x80000
7612	orr	r1, r1, #0x6300
7613#else
7614#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7615	mov	r1, #0x29
7616	orr	r1, r1, #0x6300
7617#else
7618	mov	r1, #0x6329
7619#endif
7620#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7621	orr	r1, r1, #0x5d000000
7622	orr	r1, r1, #0x80000
7623#else
7624	movt	r1, #0x5d08
7625#endif
7626#endif
7627	mov	r11, #0
7628	ldm	r0, {r6, r7, r8, r9}
7629	umlal	r6, r11, r2, r1
7630	adds	r7, r7, r11
7631	mov	r11, #0
7632	adc	r11, r11, #0
7633	umlal	r7, r11, r3, r1
7634	adds	r8, r8, r11
7635	mov	r11, #0
7636	adc	r11, r11, #0
7637	umlal	r8, r11, r4, r1
7638	adds	r9, r9, r11
7639	mov	r11, #0
7640	adc	r11, r11, #0
7641	umlal	r9, r11, r5, r1
7642	stm	r0, {r6, r7, r8, r9}
7643	add	r0, r0, #4
7644	#   * -14def9df
7645#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7646	mov	r1, #33
7647	orr	r1, r1, #0xeb000000
7648	orr	r1, r1, #0x210000
7649	orr	r1, r1, #0x600
7650#else
7651#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7652	mov	r1, #0x21
7653	orr	r1, r1, #0x600
7654#else
7655	mov	r1, #0x621
7656#endif
7657#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7658	orr	r1, r1, #0xeb000000
7659	orr	r1, r1, #0x210000
7660#else
7661	movt	r1, #0xeb21
7662#endif
7663#endif
7664	mov	r12, #0
7665	ldm	r0, {r6, r7, r8, r9}
7666	umlal	r6, r12, r2, r1
7667	adds	r7, r7, r12
7668	mov	r12, #0
7669	adc	r12, r12, #0
7670	umlal	r7, r12, r3, r1
7671	adds	r8, r8, r12
7672	mov	r12, #0
7673	adc	r12, r12, #0
7674	umlal	r8, r12, r4, r1
7675	adds	r9, r9, r12
7676	mov	r12, #0
7677	adc	r12, r12, #0
7678	umlal	r9, r12, r5, r1
7679	stm	r0, {r6, r7, r8, r9}
7680	add	r0, r0, #4
7681	# Add overflows at 4 * 32
7682	ldm	r0, {r6, r7, r8, r9}
7683#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7684	bic	r9, r9, #0xf0000000
7685#else
7686	bfc	r9, #28, #4
7687#endif
7688	adds	r6, r6, lr
7689	adcs	r7, r7, r10
7690	adcs	r8, r8, r11
7691	adc	r9, r9, r12
7692	# Subtract top at 4 * 32
7693	subs	r6, r6, r2
7694	sbcs	r7, r7, r3
7695	sbcs	r8, r8, r4
7696	sbcs	r9, r9, r5
7697	sbc	r1, r1, r1
7698	sub	r0, r0, #16
7699	ldm	r0, {r2, r3, r4, r5}
7700#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7701	mov	r10, #0xed
7702	orr	r10, r10, #0x5c000000
7703	orr	r10, r10, #0xf50000
7704	orr	r10, r10, #0xd300
7705#else
7706#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7707	mov	r10, #0xed
7708	orr	r10, r10, #0xd300
7709#else
7710	mov	r10, #0xd3ed
7711#endif
7712#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7713	orr	r10, r10, #0x5c000000
7714	orr	r10, r10, #0xf50000
7715#else
7716	movt	r10, #0x5cf5
7717#endif
7718#endif
7719#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7720	mov	r11, #26
7721	orr	r11, r11, #0x58000000
7722	orr	r11, r11, #0x120000
7723	orr	r11, r11, #0x6300
7724#else
7725#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7726	mov	r11, #0x1a
7727	orr	r11, r11, #0x6300
7728#else
7729	mov	r11, #0x631a
7730#endif
7731#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7732	orr	r11, r11, #0x58000000
7733	orr	r11, r11, #0x120000
7734#else
7735	movt	r11, #0x5812
7736#endif
7737#endif
7738#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7739	mov	r12, #0xd6
7740	orr	r12, r12, #0xa2000000
7741	orr	r12, r12, #0xf70000
7742	orr	r12, r12, #0x9c00
7743#else
7744#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7745	mov	r12, #0xd6
7746	orr	r12, r12, #0x9c00
7747#else
7748	mov	r12, #0x9cd6
7749#endif
7750#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7751	orr	r12, r12, #0xa2000000
7752	orr	r12, r12, #0xf70000
7753#else
7754	movt	r12, #0xa2f7
7755#endif
7756#endif
7757#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7758	mov	lr, #0xde
7759	orr	lr, lr, #0x14000000
7760	orr	lr, lr, #0xde0000
7761	orr	lr, lr, #0xf900
7762#else
7763#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7764	mov	lr, #0xde
7765	orr	lr, lr, #0xf900
7766#else
7767	mov	lr, #0xf9de
7768#endif
7769#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7770	orr	lr, lr, #0x14000000
7771	orr	lr, lr, #0xde0000
7772#else
7773	movt	lr, #0x14de
7774#endif
7775#endif
7776	and	r10, r10, r1
7777	and	r11, r11, r1
7778	and	r12, r12, r1
7779	and	lr, lr, r1
7780	adds	r2, r2, r10
7781	adcs	r3, r3, r11
7782	adcs	r4, r4, r12
7783	adcs	r5, r5, lr
7784	adcs	r6, r6, #0
7785	adcs	r7, r7, #0
7786	and	r1, r1, #0x10000000
7787	adcs	r8, r8, #0
7788	adc	r9, r9, r1
7789#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7790	bic	r9, r9, #0xf0000000
7791#else
7792	bfc	r9, #28, #4
7793#endif
7794	ldr	r0, [sp, #68]
7795	# Store result
7796	str	r2, [r0]
7797	str	r3, [r0, #4]
7798	str	r4, [r0, #8]
7799	str	r5, [r0, #12]
7800	str	r6, [r0, #16]
7801	str	r7, [r0, #20]
7802	str	r8, [r0, #24]
7803	str	r9, [r0, #28]
7804	add	sp, sp, #0x50
7805	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
7806	.size	sc_muladd,.-sc_muladd
7807#else
7808	.text
7809	.align	4
7810	.globl	sc_muladd
7811	.type	sc_muladd, %function
7812sc_muladd:
7813	push	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
7814	sub	sp, sp, #0x50
7815	add	lr, sp, #0x44
7816	stm	lr, {r0, r1, r3}
7817	mov	lr, r2
7818	ldm	r1, {r0, r1, r2, r3}
7819	ldm	lr!, {r4, r5, r6}
7820	umull	r10, r11, r0, r4
7821	umull	r12, r7, r1, r4
7822	umaal	r11, r12, r0, r5
7823	umull	r8, r9, r2, r4
7824	umaal	r12, r8, r1, r5
7825	umaal	r12, r7, r0, r6
7826	umaal	r8, r9, r3, r4
7827	stm	sp, {r10, r11, r12}
7828	umaal	r7, r8, r2, r5
7829	ldm	lr!, {r4}
7830	umull	r10, r11, r1, r6
7831	umaal	r8, r9, r2, r6
7832	umaal	r7, r10, r0, r4
7833	umaal	r8, r11, r3, r5
7834	str	r7, [sp, #12]
7835	umaal	r8, r10, r1, r4
7836	umaal	r9, r11, r3, r6
7837	umaal	r9, r10, r2, r4
7838	umaal	r10, r11, r3, r4
7839	ldm	lr, {r4, r5, r6, r7}
7840	mov	r12, #0
7841	umlal	r8, r12, r0, r4
7842	umaal	r9, r12, r1, r4
7843	umaal	r10, r12, r2, r4
7844	umaal	r11, r12, r3, r4
7845	mov	r4, #0
7846	umlal	r9, r4, r0, r5
7847	umaal	r10, r4, r1, r5
7848	umaal	r11, r4, r2, r5
7849	umaal	r12, r4, r3, r5
7850	mov	r5, #0
7851	umlal	r10, r5, r0, r6
7852	umaal	r11, r5, r1, r6
7853	umaal	r12, r5, r2, r6
7854	umaal	r4, r5, r3, r6
7855	mov	r6, #0
7856	umlal	r11, r6, r0, r7
7857	ldr	r0, [sp, #72]
7858	umaal	r12, r6, r1, r7
7859	add	r0, r0, #16
7860	umaal	r4, r6, r2, r7
7861	sub	lr, lr, #16
7862	umaal	r5, r6, r3, r7
7863	ldm	r0, {r0, r1, r2, r3}
7864	str	r6, [sp, #64]
7865	ldm	lr!, {r6}
7866	mov	r7, #0
7867	umlal	r8, r7, r0, r6
7868	umaal	r9, r7, r1, r6
7869	str	r8, [sp, #16]
7870	umaal	r10, r7, r2, r6
7871	umaal	r11, r7, r3, r6
7872	ldm	lr!, {r6}
7873	mov	r8, #0
7874	umlal	r9, r8, r0, r6
7875	umaal	r10, r8, r1, r6
7876	str	r9, [sp, #20]
7877	umaal	r11, r8, r2, r6
7878	umaal	r12, r8, r3, r6
7879	ldm	lr!, {r6}
7880	mov	r9, #0
7881	umlal	r10, r9, r0, r6
7882	umaal	r11, r9, r1, r6
7883	str	r10, [sp, #24]
7884	umaal	r12, r9, r2, r6
7885	umaal	r4, r9, r3, r6
7886	ldm	lr!, {r6}
7887	mov	r10, #0
7888	umlal	r11, r10, r0, r6
7889	umaal	r12, r10, r1, r6
7890	str	r11, [sp, #28]
7891	umaal	r4, r10, r2, r6
7892	umaal	r5, r10, r3, r6
7893	ldm	lr!, {r11}
7894	umaal	r12, r7, r0, r11
7895	umaal	r4, r7, r1, r11
7896	ldr	r6, [sp, #64]
7897	umaal	r5, r7, r2, r11
7898	umaal	r6, r7, r3, r11
7899	ldm	lr!, {r11}
7900	umaal	r4, r8, r0, r11
7901	umaal	r5, r8, r1, r11
7902	umaal	r6, r8, r2, r11
7903	umaal	r7, r8, r3, r11
7904	ldm	lr, {r11, lr}
7905	umaal	r5, r9, r0, r11
7906	umaal	r6, r10, r0, lr
7907	umaal	r6, r9, r1, r11
7908	umaal	r7, r10, r1, lr
7909	umaal	r7, r9, r2, r11
7910	umaal	r8, r10, r2, lr
7911	umaal	r8, r9, r3, r11
7912	umaal	r9, r10, r3, lr
7913	mov	r3, r12
7914	add	lr, sp, #32
7915	stm	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
7916	mov	r0, sp
7917	# Add c to a * b
7918	ldr	lr, [sp, #76]
7919	ldm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
7920	ldm	lr!, {r1, r10, r11, r12}
7921	adds	r2, r2, r1
7922	adcs	r3, r3, r10
7923	adcs	r4, r4, r11
7924	adcs	r5, r5, r12
7925	ldm	lr!, {r1, r10, r11, r12}
7926	adcs	r6, r6, r1
7927	adcs	r7, r7, r10
7928	adcs	r8, r8, r11
7929	adcs	r9, r9, r12
7930	mov	r1, r9
7931	stm	r0!, {r2, r3, r4, r5, r6, r7, r8, r9}
7932	ldm	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
7933	adcs	r2, r2, #0
7934	adcs	r3, r3, #0
7935	adcs	r4, r4, #0
7936	adcs	r5, r5, #0
7937	adcs	r6, r6, #0
7938	adcs	r7, r7, #0
7939	adcs	r8, r8, #0
7940	adc	r9, r9, #0
7941	sub	r0, r0, #32
7942	# Get 252..503 and 504..507
7943	lsr	lr, r9, #24
7944	lsl	r9, r9, #4
7945	orr	r9, r9, r8, lsr #28
7946	lsl	r8, r8, #4
7947	orr	r8, r8, r7, lsr #28
7948	lsl	r7, r7, #4
7949	orr	r7, r7, r6, lsr #28
7950	lsl	r6, r6, #4
7951	orr	r6, r6, r5, lsr #28
7952	lsl	r5, r5, #4
7953	orr	r5, r5, r4, lsr #28
7954	lsl	r4, r4, #4
7955	orr	r4, r4, r3, lsr #28
7956	lsl	r3, r3, #4
7957	orr	r3, r3, r2, lsr #28
7958	lsl	r2, r2, #4
7959	orr	r2, r2, r1, lsr #28
7960#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7961	bic	r9, r9, #0xf0000000
7962#else
7963	bfc	r9, #28, #4
7964#endif
7965	# Add order times bits 504..507
7966#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7967	mov	r10, #19
7968	orr	r10, r10, #0xa3000000
7969	orr	r10, r10, #0xa0000
7970	orr	r10, r10, #0x2c00
7971#else
7972#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7973	mov	r10, #0x13
7974	orr	r10, r10, #0x2c00
7975#else
7976	mov	r10, #0x2c13
7977#endif
7978#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7979	orr	r10, r10, #0xa3000000
7980	orr	r10, r10, #0xa0000
7981#else
7982	movt	r10, #0xa30a
7983#endif
7984#endif
7985#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7986	mov	r11, #0xe5
7987	orr	r11, r11, #0xa7000000
7988	orr	r11, r11, #0xed0000
7989	orr	r11, r11, #0x9c00
7990#else
7991#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7992	mov	r11, #0xe5
7993	orr	r11, r11, #0x9c00
7994#else
7995	mov	r11, #0x9ce5
7996#endif
7997#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
7998	orr	r11, r11, #0xa7000000
7999	orr	r11, r11, #0xed0000
8000#else
8001	movt	r11, #0xa7ed
8002#endif
8003#endif
8004	mov	r1, #0
8005	umlal	r2, r1, r10, lr
8006	umaal	r3, r1, r11, lr
8007#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8008	mov	r10, #41
8009	orr	r10, r10, #0x5d000000
8010	orr	r10, r10, #0x80000
8011	orr	r10, r10, #0x6300
8012#else
8013#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8014	mov	r10, #0x29
8015	orr	r10, r10, #0x6300
8016#else
8017	mov	r10, #0x6329
8018#endif
8019#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8020	orr	r10, r10, #0x5d000000
8021	orr	r10, r10, #0x80000
8022#else
8023	movt	r10, #0x5d08
8024#endif
8025#endif
8026#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8027	mov	r11, #33
8028	orr	r11, r11, #0xeb000000
8029	orr	r11, r11, #0x210000
8030	orr	r11, r11, #0x600
8031#else
8032#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8033	mov	r11, #0x21
8034	orr	r11, r11, #0x600
8035#else
8036	mov	r11, #0x621
8037#endif
8038#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8039	orr	r11, r11, #0xeb000000
8040	orr	r11, r11, #0x210000
8041#else
8042	movt	r11, #0xeb21
8043#endif
8044#endif
8045	umaal	r4, r1, r10, lr
8046	umaal	r5, r1, r11, lr
8047	adds	r6, r6, r1
8048	adcs	r7, r7, #0
8049	adcs	r8, r8, #0
8050	adc	r9, r9, #0
8051	subs	r6, r6, lr
8052	sbcs	r7, r7, #0
8053	sbcs	r8, r8, #0
8054	sbc	r9, r9, #0
8055	# Sub product of top 8 words and order
8056	mov	r12, sp
8057#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8058	mov	r1, #19
8059	orr	r1, r1, #0xa3000000
8060	orr	r1, r1, #0xa0000
8061	orr	r1, r1, #0x2c00
8062#else
8063#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8064	mov	r1, #0x13
8065	orr	r1, r1, #0x2c00
8066#else
8067	mov	r1, #0x2c13
8068#endif
8069#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8070	orr	r1, r1, #0xa3000000
8071	orr	r1, r1, #0xa0000
8072#else
8073	movt	r1, #0xa30a
8074#endif
8075#endif
8076	mov	lr, #0
8077	ldm	r0!, {r10, r11}
8078	umlal	r10, lr, r2, r1
8079	umaal	r11, lr, r3, r1
8080	stm	r12!, {r10, r11}
8081	ldm	r0!, {r10, r11}
8082	umaal	r10, lr, r4, r1
8083	umaal	r11, lr, r5, r1
8084	stm	r12!, {r10, r11}
8085	ldm	r0!, {r10, r11}
8086	umaal	r10, lr, r6, r1
8087	umaal	r11, lr, r7, r1
8088	stm	r12!, {r10, r11}
8089	ldm	r0!, {r10, r11}
8090	umaal	r10, lr, r8, r1
8091#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8092	bic	r11, r11, #0xf0000000
8093#else
8094	bfc	r11, #28, #4
8095#endif
8096	umaal	r11, lr, r9, r1
8097	stm	r12!, {r10, r11, lr}
8098	sub	r0, r0, #16
8099	sub	r12, r12, #32
8100#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8101	mov	r1, #0xe5
8102	orr	r1, r1, #0xa7000000
8103	orr	r1, r1, #0xed0000
8104	orr	r1, r1, #0x9c00
8105#else
8106#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8107	mov	r1, #0xe5
8108	orr	r1, r1, #0x9c00
8109#else
8110	mov	r1, #0x9ce5
8111#endif
8112#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8113	orr	r1, r1, #0xa7000000
8114	orr	r1, r1, #0xed0000
8115#else
8116	movt	r1, #0xa7ed
8117#endif
8118#endif
8119	mov	lr, #0
8120	ldm	r12, {r10, r11}
8121	umlal	r10, lr, r2, r1
8122	umaal	r11, lr, r3, r1
8123	stm	r12!, {r10, r11}
8124	ldm	r12, {r10, r11}
8125	umaal	r10, lr, r4, r1
8126	umaal	r11, lr, r5, r1
8127	stm	r12!, {r10, r11}
8128	ldm	r12, {r10, r11}
8129	umaal	r10, lr, r6, r1
8130	umaal	r11, lr, r7, r1
8131	stm	r12!, {r10, r11}
8132	ldm	r12, {r10, r11}
8133	umaal	r10, lr, r8, r1
8134	umaal	r11, lr, r9, r1
8135	stm	r12!, {r10, r11, lr}
8136	sub	r12, r12, #32
8137#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8138	mov	r1, #41
8139	orr	r1, r1, #0x5d000000
8140	orr	r1, r1, #0x80000
8141	orr	r1, r1, #0x6300
8142#else
8143#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8144	mov	r1, #0x29
8145	orr	r1, r1, #0x6300
8146#else
8147	mov	r1, #0x6329
8148#endif
8149#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8150	orr	r1, r1, #0x5d000000
8151	orr	r1, r1, #0x80000
8152#else
8153	movt	r1, #0x5d08
8154#endif
8155#endif
8156	mov	lr, #0
8157	ldm	r12, {r10, r11}
8158	umlal	r10, lr, r2, r1
8159	umaal	r11, lr, r3, r1
8160	stm	r12!, {r10, r11}
8161	ldm	r12, {r10, r11}
8162	umaal	r10, lr, r4, r1
8163	umaal	r11, lr, r5, r1
8164	stm	r12!, {r10, r11}
8165	ldm	r12, {r10, r11}
8166	umaal	r10, lr, r6, r1
8167	umaal	r11, lr, r7, r1
8168	stm	r12!, {r10, r11}
8169	ldm	r12, {r10, r11}
8170	umaal	r10, lr, r8, r1
8171	umaal	r11, lr, r9, r1
8172	stm	r12!, {r10, r11, lr}
8173	sub	r12, r12, #32
8174#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8175	mov	r1, #33
8176	orr	r1, r1, #0xeb000000
8177	orr	r1, r1, #0x210000
8178	orr	r1, r1, #0x600
8179#else
8180#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8181	mov	r1, #0x21
8182	orr	r1, r1, #0x600
8183#else
8184	mov	r1, #0x621
8185#endif
8186#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8187	orr	r1, r1, #0xeb000000
8188	orr	r1, r1, #0x210000
8189#else
8190	movt	r1, #0xeb21
8191#endif
8192#endif
8193	mov	lr, #0
8194	ldm	r12, {r10, r11}
8195	umlal	r10, lr, r2, r1
8196	umaal	r11, lr, r3, r1
8197	stm	r12!, {r10, r11}
8198	ldm	r12, {r10, r11}
8199	umaal	r10, lr, r4, r1
8200	umaal	r11, lr, r5, r1
8201	stm	r12!, {r10, r11}
8202	ldm	r12, {r10, r11}
8203	umaal	r10, lr, r6, r1
8204	umaal	r11, lr, r7, r1
8205	stm	r12!, {r10, r11}
8206	ldm	r12, {r10, r11}
8207	umaal	r10, lr, r8, r1
8208	umaal	r11, lr, r9, r1
8209	stm	r12!, {r10, r11, lr}
8210	sub	r12, r12, #32
8211	# Subtract at 4 * 32
8212	ldm	r12, {r10, r11}
8213	subs	r10, r10, r2
8214	sbcs	r11, r11, r3
8215	stm	r12!, {r10, r11}
8216	ldm	r12, {r10, r11}
8217	sbcs	r10, r10, r4
8218	sbcs	r11, r11, r5
8219	stm	r12!, {r10, r11}
8220	ldm	r12, {r10, r11}
8221	sbcs	r10, r10, r6
8222	sbcs	r11, r11, r7
8223	stm	r12!, {r10, r11}
8224	ldm	r12, {r10, r11}
8225	sbcs	r10, r10, r8
8226	sbc	r11, r11, r9
8227	stm	r12!, {r10, r11}
8228	sub	r12, r12, #36
8229	asr	lr, r11, #25
8230	# Conditionally subtract order starting at bit 125
8231	mov	r1, #0xa0000000
8232#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8233	mov	r2, #0x7d
8234	orr	r2, r2, #0x4b000000
8235	orr	r2, r2, #0x9e0000
8236	orr	r2, r2, #0xba00
8237#else
8238#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8239	mov	r2, #0x7d
8240	orr	r2, r2, #0xba00
8241#else
8242	mov	r2, #0xba7d
8243#endif
8244#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8245	orr	r2, r2, #0x4b000000
8246	orr	r2, r2, #0x9e0000
8247#else
8248	movt	r2, #0x4b9e
8249#endif
8250#endif
8251#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8252	mov	r3, #0x63
8253	orr	r3, r3, #0xcb000000
8254	orr	r3, r3, #0x20000
8255	orr	r3, r3, #0x4c00
8256#else
8257#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8258	mov	r3, #0x63
8259	orr	r3, r3, #0x4c00
8260#else
8261	mov	r3, #0x4c63
8262#endif
8263#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8264	orr	r3, r3, #0xcb000000
8265	orr	r3, r3, #0x20000
8266#else
8267	movt	r3, #0xcb02
8268#endif
8269#endif
8270#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8271	mov	r4, #0x9a
8272	orr	r4, r4, #0xd4000000
8273	orr	r4, r4, #0x5e0000
8274	orr	r4, r4, #0xf300
8275#else
8276#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8277	mov	r4, #0x9a
8278	orr	r4, r4, #0xf300
8279#else
8280	mov	r4, #0xf39a
8281#endif
8282#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8283	orr	r4, r4, #0xd4000000
8284	orr	r4, r4, #0x5e0000
8285#else
8286	movt	r4, #0xd45e
8287#endif
8288#endif
8289#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8290	mov	r5, #59
8291	orr	r5, r5, #0x2000000
8292	orr	r5, r5, #0x9b0000
8293	orr	r5, r5, #0xdf00
8294#else
8295#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8296	mov	r5, #0x3b
8297	orr	r5, r5, #0xdf00
8298#else
8299	mov	r5, #0xdf3b
8300#endif
8301#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8302	orr	r5, r5, #0x2000000
8303	orr	r5, r5, #0x9b0000
8304#else
8305	movt	r5, #0x29b
8306#endif
8307#endif
8308	mov	r9, #0x2000000
8309	and	r1, r1, lr
8310	and	r2, r2, lr
8311	and	r3, r3, lr
8312	and	r4, r4, lr
8313	and	r5, r5, lr
8314	and	r9, r9, lr
8315	ldm	r12, {r10, r11}
8316	adds	r10, r10, r1
8317	adcs	r11, r11, r2
8318	stm	r12!, {r10, r11}
8319	ldm	r12, {r10, r11}
8320	adcs	r10, r10, r3
8321	adcs	r11, r11, r4
8322	stm	r12!, {r10, r11}
8323	ldm	r12, {r10, r11}
8324	adcs	r10, r10, r5
8325	adcs	r11, r11, #0
8326	stm	r12!, {r10, r11}
8327	ldm	r12, {r10, r11}
8328	adcs	r10, r10, #0
8329	adcs	r11, r11, #0
8330	stm	r12!, {r10, r11}
8331	ldm	r12, {r10}
8332	adcs	r10, r10, #0
8333	stm	r12!, {r10}
8334	sub	r0, r0, #16
8335	mov	r12, sp
8336	# Load bits 252-376
8337	add	r12, r12, #28
8338	ldm	r12, {r1, r2, r3, r4, r5}
8339	lsl	r5, r5, #4
8340	orr	r5, r5, r4, lsr #28
8341	lsl	r4, r4, #4
8342	orr	r4, r4, r3, lsr #28
8343	lsl	r3, r3, #4
8344	orr	r3, r3, r2, lsr #28
8345	lsl	r2, r2, #4
8346	orr	r2, r2, r1, lsr #28
8347#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8348	bic	r5, r5, #0xe0000000
8349#else
8350	bfc	r5, #29, #3
8351#endif
8352	sub	r12, r12, #28
8353	# Sub product of top 4 words and order
8354	mov	r0, sp
8355	#   * -5cf5d3ed
8356#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8357	mov	r1, #19
8358	orr	r1, r1, #0xa3000000
8359	orr	r1, r1, #0xa0000
8360	orr	r1, r1, #0x2c00
8361#else
8362#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8363	mov	r1, #0x13
8364	orr	r1, r1, #0x2c00
8365#else
8366	mov	r1, #0x2c13
8367#endif
8368#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8369	orr	r1, r1, #0xa3000000
8370	orr	r1, r1, #0xa0000
8371#else
8372	movt	r1, #0xa30a
8373#endif
8374#endif
8375	mov	lr, #0
8376	ldm	r0, {r6, r7, r8, r9}
8377	umlal	r6, lr, r2, r1
8378	umaal	r7, lr, r3, r1
8379	umaal	r8, lr, r4, r1
8380	umaal	r9, lr, r5, r1
8381	stm	r0, {r6, r7, r8, r9}
8382	add	r0, r0, #4
8383	#   * -5812631b
8384#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8385	mov	r1, #0xe5
8386	orr	r1, r1, #0xa7000000
8387	orr	r1, r1, #0xed0000
8388	orr	r1, r1, #0x9c00
8389#else
8390#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8391	mov	r1, #0xe5
8392	orr	r1, r1, #0x9c00
8393#else
8394	mov	r1, #0x9ce5
8395#endif
8396#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8397	orr	r1, r1, #0xa7000000
8398	orr	r1, r1, #0xed0000
8399#else
8400	movt	r1, #0xa7ed
8401#endif
8402#endif
8403	mov	r10, #0
8404	ldm	r0, {r6, r7, r8, r9}
8405	umlal	r6, r10, r2, r1
8406	umaal	r7, r10, r3, r1
8407	umaal	r8, r10, r4, r1
8408	umaal	r9, r10, r5, r1
8409	stm	r0, {r6, r7, r8, r9}
8410	add	r0, r0, #4
8411	#   * -a2f79cd7
8412#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8413	mov	r1, #41
8414	orr	r1, r1, #0x5d000000
8415	orr	r1, r1, #0x80000
8416	orr	r1, r1, #0x6300
8417#else
8418#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8419	mov	r1, #0x29
8420	orr	r1, r1, #0x6300
8421#else
8422	mov	r1, #0x6329
8423#endif
8424#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8425	orr	r1, r1, #0x5d000000
8426	orr	r1, r1, #0x80000
8427#else
8428	movt	r1, #0x5d08
8429#endif
8430#endif
8431	mov	r11, #0
8432	ldm	r0, {r6, r7, r8, r9}
8433	umlal	r6, r11, r2, r1
8434	umaal	r7, r11, r3, r1
8435	umaal	r8, r11, r4, r1
8436	umaal	r9, r11, r5, r1
8437	stm	r0, {r6, r7, r8, r9}
8438	add	r0, r0, #4
8439	#   * -14def9df
8440#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8441	mov	r1, #33
8442	orr	r1, r1, #0xeb000000
8443	orr	r1, r1, #0x210000
8444	orr	r1, r1, #0x600
8445#else
8446#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8447	mov	r1, #0x21
8448	orr	r1, r1, #0x600
8449#else
8450	mov	r1, #0x621
8451#endif
8452#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8453	orr	r1, r1, #0xeb000000
8454	orr	r1, r1, #0x210000
8455#else
8456	movt	r1, #0xeb21
8457#endif
8458#endif
8459	mov	r12, #0
8460	ldm	r0, {r6, r7, r8, r9}
8461	umlal	r6, r12, r2, r1
8462	umaal	r7, r12, r3, r1
8463	umaal	r8, r12, r4, r1
8464	umaal	r9, r12, r5, r1
8465	stm	r0, {r6, r7, r8, r9}
8466	add	r0, r0, #4
8467	# Add overflows at 4 * 32
8468	ldm	r0, {r6, r7, r8, r9}
8469#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8470	bic	r9, r9, #0xf0000000
8471#else
8472	bfc	r9, #28, #4
8473#endif
8474	adds	r6, r6, lr
8475	adcs	r7, r7, r10
8476	adcs	r8, r8, r11
8477	adc	r9, r9, r12
8478	# Subtract top at 4 * 32
8479	subs	r6, r6, r2
8480	sbcs	r7, r7, r3
8481	sbcs	r8, r8, r4
8482	sbcs	r9, r9, r5
8483	sbc	r1, r1, r1
8484	sub	r0, r0, #16
8485	ldm	r0, {r2, r3, r4, r5}
8486#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8487	mov	r10, #0xed
8488	orr	r10, r10, #0x5c000000
8489	orr	r10, r10, #0xf50000
8490	orr	r10, r10, #0xd300
8491#else
8492#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8493	mov	r10, #0xed
8494	orr	r10, r10, #0xd300
8495#else
8496	mov	r10, #0xd3ed
8497#endif
8498#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8499	orr	r10, r10, #0x5c000000
8500	orr	r10, r10, #0xf50000
8501#else
8502	movt	r10, #0x5cf5
8503#endif
8504#endif
8505#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8506	mov	r11, #26
8507	orr	r11, r11, #0x58000000
8508	orr	r11, r11, #0x120000
8509	orr	r11, r11, #0x6300
8510#else
8511#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8512	mov	r11, #0x1a
8513	orr	r11, r11, #0x6300
8514#else
8515	mov	r11, #0x631a
8516#endif
8517#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8518	orr	r11, r11, #0x58000000
8519	orr	r11, r11, #0x120000
8520#else
8521	movt	r11, #0x5812
8522#endif
8523#endif
8524#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8525	mov	r12, #0xd6
8526	orr	r12, r12, #0xa2000000
8527	orr	r12, r12, #0xf70000
8528	orr	r12, r12, #0x9c00
8529#else
8530#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8531	mov	r12, #0xd6
8532	orr	r12, r12, #0x9c00
8533#else
8534	mov	r12, #0x9cd6
8535#endif
8536#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8537	orr	r12, r12, #0xa2000000
8538	orr	r12, r12, #0xf70000
8539#else
8540	movt	r12, #0xa2f7
8541#endif
8542#endif
8543#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8544	mov	lr, #0xde
8545	orr	lr, lr, #0x14000000
8546	orr	lr, lr, #0xde0000
8547	orr	lr, lr, #0xf900
8548#else
8549#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8550	mov	lr, #0xde
8551	orr	lr, lr, #0xf900
8552#else
8553	mov	lr, #0xf9de
8554#endif
8555#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8556	orr	lr, lr, #0x14000000
8557	orr	lr, lr, #0xde0000
8558#else
8559	movt	lr, #0x14de
8560#endif
8561#endif
8562	and	r10, r10, r1
8563	and	r11, r11, r1
8564	and	r12, r12, r1
8565	and	lr, lr, r1
8566	adds	r2, r2, r10
8567	adcs	r3, r3, r11
8568	adcs	r4, r4, r12
8569	adcs	r5, r5, lr
8570	adcs	r6, r6, #0
8571	adcs	r7, r7, #0
8572	and	r1, r1, #0x10000000
8573	adcs	r8, r8, #0
8574	adc	r9, r9, r1
8575#if defined(WOLFSSL_ARM_ARCH) && (WOLFSSL_ARM_ARCH < 7)
8576	bic	r9, r9, #0xf0000000
8577#else
8578	bfc	r9, #28, #4
8579#endif
8580	ldr	r0, [sp, #68]
8581	# Store result
8582	str	r2, [r0]
8583	str	r3, [r0, #4]
8584	str	r4, [r0, #8]
8585	str	r5, [r0, #12]
8586	str	r6, [r0, #16]
8587	str	r7, [r0, #20]
8588	str	r8, [r0, #24]
8589	str	r9, [r0, #28]
8590	add	sp, sp, #0x50
8591	pop	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
8592	.size	sc_muladd,.-sc_muladd
8593#endif /* WOLFSSL_ARM_ARCH && WOLFSSL_ARM_ARCH < 6 */
8594#endif /* HAVE_ED25519_SIGN */
8595#endif /* HAVE_ED25519 */
8596
8597#endif /* !CURVE25519_SMALL || !ED25519_SMALL */
8598#endif /* HAVE_CURVE25519 || HAVE_ED25519 */
8599#endif /* !__aarch64__ && !WOLFSSL_ARMASM_THUMB2 */
8600#endif /* WOLFSSL_ARMASM */
8601
8602#if defined(__linux__) && defined(__ELF__)
8603.section	.note.GNU-stack,"",%progbits
8604#endif
8605#endif /* !WOLFSSL_ARMASM_INLINE */