luna - wolfssl/wolfcrypt/src/port/arm/thumb2-curve25519.S

   1/* thumb2-curve25519
   2 *
   3 * Copyright (C) 2006-2026 wolfSSL Inc.
   4 *
   5 * This file is part of wolfSSL.
   6 *
   7 * wolfSSL is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 3 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * wolfSSL is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  20 */
  21
  22/* Generated using (from wolfssl):
  23 *   cd ../scripts
  24 *   ruby ./x25519/x25519.rb \
  25 *       thumb2 ../wolfssl/wolfcrypt/src/port/arm/thumb2-curve25519.S
  26 */
  27
  28#include <wolfssl/wolfcrypt/libwolfssl_sources_asm.h>
  29
  30#ifdef WOLFSSL_ARMASM
  31#ifdef WOLFSSL_ARMASM_THUMB2
  32#ifndef WOLFSSL_ARMASM_INLINE
  33	.thumb
  34	.syntax unified
  35#if defined(HAVE_CURVE25519) || defined(HAVE_ED25519)
  36#if !defined(CURVE25519_SMALL) || !defined(ED25519_SMALL)
  37
  38	.text
  39	.align	4
  40	.globl	fe_init
  41	.type	fe_init, %function
  42fe_init:
  43	BX	lr
  44	/* Cycle Count = 4 */
  45	.size	fe_init,.-fe_init
  46	.text
  47	.align	4
  48	.globl	fe_add_sub_op
  49	.type	fe_add_sub_op, %function
  50fe_add_sub_op:
  51	PUSH	{lr}
  52	/* Add-Sub */
  53	LDRD	r4, r5, [r2]
  54	LDRD	r6, r7, [r3]
  55	/*  Add */
  56	ADDS	r8, r4, r6
  57	MOV	r12, #0x0
  58	ADCS	r9, r5, r7
  59	ADC	r12, r12, #0x0
  60	STRD	r8, r9, [r0]
  61	/*  Sub */
  62	SUBS	r10, r4, r6
  63	SBCS	r11, r5, r7
  64	STRD	r10, r11, [r1]
  65	LDRD	r4, r5, [r2, #8]
  66	LDRD	r6, r7, [r3, #8]
  67	/*  Sub */
  68	SBCS	r10, r4, r6
  69	MOV	lr, #0x0
  70	SBCS	r11, r5, r7
  71	ADC	lr, lr, #0x0
  72	STRD	r10, r11, [r1, #8]
  73	/*  Add */
  74	SUBS	r12, r12, #0x1
  75	ADCS	r8, r4, r6
  76	ADCS	r9, r5, r7
  77	STRD	r8, r9, [r0, #8]
  78	LDRD	r4, r5, [r2, #16]
  79	LDRD	r6, r7, [r3, #16]
  80	/*  Add */
  81	ADCS	r8, r4, r6
  82	MOV	r12, #0x0
  83	ADCS	r9, r5, r7
  84	ADC	r12, r12, #0x0
  85	STRD	r8, r9, [r0, #16]
  86	/*  Sub */
  87	SUBS	lr, lr, #0x1
  88	SBCS	r10, r4, r6
  89	SBCS	r11, r5, r7
  90	STRD	r10, r11, [r1, #16]
  91	LDRD	r4, r5, [r2, #24]
  92	LDRD	r6, r7, [r3, #24]
  93	/*  Sub */
  94	SBCS	r10, r4, r6
  95	SBC	r11, r5, r7
  96	/*  Add */
  97	SUBS	r12, r12, #0x1
  98	ADCS	r8, r4, r6
  99	MOV	r12, #0x0
 100	ADCS	r9, r5, r7
 101	ADC	r12, r12, #0x0
 102	/*   Multiply -modulus by overflow */
 103	LSL	r3, r12, #1
 104	MOV	r12, #0x13
 105	ORR	r3, r3, r9, LSR #31
 106	MUL	r12, r3, r12
 107	/*   Add -x*modulus (if overflow) */
 108	LDRD	r4, r5, [r0]
 109	LDRD	r6, r7, [r0, #8]
 110	ADDS	r4, r4, r12
 111	ADCS	r5, r5, #0x0
 112	ADCS	r6, r6, #0x0
 113	ADCS	r7, r7, #0x0
 114	STRD	r4, r5, [r0]
 115	STRD	r6, r7, [r0, #8]
 116	LDRD	r4, r5, [r0, #16]
 117	ADCS	r4, r4, #0x0
 118	ADCS	r5, r5, #0x0
 119	STRD	r4, r5, [r0, #16]
 120	BFC	r9, #31, #1
 121	ADCS	r8, r8, #0x0
 122	ADC	r9, r9, #0x0
 123	STRD	r8, r9, [r0, #24]
 124	/*   Add -modulus on underflow */
 125	MOV	lr, #0x13
 126	AND	lr, lr, r11, ASR #31
 127	LDM	r1, {r4, r5, r6, r7, r8, r9}
 128	SUBS	r4, r4, lr
 129	SBCS	r5, r5, #0x0
 130	SBCS	r6, r6, #0x0
 131	SBCS	r7, r7, #0x0
 132	SBCS	r8, r8, #0x0
 133	SBCS	r9, r9, #0x0
 134	BFC	r11, #31, #1
 135	SBCS	r10, r10, #0x0
 136	SBC	r11, r11, #0x0
 137	STM	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
 138	/* Done Add-Sub */
 139	POP	{pc}
 140	/* Cycle Count = 134 */
 141	.size	fe_add_sub_op,.-fe_add_sub_op
 142	.text
 143	.align	4
 144	.globl	fe_sub_op
 145	.type	fe_sub_op, %function
 146fe_sub_op:
 147	PUSH	{lr}
 148	/* Sub */
 149	LDM	r2!, {r6, r7, r8, r9, r10, r11, r12, lr}
 150	LDM	r1!, {r2, r3, r4, r5}
 151	SUBS	r6, r2, r6
 152	SBCS	r7, r3, r7
 153	SBCS	r8, r4, r8
 154	SBCS	r9, r5, r9
 155	LDM	r1!, {r2, r3, r4, r5}
 156	SBCS	r10, r2, r10
 157	SBCS	r11, r3, r11
 158	SBCS	r12, r4, r12
 159	SBC	lr, r5, lr
 160	MOV	r2, #0x13
 161	AND	r2, r2, lr, ASR #31
 162	SUBS	r6, r6, r2
 163	SBCS	r7, r7, #0x0
 164	SBCS	r8, r8, #0x0
 165	SBCS	r9, r9, #0x0
 166	SBCS	r10, r10, #0x0
 167	SBCS	r11, r11, #0x0
 168	BFC	lr, #31, #1
 169	SBCS	r12, r12, #0x0
 170	SBC	lr, lr, #0x0
 171	STM	r0, {r6, r7, r8, r9, r10, r11, r12, lr}
 172	/* Done Sub */
 173	POP	{pc}
 174	/* Cycle Count = 51 */
 175	.size	fe_sub_op,.-fe_sub_op
 176	.text
 177	.align	4
 178	.globl	fe_sub
 179	.type	fe_sub, %function
 180fe_sub:
 181	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 182	BL	fe_sub_op
 183	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 184	/* Cycle Count = 24 */
 185	.size	fe_sub,.-fe_sub
 186	.text
 187	.align	4
 188	.globl	fe_add_op
 189	.type	fe_add_op, %function
 190fe_add_op:
 191	PUSH	{lr}
 192	/* Add */
 193	LDM	r2!, {r6, r7, r8, r9, r10, r11, r12, lr}
 194	LDM	r1!, {r2, r3, r4, r5}
 195	ADDS	r6, r2, r6
 196	ADCS	r7, r3, r7
 197	ADCS	r8, r4, r8
 198	ADCS	r9, r5, r9
 199	LDM	r1!, {r2, r3, r4, r5}
 200	ADCS	r10, r2, r10
 201	ADCS	r11, r3, r11
 202	ADCS	r12, r4, r12
 203	ADC	lr, r5, lr
 204	MOV	r2, #0x13
 205	AND	r2, r2, lr, ASR #31
 206	ADDS	r6, r6, r2
 207	ADCS	r7, r7, #0x0
 208	ADCS	r8, r8, #0x0
 209	ADCS	r9, r9, #0x0
 210	ADCS	r10, r10, #0x0
 211	ADCS	r11, r11, #0x0
 212	BFC	lr, #31, #1
 213	ADCS	r12, r12, #0x0
 214	ADC	lr, lr, #0x0
 215	STM	r0, {r6, r7, r8, r9, r10, r11, r12, lr}
 216	/* Done Add */
 217	POP	{pc}
 218	/* Cycle Count = 51 */
 219	.size	fe_add_op,.-fe_add_op
 220	.text
 221	.align	4
 222	.globl	fe_add
 223	.type	fe_add, %function
 224fe_add:
 225	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 226	BL	fe_add_op
 227	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
 228	/* Cycle Count = 24 */
 229	.size	fe_add,.-fe_add
 230#if defined(HAVE_ED25519) || defined(WOLFSSL_CURVE25519_USE_ED25519)
 231	.text
 232	.align	4
 233	.globl	fe_frombytes
 234	.type	fe_frombytes, %function
 235fe_frombytes:
 236	PUSH	{r4, r5, r6, r7, r8, r9, lr}
 237	LDR	r2, [r1]
 238	LDR	r3, [r1, #4]
 239	LDR	r4, [r1, #8]
 240	LDR	r5, [r1, #12]
 241	LDR	r6, [r1, #16]
 242	LDR	r7, [r1, #20]
 243	LDR	r8, [r1, #24]
 244	LDR	r9, [r1, #28]
 245	BFC	r9, #31, #1
 246	STR	r2, [r0]
 247	STR	r3, [r0, #4]
 248	STR	r4, [r0, #8]
 249	STR	r5, [r0, #12]
 250	STR	r6, [r0, #16]
 251	STR	r7, [r0, #20]
 252	STR	r8, [r0, #24]
 253	STR	r9, [r0, #28]
 254	POP	{r4, r5, r6, r7, r8, r9, pc}
 255	/* Cycle Count = 49 */
 256	.size	fe_frombytes,.-fe_frombytes
 257	.text
 258	.align	4
 259	.globl	fe_tobytes
 260	.type	fe_tobytes, %function
 261fe_tobytes:
 262	PUSH	{r4, r5, r6, r7, r8, r9, r10, lr}
 263	LDM	r1, {r2, r3, r4, r5, r6, r7, r8, r9}
 264	ADDS	r10, r2, #0x13
 265	ADCS	r10, r3, #0x0
 266	ADCS	r10, r4, #0x0
 267	ADCS	r10, r5, #0x0
 268	ADCS	r10, r6, #0x0
 269	ADCS	r10, r7, #0x0
 270	ADCS	r10, r8, #0x0
 271	ADC	r10, r9, #0x0
 272	ASR	r10, r10, #31
 273	AND	r10, r10, #0x13
 274	ADDS	r2, r2, r10
 275	ADCS	r3, r3, #0x0
 276	ADCS	r4, r4, #0x0
 277	ADCS	r5, r5, #0x0
 278	ADCS	r6, r6, #0x0
 279	ADCS	r7, r7, #0x0
 280	ADCS	r8, r8, #0x0
 281	ADC	r9, r9, #0x0
 282	BFC	r9, #31, #1
 283	STR	r2, [r0]
 284	STR	r3, [r0, #4]
 285	STR	r4, [r0, #8]
 286	STR	r5, [r0, #12]
 287	STR	r6, [r0, #16]
 288	STR	r7, [r0, #20]
 289	STR	r8, [r0, #24]
 290	STR	r9, [r0, #28]
 291	POP	{r4, r5, r6, r7, r8, r9, r10, pc}
 292	/* Cycle Count = 62 */
 293	.size	fe_tobytes,.-fe_tobytes
 294	.text
 295	.align	4
 296	.globl	fe_1
 297	.type	fe_1, %function
 298fe_1:
 299	PUSH	{r4, r5, r6, r7, r8, r9, lr}
 300	/* Set one */
 301	MOV	r2, #0x1
 302	MOV	r3, #0x0
 303	MOV	r4, #0x0
 304	MOV	r5, #0x0
 305	MOV	r6, #0x0
 306	MOV	r7, #0x0
 307	MOV	r8, #0x0
 308	MOV	r9, #0x0
 309	STM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
 310	POP	{r4, r5, r6, r7, r8, r9, pc}
 311	/* Cycle Count = 33 */
 312	.size	fe_1,.-fe_1
 313	.text
 314	.align	4
 315	.globl	fe_0
 316	.type	fe_0, %function
 317fe_0:
 318	PUSH	{r4, r5, r6, r7, r8, r9, lr}
 319	/* Set zero */
 320	MOV	r2, #0x0
 321	MOV	r3, #0x0
 322	MOV	r4, #0x0
 323	MOV	r5, #0x0
 324	MOV	r6, #0x0
 325	MOV	r7, #0x0
 326	MOV	r8, #0x0
 327	MOV	r9, #0x0
 328	STM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
 329	POP	{r4, r5, r6, r7, r8, r9, pc}
 330	/* Cycle Count = 33 */
 331	.size	fe_0,.-fe_0
 332	.text
 333	.align	4
 334	.globl	fe_copy
 335	.type	fe_copy, %function
 336fe_copy:
 337	PUSH	{r4, r5, lr}
 338	/* Copy */
 339	LDRD	r2, r3, [r1]
 340	LDRD	r4, r5, [r1, #8]
 341	STRD	r2, r3, [r0]
 342	STRD	r4, r5, [r0, #8]
 343	LDRD	r2, r3, [r1, #16]
 344	LDRD	r4, r5, [r1, #24]
 345	STRD	r2, r3, [r0, #16]
 346	STRD	r4, r5, [r0, #24]
 347	POP	{r4, r5, pc}
 348	/* Cycle Count = 32 */
 349	.size	fe_copy,.-fe_copy
 350	.text
 351	.align	4
 352	.globl	fe_neg
 353	.type	fe_neg, %function
 354fe_neg:
 355	PUSH	{r4, r5, r6, r7, lr}
 356	MVN	r7, #0x0
 357	MVN	r6, #0x12
 358	LDM	r1!, {r2, r3, r4, r5}
 359	SUBS	r2, r6, r2
 360	SBCS	r3, r7, r3
 361	SBCS	r4, r7, r4
 362	SBCS	r5, r7, r5
 363	STM	r0!, {r2, r3, r4, r5}
 364	MVN	r6, #0x80000000
 365	LDM	r1!, {r2, r3, r4, r5}
 366	SBCS	r2, r7, r2
 367	SBCS	r3, r7, r3
 368	SBCS	r4, r7, r4
 369	SBC	r5, r6, r5
 370	STM	r0!, {r2, r3, r4, r5}
 371	POP	{r4, r5, r6, r7, pc}
 372	/* Cycle Count = 43 */
 373	.size	fe_neg,.-fe_neg
 374	.text
 375	.align	4
 376	.globl	fe_isnonzero
 377	.type	fe_isnonzero, %function
 378fe_isnonzero:
 379	PUSH	{r4, r5, r6, r7, r8, r9, r10, lr}
 380	LDM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
 381	ADDS	r1, r2, #0x13
 382	ADCS	r1, r3, #0x0
 383	ADCS	r1, r4, #0x0
 384	ADCS	r1, r5, #0x0
 385	ADCS	r1, r6, #0x0
 386	ADCS	r1, r7, #0x0
 387	ADCS	r1, r8, #0x0
 388	ADC	r1, r9, #0x0
 389	ASR	r1, r1, #31
 390	AND	r1, r1, #0x13
 391	ADDS	r2, r2, r1
 392	ADCS	r3, r3, #0x0
 393	ADCS	r4, r4, #0x0
 394	ADCS	r5, r5, #0x0
 395	ADCS	r6, r6, #0x0
 396	ADCS	r7, r7, #0x0
 397	ADCS	r8, r8, #0x0
 398	ADC	r9, r9, #0x0
 399	BFC	r9, #31, #1
 400	ORR	r2, r2, r3
 401	ORR	r4, r4, r5
 402	ORR	r6, r6, r7
 403	ORR	r8, r8, r9
 404	ORR	r4, r4, r6
 405	ORR	r2, r2, r8
 406	ORR	r0, r2, r4
 407	POP	{r4, r5, r6, r7, r8, r9, r10, pc}
 408	/* Cycle Count = 53 */
 409	.size	fe_isnonzero,.-fe_isnonzero
 410	.text
 411	.align	4
 412	.globl	fe_isnegative
 413	.type	fe_isnegative, %function
 414fe_isnegative:
 415	PUSH	{r4, r5, lr}
 416	LDM	r0!, {r2, r3, r4, r5}
 417	ADDS	r1, r2, #0x13
 418	ADCS	r1, r3, #0x0
 419	ADCS	r1, r4, #0x0
 420	ADCS	r1, r5, #0x0
 421	LDM	r0, {r2, r3, r4, r5}
 422	ADCS	r1, r2, #0x0
 423	ADCS	r1, r3, #0x0
 424	ADCS	r1, r4, #0x0
 425	LDR	r2, [r0, #-16]
 426	ADC	r1, r5, #0x0
 427	AND	r0, r2, #0x1
 428	LSR	r1, r1, #31
 429	EOR	r0, r0, r1
 430	POP	{r4, r5, pc}
 431	/* Cycle Count = 31 */
 432	.size	fe_isnegative,.-fe_isnegative
 433#if defined(HAVE_ED25519_MAKE_KEY) || defined(HAVE_ED25519_SIGN) || defined(WOLFSSL_CURVE25519_USE_ED25519)
 434#ifndef WC_NO_CACHE_RESISTANT
 435	.text
 436	.align	4
 437	.globl	fe_cmov_table
 438	.type	fe_cmov_table, %function
 439fe_cmov_table:
 440	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
 441	SXTB	r2, r2
 442	SBFX	r3, r2, #7, #1
 443	EOR	r12, r2, r3
 444	SUB	r12, r12, r3
 445	MOV	r4, #0x1
 446	MOV	r5, #0x0
 447	MOV	r6, #0x1
 448	MOV	r7, #0x0
 449	MOV	r8, #0x0
 450	MOV	r9, #0x0
 451	MOV	r3, #0x80000000
 452	ROR	r3, r3, #31
 453	ROR	r3, r3, r12
 454	ASR	r3, r3, #31
 455	LDRD	r10, r11, [r1]
 456	EOR	r10, r10, r4
 457	EOR	r11, r11, r5
 458	AND	r10, r10, r3
 459	AND	r11, r11, r3
 460	EOR	r4, r4, r10
 461	EOR	r5, r5, r11
 462	LDRD	r10, r11, [r1, #32]
 463	EOR	r10, r10, r6
 464	EOR	r11, r11, r7
 465	AND	r10, r10, r3
 466	AND	r11, r11, r3
 467	EOR	r6, r6, r10
 468	EOR	r7, r7, r11
 469	LDRD	r10, r11, [r1, #64]
 470	EOR	r10, r10, r8
 471	EOR	r11, r11, r9
 472	AND	r10, r10, r3
 473	AND	r11, r11, r3
 474	EOR	r8, r8, r10
 475	EOR	r9, r9, r11
 476	ADD	r1, r1, #0x60
 477	MOV	r3, #0x80000000
 478	ROR	r3, r3, #30
 479	ROR	r3, r3, r12
 480	ASR	r3, r3, #31
 481	LDRD	r10, r11, [r1]
 482	EOR	r10, r10, r4
 483	EOR	r11, r11, r5
 484	AND	r10, r10, r3
 485	AND	r11, r11, r3
 486	EOR	r4, r4, r10
 487	EOR	r5, r5, r11
 488	LDRD	r10, r11, [r1, #32]
 489	EOR	r10, r10, r6
 490	EOR	r11, r11, r7
 491	AND	r10, r10, r3
 492	AND	r11, r11, r3
 493	EOR	r6, r6, r10
 494	EOR	r7, r7, r11
 495	LDRD	r10, r11, [r1, #64]
 496	EOR	r10, r10, r8
 497	EOR	r11, r11, r9
 498	AND	r10, r10, r3
 499	AND	r11, r11, r3
 500	EOR	r8, r8, r10
 501	EOR	r9, r9, r11
 502	ADD	r1, r1, #0x60
 503	MOV	r3, #0x80000000
 504	ROR	r3, r3, #29
 505	ROR	r3, r3, r12
 506	ASR	r3, r3, #31
 507	LDRD	r10, r11, [r1]
 508	EOR	r10, r10, r4
 509	EOR	r11, r11, r5
 510	AND	r10, r10, r3
 511	AND	r11, r11, r3
 512	EOR	r4, r4, r10
 513	EOR	r5, r5, r11
 514	LDRD	r10, r11, [r1, #32]
 515	EOR	r10, r10, r6
 516	EOR	r11, r11, r7
 517	AND	r10, r10, r3
 518	AND	r11, r11, r3
 519	EOR	r6, r6, r10
 520	EOR	r7, r7, r11
 521	LDRD	r10, r11, [r1, #64]
 522	EOR	r10, r10, r8
 523	EOR	r11, r11, r9
 524	AND	r10, r10, r3
 525	AND	r11, r11, r3
 526	EOR	r8, r8, r10
 527	EOR	r9, r9, r11
 528	ADD	r1, r1, #0x60
 529	MOV	r3, #0x80000000
 530	ROR	r3, r3, #28
 531	ROR	r3, r3, r12
 532	ASR	r3, r3, #31
 533	LDRD	r10, r11, [r1]
 534	EOR	r10, r10, r4
 535	EOR	r11, r11, r5
 536	AND	r10, r10, r3
 537	AND	r11, r11, r3
 538	EOR	r4, r4, r10
 539	EOR	r5, r5, r11
 540	LDRD	r10, r11, [r1, #32]
 541	EOR	r10, r10, r6
 542	EOR	r11, r11, r7
 543	AND	r10, r10, r3
 544	AND	r11, r11, r3
 545	EOR	r6, r6, r10
 546	EOR	r7, r7, r11
 547	LDRD	r10, r11, [r1, #64]
 548	EOR	r10, r10, r8
 549	EOR	r11, r11, r9
 550	AND	r10, r10, r3
 551	AND	r11, r11, r3
 552	EOR	r8, r8, r10
 553	EOR	r9, r9, r11
 554	ADD	r1, r1, #0x60
 555	MOV	r3, #0x80000000
 556	ROR	r3, r3, #27
 557	ROR	r3, r3, r12
 558	ASR	r3, r3, #31
 559	LDRD	r10, r11, [r1]
 560	EOR	r10, r10, r4
 561	EOR	r11, r11, r5
 562	AND	r10, r10, r3
 563	AND	r11, r11, r3
 564	EOR	r4, r4, r10
 565	EOR	r5, r5, r11
 566	LDRD	r10, r11, [r1, #32]
 567	EOR	r10, r10, r6
 568	EOR	r11, r11, r7
 569	AND	r10, r10, r3
 570	AND	r11, r11, r3
 571	EOR	r6, r6, r10
 572	EOR	r7, r7, r11
 573	LDRD	r10, r11, [r1, #64]
 574	EOR	r10, r10, r8
 575	EOR	r11, r11, r9
 576	AND	r10, r10, r3
 577	AND	r11, r11, r3
 578	EOR	r8, r8, r10
 579	EOR	r9, r9, r11
 580	ADD	r1, r1, #0x60
 581	MOV	r3, #0x80000000
 582	ROR	r3, r3, #26
 583	ROR	r3, r3, r12
 584	ASR	r3, r3, #31
 585	LDRD	r10, r11, [r1]
 586	EOR	r10, r10, r4
 587	EOR	r11, r11, r5
 588	AND	r10, r10, r3
 589	AND	r11, r11, r3
 590	EOR	r4, r4, r10
 591	EOR	r5, r5, r11
 592	LDRD	r10, r11, [r1, #32]
 593	EOR	r10, r10, r6
 594	EOR	r11, r11, r7
 595	AND	r10, r10, r3
 596	AND	r11, r11, r3
 597	EOR	r6, r6, r10
 598	EOR	r7, r7, r11
 599	LDRD	r10, r11, [r1, #64]
 600	EOR	r10, r10, r8
 601	EOR	r11, r11, r9
 602	AND	r10, r10, r3
 603	AND	r11, r11, r3
 604	EOR	r8, r8, r10
 605	EOR	r9, r9, r11
 606	ADD	r1, r1, #0x60
 607	MOV	r3, #0x80000000
 608	ROR	r3, r3, #25
 609	ROR	r3, r3, r12
 610	ASR	r3, r3, #31
 611	LDRD	r10, r11, [r1]
 612	EOR	r10, r10, r4
 613	EOR	r11, r11, r5
 614	AND	r10, r10, r3
 615	AND	r11, r11, r3
 616	EOR	r4, r4, r10
 617	EOR	r5, r5, r11
 618	LDRD	r10, r11, [r1, #32]
 619	EOR	r10, r10, r6
 620	EOR	r11, r11, r7
 621	AND	r10, r10, r3
 622	AND	r11, r11, r3
 623	EOR	r6, r6, r10
 624	EOR	r7, r7, r11
 625	LDRD	r10, r11, [r1, #64]
 626	EOR	r10, r10, r8
 627	EOR	r11, r11, r9
 628	AND	r10, r10, r3
 629	AND	r11, r11, r3
 630	EOR	r8, r8, r10
 631	EOR	r9, r9, r11
 632	ADD	r1, r1, #0x60
 633	MOV	r3, #0x80000000
 634	ROR	r3, r3, #24
 635	ROR	r3, r3, r12
 636	ASR	r3, r3, #31
 637	LDRD	r10, r11, [r1]
 638	EOR	r10, r10, r4
 639	EOR	r11, r11, r5
 640	AND	r10, r10, r3
 641	AND	r11, r11, r3
 642	EOR	r4, r4, r10
 643	EOR	r5, r5, r11
 644	LDRD	r10, r11, [r1, #32]
 645	EOR	r10, r10, r6
 646	EOR	r11, r11, r7
 647	AND	r10, r10, r3
 648	AND	r11, r11, r3
 649	EOR	r6, r6, r10
 650	EOR	r7, r7, r11
 651	LDRD	r10, r11, [r1, #64]
 652	EOR	r10, r10, r8
 653	EOR	r11, r11, r9
 654	AND	r10, r10, r3
 655	AND	r11, r11, r3
 656	EOR	r8, r8, r10
 657	EOR	r9, r9, r11
 658	SUB	r1, r1, #0x2a0
 659	MVN	r10, #0x12
 660	MVN	r11, #0x0
 661	SUBS	r10, r10, r8
 662	SBCS	r11, r11, r9
 663	SBC	lr, lr, lr
 664	ASR	r12, r2, #31
 665	EOR	r3, r4, r6
 666	AND	r3, r3, r12
 667	EOR	r4, r4, r3
 668	EOR	r6, r6, r3
 669	EOR	r3, r5, r7
 670	AND	r3, r3, r12
 671	EOR	r5, r5, r3
 672	EOR	r7, r7, r3
 673	EOR	r10, r10, r8
 674	AND	r10, r10, r12
 675	EOR	r8, r8, r10
 676	EOR	r11, r11, r9
 677	AND	r11, r11, r12
 678	EOR	r9, r9, r11
 679	STRD	r4, r5, [r0]
 680	STRD	r6, r7, [r0, #32]
 681	STRD	r8, r9, [r0, #64]
 682	SBFX	r3, r2, #7, #1
 683	EOR	r12, r2, r3
 684	SUB	r12, r12, r3
 685	MOV	r4, #0x0
 686	MOV	r5, #0x0
 687	MOV	r6, #0x0
 688	MOV	r7, #0x0
 689	MOV	r8, #0x0
 690	MOV	r9, #0x0
 691	MOV	r3, #0x80000000
 692	ROR	r3, r3, #31
 693	ROR	r3, r3, r12
 694	ASR	r3, r3, #31
 695	LDRD	r10, r11, [r1, #8]
 696	EOR	r10, r10, r4
 697	EOR	r11, r11, r5
 698	AND	r10, r10, r3
 699	AND	r11, r11, r3
 700	EOR	r4, r4, r10
 701	EOR	r5, r5, r11
 702	LDRD	r10, r11, [r1, #40]
 703	EOR	r10, r10, r6
 704	EOR	r11, r11, r7
 705	AND	r10, r10, r3
 706	AND	r11, r11, r3
 707	EOR	r6, r6, r10
 708	EOR	r7, r7, r11
 709	LDRD	r10, r11, [r1, #72]
 710	EOR	r10, r10, r8
 711	EOR	r11, r11, r9
 712	AND	r10, r10, r3
 713	AND	r11, r11, r3
 714	EOR	r8, r8, r10
 715	EOR	r9, r9, r11
 716	ADD	r1, r1, #0x60
 717	MOV	r3, #0x80000000
 718	ROR	r3, r3, #30
 719	ROR	r3, r3, r12
 720	ASR	r3, r3, #31
 721	LDRD	r10, r11, [r1, #8]
 722	EOR	r10, r10, r4
 723	EOR	r11, r11, r5
 724	AND	r10, r10, r3
 725	AND	r11, r11, r3
 726	EOR	r4, r4, r10
 727	EOR	r5, r5, r11
 728	LDRD	r10, r11, [r1, #40]
 729	EOR	r10, r10, r6
 730	EOR	r11, r11, r7
 731	AND	r10, r10, r3
 732	AND	r11, r11, r3
 733	EOR	r6, r6, r10
 734	EOR	r7, r7, r11
 735	LDRD	r10, r11, [r1, #72]
 736	EOR	r10, r10, r8
 737	EOR	r11, r11, r9
 738	AND	r10, r10, r3
 739	AND	r11, r11, r3
 740	EOR	r8, r8, r10
 741	EOR	r9, r9, r11
 742	ADD	r1, r1, #0x60
 743	MOV	r3, #0x80000000
 744	ROR	r3, r3, #29
 745	ROR	r3, r3, r12
 746	ASR	r3, r3, #31
 747	LDRD	r10, r11, [r1, #8]
 748	EOR	r10, r10, r4
 749	EOR	r11, r11, r5
 750	AND	r10, r10, r3
 751	AND	r11, r11, r3
 752	EOR	r4, r4, r10
 753	EOR	r5, r5, r11
 754	LDRD	r10, r11, [r1, #40]
 755	EOR	r10, r10, r6
 756	EOR	r11, r11, r7
 757	AND	r10, r10, r3
 758	AND	r11, r11, r3
 759	EOR	r6, r6, r10
 760	EOR	r7, r7, r11
 761	LDRD	r10, r11, [r1, #72]
 762	EOR	r10, r10, r8
 763	EOR	r11, r11, r9
 764	AND	r10, r10, r3
 765	AND	r11, r11, r3
 766	EOR	r8, r8, r10
 767	EOR	r9, r9, r11
 768	ADD	r1, r1, #0x60
 769	MOV	r3, #0x80000000
 770	ROR	r3, r3, #28
 771	ROR	r3, r3, r12
 772	ASR	r3, r3, #31
 773	LDRD	r10, r11, [r1, #8]
 774	EOR	r10, r10, r4
 775	EOR	r11, r11, r5
 776	AND	r10, r10, r3
 777	AND	r11, r11, r3
 778	EOR	r4, r4, r10
 779	EOR	r5, r5, r11
 780	LDRD	r10, r11, [r1, #40]
 781	EOR	r10, r10, r6
 782	EOR	r11, r11, r7
 783	AND	r10, r10, r3
 784	AND	r11, r11, r3
 785	EOR	r6, r6, r10
 786	EOR	r7, r7, r11
 787	LDRD	r10, r11, [r1, #72]
 788	EOR	r10, r10, r8
 789	EOR	r11, r11, r9
 790	AND	r10, r10, r3
 791	AND	r11, r11, r3
 792	EOR	r8, r8, r10
 793	EOR	r9, r9, r11
 794	ADD	r1, r1, #0x60
 795	MOV	r3, #0x80000000
 796	ROR	r3, r3, #27
 797	ROR	r3, r3, r12
 798	ASR	r3, r3, #31
 799	LDRD	r10, r11, [r1, #8]
 800	EOR	r10, r10, r4
 801	EOR	r11, r11, r5
 802	AND	r10, r10, r3
 803	AND	r11, r11, r3
 804	EOR	r4, r4, r10
 805	EOR	r5, r5, r11
 806	LDRD	r10, r11, [r1, #40]
 807	EOR	r10, r10, r6
 808	EOR	r11, r11, r7
 809	AND	r10, r10, r3
 810	AND	r11, r11, r3
 811	EOR	r6, r6, r10
 812	EOR	r7, r7, r11
 813	LDRD	r10, r11, [r1, #72]
 814	EOR	r10, r10, r8
 815	EOR	r11, r11, r9
 816	AND	r10, r10, r3
 817	AND	r11, r11, r3
 818	EOR	r8, r8, r10
 819	EOR	r9, r9, r11
 820	ADD	r1, r1, #0x60
 821	MOV	r3, #0x80000000
 822	ROR	r3, r3, #26
 823	ROR	r3, r3, r12
 824	ASR	r3, r3, #31
 825	LDRD	r10, r11, [r1, #8]
 826	EOR	r10, r10, r4
 827	EOR	r11, r11, r5
 828	AND	r10, r10, r3
 829	AND	r11, r11, r3
 830	EOR	r4, r4, r10
 831	EOR	r5, r5, r11
 832	LDRD	r10, r11, [r1, #40]
 833	EOR	r10, r10, r6
 834	EOR	r11, r11, r7
 835	AND	r10, r10, r3
 836	AND	r11, r11, r3
 837	EOR	r6, r6, r10
 838	EOR	r7, r7, r11
 839	LDRD	r10, r11, [r1, #72]
 840	EOR	r10, r10, r8
 841	EOR	r11, r11, r9
 842	AND	r10, r10, r3
 843	AND	r11, r11, r3
 844	EOR	r8, r8, r10
 845	EOR	r9, r9, r11
 846	ADD	r1, r1, #0x60
 847	MOV	r3, #0x80000000
 848	ROR	r3, r3, #25
 849	ROR	r3, r3, r12
 850	ASR	r3, r3, #31
 851	LDRD	r10, r11, [r1, #8]
 852	EOR	r10, r10, r4
 853	EOR	r11, r11, r5
 854	AND	r10, r10, r3
 855	AND	r11, r11, r3
 856	EOR	r4, r4, r10
 857	EOR	r5, r5, r11
 858	LDRD	r10, r11, [r1, #40]
 859	EOR	r10, r10, r6
 860	EOR	r11, r11, r7
 861	AND	r10, r10, r3
 862	AND	r11, r11, r3
 863	EOR	r6, r6, r10
 864	EOR	r7, r7, r11
 865	LDRD	r10, r11, [r1, #72]
 866	EOR	r10, r10, r8
 867	EOR	r11, r11, r9
 868	AND	r10, r10, r3
 869	AND	r11, r11, r3
 870	EOR	r8, r8, r10
 871	EOR	r9, r9, r11
 872	ADD	r1, r1, #0x60
 873	MOV	r3, #0x80000000
 874	ROR	r3, r3, #24
 875	ROR	r3, r3, r12
 876	ASR	r3, r3, #31
 877	LDRD	r10, r11, [r1, #8]
 878	EOR	r10, r10, r4
 879	EOR	r11, r11, r5
 880	AND	r10, r10, r3
 881	AND	r11, r11, r3
 882	EOR	r4, r4, r10
 883	EOR	r5, r5, r11
 884	LDRD	r10, r11, [r1, #40]
 885	EOR	r10, r10, r6
 886	EOR	r11, r11, r7
 887	AND	r10, r10, r3
 888	AND	r11, r11, r3
 889	EOR	r6, r6, r10
 890	EOR	r7, r7, r11
 891	LDRD	r10, r11, [r1, #72]
 892	EOR	r10, r10, r8
 893	EOR	r11, r11, r9
 894	AND	r10, r10, r3
 895	AND	r11, r11, r3
 896	EOR	r8, r8, r10
 897	EOR	r9, r9, r11
 898	SUB	r1, r1, #0x2a0
 899	MVN	r10, #0x0
 900	MVN	r11, #0x0
 901	RSBS	lr, lr, #0x0
 902	SBCS	r10, r10, r8
 903	SBCS	r11, r11, r9
 904	SBC	lr, lr, lr
 905	ASR	r12, r2, #31
 906	EOR	r3, r4, r6
 907	AND	r3, r3, r12
 908	EOR	r4, r4, r3
 909	EOR	r6, r6, r3
 910	EOR	r3, r5, r7
 911	AND	r3, r3, r12
 912	EOR	r5, r5, r3
 913	EOR	r7, r7, r3
 914	EOR	r10, r10, r8
 915	AND	r10, r10, r12
 916	EOR	r8, r8, r10
 917	EOR	r11, r11, r9
 918	AND	r11, r11, r12
 919	EOR	r9, r9, r11
 920	STRD	r4, r5, [r0, #8]
 921	STRD	r6, r7, [r0, #40]
 922	STRD	r8, r9, [r0, #72]
 923	SBFX	r3, r2, #7, #1
 924	EOR	r12, r2, r3
 925	SUB	r12, r12, r3
 926	MOV	r4, #0x0
 927	MOV	r5, #0x0
 928	MOV	r6, #0x0
 929	MOV	r7, #0x0
 930	MOV	r8, #0x0
 931	MOV	r9, #0x0
 932	MOV	r3, #0x80000000
 933	ROR	r3, r3, #31
 934	ROR	r3, r3, r12
 935	ASR	r3, r3, #31
 936	LDRD	r10, r11, [r1, #16]
 937	EOR	r10, r10, r4
 938	EOR	r11, r11, r5
 939	AND	r10, r10, r3
 940	AND	r11, r11, r3
 941	EOR	r4, r4, r10
 942	EOR	r5, r5, r11
 943	LDRD	r10, r11, [r1, #48]
 944	EOR	r10, r10, r6
 945	EOR	r11, r11, r7
 946	AND	r10, r10, r3
 947	AND	r11, r11, r3
 948	EOR	r6, r6, r10
 949	EOR	r7, r7, r11
 950	LDRD	r10, r11, [r1, #80]
 951	EOR	r10, r10, r8
 952	EOR	r11, r11, r9
 953	AND	r10, r10, r3
 954	AND	r11, r11, r3
 955	EOR	r8, r8, r10
 956	EOR	r9, r9, r11
 957	ADD	r1, r1, #0x60
 958	MOV	r3, #0x80000000
 959	ROR	r3, r3, #30
 960	ROR	r3, r3, r12
 961	ASR	r3, r3, #31
 962	LDRD	r10, r11, [r1, #16]
 963	EOR	r10, r10, r4
 964	EOR	r11, r11, r5
 965	AND	r10, r10, r3
 966	AND	r11, r11, r3
 967	EOR	r4, r4, r10
 968	EOR	r5, r5, r11
 969	LDRD	r10, r11, [r1, #48]
 970	EOR	r10, r10, r6
 971	EOR	r11, r11, r7
 972	AND	r10, r10, r3
 973	AND	r11, r11, r3
 974	EOR	r6, r6, r10
 975	EOR	r7, r7, r11
 976	LDRD	r10, r11, [r1, #80]
 977	EOR	r10, r10, r8
 978	EOR	r11, r11, r9
 979	AND	r10, r10, r3
 980	AND	r11, r11, r3
 981	EOR	r8, r8, r10
 982	EOR	r9, r9, r11
 983	ADD	r1, r1, #0x60
 984	MOV	r3, #0x80000000
 985	ROR	r3, r3, #29
 986	ROR	r3, r3, r12
 987	ASR	r3, r3, #31
 988	LDRD	r10, r11, [r1, #16]
 989	EOR	r10, r10, r4
 990	EOR	r11, r11, r5
 991	AND	r10, r10, r3
 992	AND	r11, r11, r3
 993	EOR	r4, r4, r10
 994	EOR	r5, r5, r11
 995	LDRD	r10, r11, [r1, #48]
 996	EOR	r10, r10, r6
 997	EOR	r11, r11, r7
 998	AND	r10, r10, r3
 999	AND	r11, r11, r3
1000	EOR	r6, r6, r10
1001	EOR	r7, r7, r11
1002	LDRD	r10, r11, [r1, #80]
1003	EOR	r10, r10, r8
1004	EOR	r11, r11, r9
1005	AND	r10, r10, r3
1006	AND	r11, r11, r3
1007	EOR	r8, r8, r10
1008	EOR	r9, r9, r11
1009	ADD	r1, r1, #0x60
1010	MOV	r3, #0x80000000
1011	ROR	r3, r3, #28
1012	ROR	r3, r3, r12
1013	ASR	r3, r3, #31
1014	LDRD	r10, r11, [r1, #16]
1015	EOR	r10, r10, r4
1016	EOR	r11, r11, r5
1017	AND	r10, r10, r3
1018	AND	r11, r11, r3
1019	EOR	r4, r4, r10
1020	EOR	r5, r5, r11
1021	LDRD	r10, r11, [r1, #48]
1022	EOR	r10, r10, r6
1023	EOR	r11, r11, r7
1024	AND	r10, r10, r3
1025	AND	r11, r11, r3
1026	EOR	r6, r6, r10
1027	EOR	r7, r7, r11
1028	LDRD	r10, r11, [r1, #80]
1029	EOR	r10, r10, r8
1030	EOR	r11, r11, r9
1031	AND	r10, r10, r3
1032	AND	r11, r11, r3
1033	EOR	r8, r8, r10
1034	EOR	r9, r9, r11
1035	ADD	r1, r1, #0x60
1036	MOV	r3, #0x80000000
1037	ROR	r3, r3, #27
1038	ROR	r3, r3, r12
1039	ASR	r3, r3, #31
1040	LDRD	r10, r11, [r1, #16]
1041	EOR	r10, r10, r4
1042	EOR	r11, r11, r5
1043	AND	r10, r10, r3
1044	AND	r11, r11, r3
1045	EOR	r4, r4, r10
1046	EOR	r5, r5, r11
1047	LDRD	r10, r11, [r1, #48]
1048	EOR	r10, r10, r6
1049	EOR	r11, r11, r7
1050	AND	r10, r10, r3
1051	AND	r11, r11, r3
1052	EOR	r6, r6, r10
1053	EOR	r7, r7, r11
1054	LDRD	r10, r11, [r1, #80]
1055	EOR	r10, r10, r8
1056	EOR	r11, r11, r9
1057	AND	r10, r10, r3
1058	AND	r11, r11, r3
1059	EOR	r8, r8, r10
1060	EOR	r9, r9, r11
1061	ADD	r1, r1, #0x60
1062	MOV	r3, #0x80000000
1063	ROR	r3, r3, #26
1064	ROR	r3, r3, r12
1065	ASR	r3, r3, #31
1066	LDRD	r10, r11, [r1, #16]
1067	EOR	r10, r10, r4
1068	EOR	r11, r11, r5
1069	AND	r10, r10, r3
1070	AND	r11, r11, r3
1071	EOR	r4, r4, r10
1072	EOR	r5, r5, r11
1073	LDRD	r10, r11, [r1, #48]
1074	EOR	r10, r10, r6
1075	EOR	r11, r11, r7
1076	AND	r10, r10, r3
1077	AND	r11, r11, r3
1078	EOR	r6, r6, r10
1079	EOR	r7, r7, r11
1080	LDRD	r10, r11, [r1, #80]
1081	EOR	r10, r10, r8
1082	EOR	r11, r11, r9
1083	AND	r10, r10, r3
1084	AND	r11, r11, r3
1085	EOR	r8, r8, r10
1086	EOR	r9, r9, r11
1087	ADD	r1, r1, #0x60
1088	MOV	r3, #0x80000000
1089	ROR	r3, r3, #25
1090	ROR	r3, r3, r12
1091	ASR	r3, r3, #31
1092	LDRD	r10, r11, [r1, #16]
1093	EOR	r10, r10, r4
1094	EOR	r11, r11, r5
1095	AND	r10, r10, r3
1096	AND	r11, r11, r3
1097	EOR	r4, r4, r10
1098	EOR	r5, r5, r11
1099	LDRD	r10, r11, [r1, #48]
1100	EOR	r10, r10, r6
1101	EOR	r11, r11, r7
1102	AND	r10, r10, r3
1103	AND	r11, r11, r3
1104	EOR	r6, r6, r10
1105	EOR	r7, r7, r11
1106	LDRD	r10, r11, [r1, #80]
1107	EOR	r10, r10, r8
1108	EOR	r11, r11, r9
1109	AND	r10, r10, r3
1110	AND	r11, r11, r3
1111	EOR	r8, r8, r10
1112	EOR	r9, r9, r11
1113	ADD	r1, r1, #0x60
1114	MOV	r3, #0x80000000
1115	ROR	r3, r3, #24
1116	ROR	r3, r3, r12
1117	ASR	r3, r3, #31
1118	LDRD	r10, r11, [r1, #16]
1119	EOR	r10, r10, r4
1120	EOR	r11, r11, r5
1121	AND	r10, r10, r3
1122	AND	r11, r11, r3
1123	EOR	r4, r4, r10
1124	EOR	r5, r5, r11
1125	LDRD	r10, r11, [r1, #48]
1126	EOR	r10, r10, r6
1127	EOR	r11, r11, r7
1128	AND	r10, r10, r3
1129	AND	r11, r11, r3
1130	EOR	r6, r6, r10
1131	EOR	r7, r7, r11
1132	LDRD	r10, r11, [r1, #80]
1133	EOR	r10, r10, r8
1134	EOR	r11, r11, r9
1135	AND	r10, r10, r3
1136	AND	r11, r11, r3
1137	EOR	r8, r8, r10
1138	EOR	r9, r9, r11
1139	SUB	r1, r1, #0x2a0
1140	MVN	r10, #0x0
1141	MVN	r11, #0x0
1142	RSBS	lr, lr, #0x0
1143	SBCS	r10, r10, r8
1144	SBCS	r11, r11, r9
1145	SBC	lr, lr, lr
1146	ASR	r12, r2, #31
1147	EOR	r3, r4, r6
1148	AND	r3, r3, r12
1149	EOR	r4, r4, r3
1150	EOR	r6, r6, r3
1151	EOR	r3, r5, r7
1152	AND	r3, r3, r12
1153	EOR	r5, r5, r3
1154	EOR	r7, r7, r3
1155	EOR	r10, r10, r8
1156	AND	r10, r10, r12
1157	EOR	r8, r8, r10
1158	EOR	r11, r11, r9
1159	AND	r11, r11, r12
1160	EOR	r9, r9, r11
1161	STRD	r4, r5, [r0, #16]
1162	STRD	r6, r7, [r0, #48]
1163	STRD	r8, r9, [r0, #80]
1164	SBFX	r3, r2, #7, #1
1165	EOR	r12, r2, r3
1166	SUB	r12, r12, r3
1167	MOV	r4, #0x0
1168	MOV	r5, #0x0
1169	MOV	r6, #0x0
1170	MOV	r7, #0x0
1171	MOV	r8, #0x0
1172	MOV	r9, #0x0
1173	MOV	r3, #0x80000000
1174	ROR	r3, r3, #31
1175	ROR	r3, r3, r12
1176	ASR	r3, r3, #31
1177	LDRD	r10, r11, [r1, #24]
1178	EOR	r10, r10, r4
1179	EOR	r11, r11, r5
1180	AND	r10, r10, r3
1181	AND	r11, r11, r3
1182	EOR	r4, r4, r10
1183	EOR	r5, r5, r11
1184	LDRD	r10, r11, [r1, #56]
1185	EOR	r10, r10, r6
1186	EOR	r11, r11, r7
1187	AND	r10, r10, r3
1188	AND	r11, r11, r3
1189	EOR	r6, r6, r10
1190	EOR	r7, r7, r11
1191	LDRD	r10, r11, [r1, #88]
1192	EOR	r10, r10, r8
1193	EOR	r11, r11, r9
1194	AND	r10, r10, r3
1195	AND	r11, r11, r3
1196	EOR	r8, r8, r10
1197	EOR	r9, r9, r11
1198	ADD	r1, r1, #0x60
1199	MOV	r3, #0x80000000
1200	ROR	r3, r3, #30
1201	ROR	r3, r3, r12
1202	ASR	r3, r3, #31
1203	LDRD	r10, r11, [r1, #24]
1204	EOR	r10, r10, r4
1205	EOR	r11, r11, r5
1206	AND	r10, r10, r3
1207	AND	r11, r11, r3
1208	EOR	r4, r4, r10
1209	EOR	r5, r5, r11
1210	LDRD	r10, r11, [r1, #56]
1211	EOR	r10, r10, r6
1212	EOR	r11, r11, r7
1213	AND	r10, r10, r3
1214	AND	r11, r11, r3
1215	EOR	r6, r6, r10
1216	EOR	r7, r7, r11
1217	LDRD	r10, r11, [r1, #88]
1218	EOR	r10, r10, r8
1219	EOR	r11, r11, r9
1220	AND	r10, r10, r3
1221	AND	r11, r11, r3
1222	EOR	r8, r8, r10
1223	EOR	r9, r9, r11
1224	ADD	r1, r1, #0x60
1225	MOV	r3, #0x80000000
1226	ROR	r3, r3, #29
1227	ROR	r3, r3, r12
1228	ASR	r3, r3, #31
1229	LDRD	r10, r11, [r1, #24]
1230	EOR	r10, r10, r4
1231	EOR	r11, r11, r5
1232	AND	r10, r10, r3
1233	AND	r11, r11, r3
1234	EOR	r4, r4, r10
1235	EOR	r5, r5, r11
1236	LDRD	r10, r11, [r1, #56]
1237	EOR	r10, r10, r6
1238	EOR	r11, r11, r7
1239	AND	r10, r10, r3
1240	AND	r11, r11, r3
1241	EOR	r6, r6, r10
1242	EOR	r7, r7, r11
1243	LDRD	r10, r11, [r1, #88]
1244	EOR	r10, r10, r8
1245	EOR	r11, r11, r9
1246	AND	r10, r10, r3
1247	AND	r11, r11, r3
1248	EOR	r8, r8, r10
1249	EOR	r9, r9, r11
1250	ADD	r1, r1, #0x60
1251	MOV	r3, #0x80000000
1252	ROR	r3, r3, #28
1253	ROR	r3, r3, r12
1254	ASR	r3, r3, #31
1255	LDRD	r10, r11, [r1, #24]
1256	EOR	r10, r10, r4
1257	EOR	r11, r11, r5
1258	AND	r10, r10, r3
1259	AND	r11, r11, r3
1260	EOR	r4, r4, r10
1261	EOR	r5, r5, r11
1262	LDRD	r10, r11, [r1, #56]
1263	EOR	r10, r10, r6
1264	EOR	r11, r11, r7
1265	AND	r10, r10, r3
1266	AND	r11, r11, r3
1267	EOR	r6, r6, r10
1268	EOR	r7, r7, r11
1269	LDRD	r10, r11, [r1, #88]
1270	EOR	r10, r10, r8
1271	EOR	r11, r11, r9
1272	AND	r10, r10, r3
1273	AND	r11, r11, r3
1274	EOR	r8, r8, r10
1275	EOR	r9, r9, r11
1276	ADD	r1, r1, #0x60
1277	MOV	r3, #0x80000000
1278	ROR	r3, r3, #27
1279	ROR	r3, r3, r12
1280	ASR	r3, r3, #31
1281	LDRD	r10, r11, [r1, #24]
1282	EOR	r10, r10, r4
1283	EOR	r11, r11, r5
1284	AND	r10, r10, r3
1285	AND	r11, r11, r3
1286	EOR	r4, r4, r10
1287	EOR	r5, r5, r11
1288	LDRD	r10, r11, [r1, #56]
1289	EOR	r10, r10, r6
1290	EOR	r11, r11, r7
1291	AND	r10, r10, r3
1292	AND	r11, r11, r3
1293	EOR	r6, r6, r10
1294	EOR	r7, r7, r11
1295	LDRD	r10, r11, [r1, #88]
1296	EOR	r10, r10, r8
1297	EOR	r11, r11, r9
1298	AND	r10, r10, r3
1299	AND	r11, r11, r3
1300	EOR	r8, r8, r10
1301	EOR	r9, r9, r11
1302	ADD	r1, r1, #0x60
1303	MOV	r3, #0x80000000
1304	ROR	r3, r3, #26
1305	ROR	r3, r3, r12
1306	ASR	r3, r3, #31
1307	LDRD	r10, r11, [r1, #24]
1308	EOR	r10, r10, r4
1309	EOR	r11, r11, r5
1310	AND	r10, r10, r3
1311	AND	r11, r11, r3
1312	EOR	r4, r4, r10
1313	EOR	r5, r5, r11
1314	LDRD	r10, r11, [r1, #56]
1315	EOR	r10, r10, r6
1316	EOR	r11, r11, r7
1317	AND	r10, r10, r3
1318	AND	r11, r11, r3
1319	EOR	r6, r6, r10
1320	EOR	r7, r7, r11
1321	LDRD	r10, r11, [r1, #88]
1322	EOR	r10, r10, r8
1323	EOR	r11, r11, r9
1324	AND	r10, r10, r3
1325	AND	r11, r11, r3
1326	EOR	r8, r8, r10
1327	EOR	r9, r9, r11
1328	ADD	r1, r1, #0x60
1329	MOV	r3, #0x80000000
1330	ROR	r3, r3, #25
1331	ROR	r3, r3, r12
1332	ASR	r3, r3, #31
1333	LDRD	r10, r11, [r1, #24]
1334	EOR	r10, r10, r4
1335	EOR	r11, r11, r5
1336	AND	r10, r10, r3
1337	AND	r11, r11, r3
1338	EOR	r4, r4, r10
1339	EOR	r5, r5, r11
1340	LDRD	r10, r11, [r1, #56]
1341	EOR	r10, r10, r6
1342	EOR	r11, r11, r7
1343	AND	r10, r10, r3
1344	AND	r11, r11, r3
1345	EOR	r6, r6, r10
1346	EOR	r7, r7, r11
1347	LDRD	r10, r11, [r1, #88]
1348	EOR	r10, r10, r8
1349	EOR	r11, r11, r9
1350	AND	r10, r10, r3
1351	AND	r11, r11, r3
1352	EOR	r8, r8, r10
1353	EOR	r9, r9, r11
1354	ADD	r1, r1, #0x60
1355	MOV	r3, #0x80000000
1356	ROR	r3, r3, #24
1357	ROR	r3, r3, r12
1358	ASR	r3, r3, #31
1359	LDRD	r10, r11, [r1, #24]
1360	EOR	r10, r10, r4
1361	EOR	r11, r11, r5
1362	AND	r10, r10, r3
1363	AND	r11, r11, r3
1364	EOR	r4, r4, r10
1365	EOR	r5, r5, r11
1366	LDRD	r10, r11, [r1, #56]
1367	EOR	r10, r10, r6
1368	EOR	r11, r11, r7
1369	AND	r10, r10, r3
1370	AND	r11, r11, r3
1371	EOR	r6, r6, r10
1372	EOR	r7, r7, r11
1373	LDRD	r10, r11, [r1, #88]
1374	EOR	r10, r10, r8
1375	EOR	r11, r11, r9
1376	AND	r10, r10, r3
1377	AND	r11, r11, r3
1378	EOR	r8, r8, r10
1379	EOR	r9, r9, r11
1380	SUB	r1, r1, #0x2a0
1381	MVN	r10, #0x0
1382	MVN	r11, #0x80000000
1383	RSBS	lr, lr, #0x0
1384	SBCS	r10, r10, r8
1385	SBC	r11, r11, r9
1386	ASR	r12, r2, #31
1387	EOR	r3, r4, r6
1388	AND	r3, r3, r12
1389	EOR	r4, r4, r3
1390	EOR	r6, r6, r3
1391	EOR	r3, r5, r7
1392	AND	r3, r3, r12
1393	EOR	r5, r5, r3
1394	EOR	r7, r7, r3
1395	EOR	r10, r10, r8
1396	AND	r10, r10, r12
1397	EOR	r8, r8, r10
1398	EOR	r11, r11, r9
1399	AND	r11, r11, r12
1400	EOR	r9, r9, r11
1401	STRD	r4, r5, [r0, #24]
1402	STRD	r6, r7, [r0, #56]
1403	STRD	r8, r9, [r0, #88]
1404	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
1405	/* Cycle Count = 1195 */
1406	.size	fe_cmov_table,.-fe_cmov_table
1407#else
1408	.text
1409	.align	4
1410	.globl	fe_cmov_table
1411	.type	fe_cmov_table, %function
1412fe_cmov_table:
1413	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
1414	SXTB	r2, r2
1415	SBFX	r3, r2, #7, #1
1416	EOR	r2, r2, r3
1417	SUB	r2, r2, r3
1418	CLZ	lr, r2
1419	LSL	lr, lr, #26
1420	ASR	lr, lr, #31
1421	MVN	lr, lr
1422	ADD	r2, r2, lr
1423	MOV	r12, #0x60
1424	MUL	r2, r2, r12
1425	ADD	r1, r1, r2
1426	LDM	r1!, {r4, r5, r6, r7, r8, r9, r10, r11}
1427	AND	r4, r4, lr
1428	AND	r5, r5, lr
1429	AND	r6, r6, lr
1430	AND	r7, r7, lr
1431	AND	r8, r8, lr
1432	AND	r9, r9, lr
1433	AND	r10, r10, lr
1434	AND	r11, r11, lr
1435	MVN	r12, lr
1436	SUB	r4, r4, r12
1437	MOV	r12, #0x20
1438	AND	r12, r12, r3
1439	ADD	r0, r0, r12
1440	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
1441	SUB	r0, r0, r12
1442	LDM	r1!, {r4, r5, r6, r7, r8, r9, r10, r11}
1443	AND	r4, r4, lr
1444	AND	r5, r5, lr
1445	AND	r6, r6, lr
1446	AND	r7, r7, lr
1447	AND	r8, r8, lr
1448	AND	r9, r9, lr
1449	AND	r10, r10, lr
1450	AND	r11, r11, lr
1451	MVN	r12, lr
1452	SUB	r4, r4, r12
1453	MOV	r12, #0x20
1454	BIC	r12, r12, r3
1455	ADD	r0, r0, r12
1456	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
1457	SUB	r0, r0, r12
1458	ADD	r0, r0, #0x40
1459	LDM	r1!, {r4, r5, r6, r7}
1460	MVN	r12, #0x12
1461	SUBS	r8, r12, r4
1462	SBCS	r9, r3, r5
1463	SBCS	r10, r3, r6
1464	SBCS	r11, r3, r7
1465	BIC	r4, r4, r3
1466	BIC	r5, r5, r3
1467	BIC	r6, r6, r3
1468	BIC	r7, r7, r3
1469	AND	r8, r8, r3
1470	AND	r9, r9, r3
1471	AND	r10, r10, r3
1472	AND	r11, r11, r3
1473	ORR	r4, r4, r8
1474	ORR	r5, r5, r9
1475	ORR	r6, r6, r10
1476	ORR	r7, r7, r11
1477	AND	r4, r4, lr
1478	AND	r5, r5, lr
1479	AND	r6, r6, lr
1480	AND	r7, r7, lr
1481	STM	r0!, {r4, r5, r6, r7}
1482	LDM	r1!, {r4, r5, r6, r7}
1483	MVN	r12, #0x80000000
1484	SBCS	r8, r3, r4
1485	SBCS	r9, r3, r5
1486	SBCS	r10, r3, r6
1487	SBC	r11, r12, r7
1488	BIC	r4, r4, r3
1489	BIC	r5, r5, r3
1490	BIC	r6, r6, r3
1491	BIC	r7, r7, r3
1492	AND	r8, r8, r3
1493	AND	r9, r9, r3
1494	AND	r10, r10, r3
1495	AND	r11, r11, r3
1496	ORR	r4, r4, r8
1497	ORR	r5, r5, r9
1498	ORR	r6, r6, r10
1499	ORR	r7, r7, r11
1500	AND	r4, r4, lr
1501	AND	r5, r5, lr
1502	AND	r6, r6, lr
1503	AND	r7, r7, lr
1504	STM	r0!, {r4, r5, r6, r7}
1505	SUB	r1, r1, r2
1506	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
1507	/* Cycle Count = 160 */
1508	.size	fe_cmov_table,.-fe_cmov_table
1509#endif /* WC_NO_CACHE_RESISTANT */
1510#endif /* HAVE_ED25519_MAKE_KEY || HAVE_ED25519_SIGN || WOLFSSL_CURVE25519_USE_ED25519 */
1511#endif /* HAVE_ED25519 || WOLFSSL_CURVE25519_USE_ED25519 */
1512#ifdef WOLFSSL_ARM_ARCH_7M
1513	.text
1514	.align	4
1515	.globl	fe_mul_op
1516	.type	fe_mul_op, %function
1517fe_mul_op:
1518	PUSH	{lr}
1519	SUB	sp, sp, #0x28
1520	STR	r0, [sp, #36]
1521	MOV	r0, #0x0
1522	LDR	r12, [r1]
1523	/* A[0] * B[0] */
1524	LDR	lr, [r2]
1525	UMULL	r3, r4, r12, lr
1526	/* A[0] * B[2] */
1527	LDR	lr, [r2, #8]
1528	UMULL	r5, r6, r12, lr
1529	/* A[0] * B[4] */
1530	LDR	lr, [r2, #16]
1531	UMULL	r7, r8, r12, lr
1532	/* A[0] * B[6] */
1533	LDR	lr, [r2, #24]
1534	UMULL	r9, r10, r12, lr
1535	STR	r3, [sp]
1536	/* A[0] * B[1] */
1537	LDR	lr, [r2, #4]
1538	MOV	r11, r0
1539	UMLAL	r4, r11, r12, lr
1540	ADDS	r5, r5, r11
1541	/* A[0] * B[3] */
1542	LDR	lr, [r2, #12]
1543	ADCS	r6, r6, #0x0
1544	ADC	r11, r0, #0x0
1545	UMLAL	r6, r11, r12, lr
1546	ADDS	r7, r7, r11
1547	/* A[0] * B[5] */
1548	LDR	lr, [r2, #20]
1549	ADCS	r8, r8, #0x0
1550	ADC	r11, r0, #0x0
1551	UMLAL	r8, r11, r12, lr
1552	ADDS	r9, r9, r11
1553	/* A[0] * B[7] */
1554	LDR	lr, [r2, #28]
1555	ADCS	r10, r10, #0x0
1556	ADC	r3, r0, #0x0
1557	UMLAL	r10, r3, r12, lr
1558	/* A[1] * B[0] */
1559	LDR	r12, [r1, #4]
1560	LDR	lr, [r2]
1561	MOV	r11, #0x0
1562	UMLAL	r4, r11, r12, lr
1563	STR	r4, [sp, #4]
1564	ADDS	r5, r5, r11
1565	/* A[1] * B[1] */
1566	LDR	lr, [r2, #4]
1567	ADC	r11, r0, #0x0
1568	UMLAL	r5, r11, r12, lr
1569	ADDS	r6, r6, r11
1570	/* A[1] * B[2] */
1571	LDR	lr, [r2, #8]
1572	ADC	r11, r0, #0x0
1573	UMLAL	r6, r11, r12, lr
1574	ADDS	r7, r7, r11
1575	/* A[1] * B[3] */
1576	LDR	lr, [r2, #12]
1577	ADC	r11, r0, #0x0
1578	UMLAL	r7, r11, r12, lr
1579	ADDS	r8, r8, r11
1580	/* A[1] * B[4] */
1581	LDR	lr, [r2, #16]
1582	ADC	r11, r0, #0x0
1583	UMLAL	r8, r11, r12, lr
1584	ADDS	r9, r9, r11
1585	/* A[1] * B[5] */
1586	LDR	lr, [r2, #20]
1587	ADC	r11, r0, #0x0
1588	UMLAL	r9, r11, r12, lr
1589	ADDS	r10, r10, r11
1590	/* A[1] * B[6] */
1591	LDR	lr, [r2, #24]
1592	ADC	r11, r0, #0x0
1593	UMLAL	r10, r11, r12, lr
1594	ADDS	r3, r3, r11
1595	/* A[1] * B[7] */
1596	LDR	lr, [r2, #28]
1597	ADC	r4, r0, #0x0
1598	UMLAL	r3, r4, r12, lr
1599	/* A[2] * B[0] */
1600	LDR	r12, [r1, #8]
1601	LDR	lr, [r2]
1602	MOV	r11, #0x0
1603	UMLAL	r5, r11, r12, lr
1604	STR	r5, [sp, #8]
1605	ADDS	r6, r6, r11
1606	/* A[2] * B[1] */
1607	LDR	lr, [r2, #4]
1608	ADC	r11, r0, #0x0
1609	UMLAL	r6, r11, r12, lr
1610	ADDS	r7, r7, r11
1611	/* A[2] * B[2] */
1612	LDR	lr, [r2, #8]
1613	ADC	r11, r0, #0x0
1614	UMLAL	r7, r11, r12, lr
1615	ADDS	r8, r8, r11
1616	/* A[2] * B[3] */
1617	LDR	lr, [r2, #12]
1618	ADC	r11, r0, #0x0
1619	UMLAL	r8, r11, r12, lr
1620	ADDS	r9, r9, r11
1621	/* A[2] * B[4] */
1622	LDR	lr, [r2, #16]
1623	ADC	r11, r0, #0x0
1624	UMLAL	r9, r11, r12, lr
1625	ADDS	r10, r10, r11
1626	/* A[2] * B[5] */
1627	LDR	lr, [r2, #20]
1628	ADC	r11, r0, #0x0
1629	UMLAL	r10, r11, r12, lr
1630	ADDS	r3, r3, r11
1631	/* A[2] * B[6] */
1632	LDR	lr, [r2, #24]
1633	ADC	r11, r0, #0x0
1634	UMLAL	r3, r11, r12, lr
1635	ADDS	r4, r4, r11
1636	/* A[2] * B[7] */
1637	LDR	lr, [r2, #28]
1638	ADC	r5, r0, #0x0
1639	UMLAL	r4, r5, r12, lr
1640	/* A[3] * B[0] */
1641	LDR	r12, [r1, #12]
1642	LDR	lr, [r2]
1643	MOV	r11, #0x0
1644	UMLAL	r6, r11, r12, lr
1645	STR	r6, [sp, #12]
1646	ADDS	r7, r7, r11
1647	/* A[3] * B[1] */
1648	LDR	lr, [r2, #4]
1649	ADC	r11, r0, #0x0
1650	UMLAL	r7, r11, r12, lr
1651	ADDS	r8, r8, r11
1652	/* A[3] * B[2] */
1653	LDR	lr, [r2, #8]
1654	ADC	r11, r0, #0x0
1655	UMLAL	r8, r11, r12, lr
1656	ADDS	r9, r9, r11
1657	/* A[3] * B[3] */
1658	LDR	lr, [r2, #12]
1659	ADC	r11, r0, #0x0
1660	UMLAL	r9, r11, r12, lr
1661	ADDS	r10, r10, r11
1662	/* A[3] * B[4] */
1663	LDR	lr, [r2, #16]
1664	ADC	r11, r0, #0x0
1665	UMLAL	r10, r11, r12, lr
1666	ADDS	r3, r3, r11
1667	/* A[3] * B[5] */
1668	LDR	lr, [r2, #20]
1669	ADC	r11, r0, #0x0
1670	UMLAL	r3, r11, r12, lr
1671	ADDS	r4, r4, r11
1672	/* A[3] * B[6] */
1673	LDR	lr, [r2, #24]
1674	ADC	r11, r0, #0x0
1675	UMLAL	r4, r11, r12, lr
1676	ADDS	r5, r5, r11
1677	/* A[3] * B[7] */
1678	LDR	lr, [r2, #28]
1679	ADC	r6, r0, #0x0
1680	UMLAL	r5, r6, r12, lr
1681	/* A[4] * B[0] */
1682	LDR	r12, [r1, #16]
1683	LDR	lr, [r2]
1684	MOV	r11, #0x0
1685	UMLAL	r7, r11, r12, lr
1686	STR	r7, [sp, #16]
1687	ADDS	r8, r8, r11
1688	/* A[4] * B[1] */
1689	LDR	lr, [r2, #4]
1690	ADC	r11, r0, #0x0
1691	UMLAL	r8, r11, r12, lr
1692	ADDS	r9, r9, r11
1693	/* A[4] * B[2] */
1694	LDR	lr, [r2, #8]
1695	ADC	r11, r0, #0x0
1696	UMLAL	r9, r11, r12, lr
1697	ADDS	r10, r10, r11
1698	/* A[4] * B[3] */
1699	LDR	lr, [r2, #12]
1700	ADC	r11, r0, #0x0
1701	UMLAL	r10, r11, r12, lr
1702	ADDS	r3, r3, r11
1703	/* A[4] * B[4] */
1704	LDR	lr, [r2, #16]
1705	ADC	r11, r0, #0x0
1706	UMLAL	r3, r11, r12, lr
1707	ADDS	r4, r4, r11
1708	/* A[4] * B[5] */
1709	LDR	lr, [r2, #20]
1710	ADC	r11, r0, #0x0
1711	UMLAL	r4, r11, r12, lr
1712	ADDS	r5, r5, r11
1713	/* A[4] * B[6] */
1714	LDR	lr, [r2, #24]
1715	ADC	r11, r0, #0x0
1716	UMLAL	r5, r11, r12, lr
1717	ADDS	r6, r6, r11
1718	/* A[4] * B[7] */
1719	LDR	lr, [r2, #28]
1720	ADC	r7, r0, #0x0
1721	UMLAL	r6, r7, r12, lr
1722	/* A[5] * B[0] */
1723	LDR	r12, [r1, #20]
1724	LDR	lr, [r2]
1725	MOV	r11, #0x0
1726	UMLAL	r8, r11, r12, lr
1727	STR	r8, [sp, #20]
1728	ADDS	r9, r9, r11
1729	/* A[5] * B[1] */
1730	LDR	lr, [r2, #4]
1731	ADC	r11, r0, #0x0
1732	UMLAL	r9, r11, r12, lr
1733	ADDS	r10, r10, r11
1734	/* A[5] * B[2] */
1735	LDR	lr, [r2, #8]
1736	ADC	r11, r0, #0x0
1737	UMLAL	r10, r11, r12, lr
1738	ADDS	r3, r3, r11
1739	/* A[5] * B[3] */
1740	LDR	lr, [r2, #12]
1741	ADC	r11, r0, #0x0
1742	UMLAL	r3, r11, r12, lr
1743	ADDS	r4, r4, r11
1744	/* A[5] * B[4] */
1745	LDR	lr, [r2, #16]
1746	ADC	r11, r0, #0x0
1747	UMLAL	r4, r11, r12, lr
1748	ADDS	r5, r5, r11
1749	/* A[5] * B[5] */
1750	LDR	lr, [r2, #20]
1751	ADC	r11, r0, #0x0
1752	UMLAL	r5, r11, r12, lr
1753	ADDS	r6, r6, r11
1754	/* A[5] * B[6] */
1755	LDR	lr, [r2, #24]
1756	ADC	r11, r0, #0x0
1757	UMLAL	r6, r11, r12, lr
1758	ADDS	r7, r7, r11
1759	/* A[5] * B[7] */
1760	LDR	lr, [r2, #28]
1761	ADC	r8, r0, #0x0
1762	UMLAL	r7, r8, r12, lr
1763	/* A[6] * B[0] */
1764	LDR	r12, [r1, #24]
1765	LDR	lr, [r2]
1766	MOV	r11, #0x0
1767	UMLAL	r9, r11, r12, lr
1768	STR	r9, [sp, #24]
1769	ADDS	r10, r10, r11
1770	/* A[6] * B[1] */
1771	LDR	lr, [r2, #4]
1772	ADC	r11, r0, #0x0
1773	UMLAL	r10, r11, r12, lr
1774	ADDS	r3, r3, r11
1775	/* A[6] * B[2] */
1776	LDR	lr, [r2, #8]
1777	ADC	r11, r0, #0x0
1778	UMLAL	r3, r11, r12, lr
1779	ADDS	r4, r4, r11
1780	/* A[6] * B[3] */
1781	LDR	lr, [r2, #12]
1782	ADC	r11, r0, #0x0
1783	UMLAL	r4, r11, r12, lr
1784	ADDS	r5, r5, r11
1785	/* A[6] * B[4] */
1786	LDR	lr, [r2, #16]
1787	ADC	r11, r0, #0x0
1788	UMLAL	r5, r11, r12, lr
1789	ADDS	r6, r6, r11
1790	/* A[6] * B[5] */
1791	LDR	lr, [r2, #20]
1792	ADC	r11, r0, #0x0
1793	UMLAL	r6, r11, r12, lr
1794	ADDS	r7, r7, r11
1795	/* A[6] * B[6] */
1796	LDR	lr, [r2, #24]
1797	ADC	r11, r0, #0x0
1798	UMLAL	r7, r11, r12, lr
1799	ADDS	r8, r8, r11
1800	/* A[6] * B[7] */
1801	LDR	lr, [r2, #28]
1802	ADC	r9, r0, #0x0
1803	UMLAL	r8, r9, r12, lr
1804	/* A[7] * B[0] */
1805	LDR	r12, [r1, #28]
1806	LDR	lr, [r2]
1807	MOV	r11, #0x0
1808	UMLAL	r10, r11, r12, lr
1809	STR	r10, [sp, #28]
1810	ADDS	r3, r3, r11
1811	/* A[7] * B[1] */
1812	LDR	lr, [r2, #4]
1813	ADC	r11, r0, #0x0
1814	UMLAL	r3, r11, r12, lr
1815	ADDS	r4, r4, r11
1816	/* A[7] * B[2] */
1817	LDR	lr, [r2, #8]
1818	ADC	r11, r0, #0x0
1819	UMLAL	r4, r11, r12, lr
1820	ADDS	r5, r5, r11
1821	/* A[7] * B[3] */
1822	LDR	lr, [r2, #12]
1823	ADC	r11, r0, #0x0
1824	UMLAL	r5, r11, r12, lr
1825	ADDS	r6, r6, r11
1826	/* A[7] * B[4] */
1827	LDR	lr, [r2, #16]
1828	ADC	r11, r0, #0x0
1829	UMLAL	r6, r11, r12, lr
1830	ADDS	r7, r7, r11
1831	/* A[7] * B[5] */
1832	LDR	lr, [r2, #20]
1833	ADC	r11, r0, #0x0
1834	UMLAL	r7, r11, r12, lr
1835	ADDS	r8, r8, r11
1836	/* A[7] * B[6] */
1837	LDR	lr, [r2, #24]
1838	ADC	r11, r0, #0x0
1839	UMLAL	r8, r11, r12, lr
1840	ADDS	r9, r9, r11
1841	/* A[7] * B[7] */
1842	LDR	lr, [r2, #28]
1843	ADC	r10, r0, #0x0
1844	UMLAL	r9, r10, r12, lr
1845	/* Reduce */
1846	LDR	r2, [sp, #28]
1847	MOV	lr, sp
1848	MOV	r12, #0x26
1849	UMULL	r10, r11, r10, r12
1850	ADDS	r10, r10, r2
1851	ADC	r11, r11, #0x0
1852	MOV	r12, #0x13
1853	LSL	r11, r11, #1
1854	ORR	r11, r11, r10, LSR #31
1855	MUL	r11, r11, r12
1856	LDM	lr!, {r1, r2}
1857	MOV	r12, #0x26
1858	ADDS	r1, r1, r11
1859	ADC	r11, r0, #0x0
1860	UMLAL	r1, r11, r3, r12
1861	ADDS	r2, r2, r11
1862	ADC	r11, r0, #0x0
1863	UMLAL	r2, r11, r4, r12
1864	LDM	lr!, {r3, r4}
1865	ADDS	r3, r3, r11
1866	ADC	r11, r0, #0x0
1867	UMLAL	r3, r11, r5, r12
1868	ADDS	r4, r4, r11
1869	ADC	r11, r0, #0x0
1870	UMLAL	r4, r11, r6, r12
1871	LDM	lr!, {r5, r6}
1872	ADDS	r5, r5, r11
1873	ADC	r11, r0, #0x0
1874	UMLAL	r5, r11, r7, r12
1875	ADDS	r6, r6, r11
1876	ADC	r11, r0, #0x0
1877	UMLAL	r6, r11, r8, r12
1878	LDM	lr!, {r7, r8}
1879	ADDS	r7, r7, r11
1880	ADC	r11, r0, #0x0
1881	UMLAL	r7, r11, r9, r12
1882	BFC	r10, #31, #1
1883	ADDS	r8, r10, r11
1884	/* Store */
1885	LDR	r0, [sp, #36]
1886	STM	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
1887	ADD	sp, sp, #0x28
1888	POP	{pc}
1889	/* Cycle Count = 406 */
1890	.size	fe_mul_op,.-fe_mul_op
1891#else
1892	.text
1893	.align	4
1894	.globl	fe_mul_op
1895	.type	fe_mul_op, %function
1896fe_mul_op:
1897	PUSH	{lr}
1898	SUB	sp, sp, #0x2c
1899	STRD	r0, r1, [sp, #36]
1900	MOV	lr, r2
1901	LDM	r1, {r0, r1, r2, r3}
1902	LDM	lr!, {r4, r5, r6}
1903	UMULL	r10, r11, r0, r4
1904	UMULL	r12, r7, r1, r4
1905	UMAAL	r11, r12, r0, r5
1906	UMULL	r8, r9, r2, r4
1907	UMAAL	r12, r8, r1, r5
1908	UMAAL	r12, r7, r0, r6
1909	UMAAL	r8, r9, r3, r4
1910	STM	sp, {r10, r11, r12}
1911	UMAAL	r7, r8, r2, r5
1912	LDM	lr!, {r4}
1913	UMULL	r10, r11, r1, r6
1914	UMAAL	r8, r9, r2, r6
1915	UMAAL	r7, r10, r0, r4
1916	UMAAL	r8, r11, r3, r5
1917	STR	r7, [sp, #12]
1918	UMAAL	r8, r10, r1, r4
1919	UMAAL	r9, r11, r3, r6
1920	UMAAL	r9, r10, r2, r4
1921	UMAAL	r10, r11, r3, r4
1922	LDM	lr, {r4, r5, r6, r7}
1923	MOV	r12, #0x0
1924	UMLAL	r8, r12, r0, r4
1925	UMAAL	r9, r12, r1, r4
1926	UMAAL	r10, r12, r2, r4
1927	UMAAL	r11, r12, r3, r4
1928	MOV	r4, #0x0
1929	UMLAL	r9, r4, r0, r5
1930	UMAAL	r10, r4, r1, r5
1931	UMAAL	r11, r4, r2, r5
1932	UMAAL	r12, r4, r3, r5
1933	MOV	r5, #0x0
1934	UMLAL	r10, r5, r0, r6
1935	UMAAL	r11, r5, r1, r6
1936	UMAAL	r12, r5, r2, r6
1937	UMAAL	r4, r5, r3, r6
1938	MOV	r6, #0x0
1939	UMLAL	r11, r6, r0, r7
1940	LDR	r0, [sp, #40]
1941	UMAAL	r12, r6, r1, r7
1942	ADD	r0, r0, #0x10
1943	UMAAL	r4, r6, r2, r7
1944	SUB	lr, lr, #0x10
1945	UMAAL	r5, r6, r3, r7
1946	LDM	r0, {r0, r1, r2, r3}
1947	STR	r6, [sp, #32]
1948	LDM	lr!, {r6}
1949	MOV	r7, #0x0
1950	UMLAL	r8, r7, r0, r6
1951	UMAAL	r9, r7, r1, r6
1952	STR	r8, [sp, #16]
1953	UMAAL	r10, r7, r2, r6
1954	UMAAL	r11, r7, r3, r6
1955	LDM	lr!, {r6}
1956	MOV	r8, #0x0
1957	UMLAL	r9, r8, r0, r6
1958	UMAAL	r10, r8, r1, r6
1959	STR	r9, [sp, #20]
1960	UMAAL	r11, r8, r2, r6
1961	UMAAL	r12, r8, r3, r6
1962	LDM	lr!, {r6}
1963	MOV	r9, #0x0
1964	UMLAL	r10, r9, r0, r6
1965	UMAAL	r11, r9, r1, r6
1966	STR	r10, [sp, #24]
1967	UMAAL	r12, r9, r2, r6
1968	UMAAL	r4, r9, r3, r6
1969	LDM	lr!, {r6}
1970	MOV	r10, #0x0
1971	UMLAL	r11, r10, r0, r6
1972	UMAAL	r12, r10, r1, r6
1973	STR	r11, [sp, #28]
1974	UMAAL	r4, r10, r2, r6
1975	UMAAL	r5, r10, r3, r6
1976	LDM	lr!, {r11}
1977	UMAAL	r12, r7, r0, r11
1978	UMAAL	r4, r7, r1, r11
1979	LDR	r6, [sp, #32]
1980	UMAAL	r5, r7, r2, r11
1981	UMAAL	r6, r7, r3, r11
1982	LDM	lr!, {r11}
1983	UMAAL	r4, r8, r0, r11
1984	UMAAL	r5, r8, r1, r11
1985	UMAAL	r6, r8, r2, r11
1986	UMAAL	r7, r8, r3, r11
1987	LDM	lr, {r11, lr}
1988	UMAAL	r5, r9, r0, r11
1989	UMAAL	r6, r10, r0, lr
1990	UMAAL	r6, r9, r1, r11
1991	UMAAL	r7, r10, r1, lr
1992	UMAAL	r7, r9, r2, r11
1993	UMAAL	r8, r10, r2, lr
1994	UMAAL	r8, r9, r3, r11
1995	UMAAL	r9, r10, r3, lr
1996	/* Reduce */
1997	LDR	r0, [sp, #28]
1998	MOV	lr, #0x25
1999	UMAAL	r10, r0, r10, lr
2000	MOV	lr, #0x13
2001	LSL	r0, r0, #1
2002	ORR	r0, r0, r10, LSR #31
2003	MUL	r11, r0, lr
2004	POP	{r0, r1, r2}
2005	MOV	lr, #0x26
2006	UMAAL	r0, r11, r12, lr
2007	UMAAL	r1, r11, r4, lr
2008	UMAAL	r2, r11, r5, lr
2009	POP	{r3, r4, r5}
2010	UMAAL	r3, r11, r6, lr
2011	UMAAL	r4, r11, r7, lr
2012	UMAAL	r5, r11, r8, lr
2013	POP	{r6}
2014	BFC	r10, #31, #1
2015	UMAAL	r6, r11, r9, lr
2016	ADD	r7, r10, r11
2017	LDR	lr, [sp, #8]
2018	/* Store */
2019	STM	lr, {r0, r1, r2, r3, r4, r5, r6, r7}
2020	ADD	sp, sp, #0x10
2021	POP	{pc}
2022	/* Cycle Count = 239 */
2023	.size	fe_mul_op,.-fe_mul_op
2024#endif /* WOLFSSL_ARM_ARCH_7M */
2025	.text
2026	.align	4
2027	.globl	fe_mul
2028	.type	fe_mul, %function
2029fe_mul:
2030	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2031	BL	fe_mul_op
2032	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2033	/* Cycle Count = 24 */
2034	.size	fe_mul,.-fe_mul
2035#ifdef WOLFSSL_ARM_ARCH_7M
2036	.text
2037	.align	4
2038	.globl	fe_sq_op
2039	.type	fe_sq_op, %function
2040fe_sq_op:
2041	PUSH	{lr}
2042	SUB	sp, sp, #0x44
2043	STR	r0, [sp, #64]
2044	/* Square */
2045	MOV	r0, #0x0
2046	LDR	r12, [r1]
2047	/* A[0] * A[1] */
2048	LDR	lr, [r1, #4]
2049	UMULL	r4, r5, r12, lr
2050	/* A[0] * A[3] */
2051	LDR	lr, [r1, #12]
2052	UMULL	r6, r7, r12, lr
2053	/* A[0] * A[5] */
2054	LDR	lr, [r1, #20]
2055	UMULL	r8, r9, r12, lr
2056	/* A[0] * A[7] */
2057	LDR	lr, [r1, #28]
2058	UMULL	r10, r3, r12, lr
2059	/* A[0] * A[2] */
2060	LDR	lr, [r1, #8]
2061	MOV	r11, #0x0
2062	UMLAL	r5, r11, r12, lr
2063	ADDS	r6, r6, r11
2064	/* A[0] * A[4] */
2065	LDR	lr, [r1, #16]
2066	ADCS	r7, r7, #0x0
2067	ADC	r11, r0, #0x0
2068	UMLAL	r7, r11, r12, lr
2069	ADDS	r8, r8, r11
2070	/* A[0] * A[6] */
2071	LDR	lr, [r1, #24]
2072	ADCS	r9, r9, #0x0
2073	ADC	r11, r0, #0x0
2074	UMLAL	r9, r11, r12, lr
2075	ADDS	r10, r10, r11
2076	ADCS	r3, r3, #0x0
2077	STR	r4, [sp, #4]
2078	STR	r5, [sp, #8]
2079	/* A[1] * A[2] */
2080	LDR	r12, [r1, #4]
2081	LDR	lr, [r1, #8]
2082	MOV	r11, #0x0
2083	UMLAL	r6, r11, r12, lr
2084	STR	r6, [sp, #12]
2085	ADDS	r7, r7, r11
2086	/* A[1] * A[3] */
2087	LDR	lr, [r1, #12]
2088	ADC	r11, r0, #0x0
2089	UMLAL	r7, r11, r12, lr
2090	STR	r7, [sp, #16]
2091	ADDS	r8, r8, r11
2092	/* A[1] * A[4] */
2093	LDR	lr, [r1, #16]
2094	ADC	r11, r0, #0x0
2095	UMLAL	r8, r11, r12, lr
2096	ADDS	r9, r9, r11
2097	/* A[1] * A[5] */
2098	LDR	lr, [r1, #20]
2099	ADC	r11, r0, #0x0
2100	UMLAL	r9, r11, r12, lr
2101	ADDS	r10, r10, r11
2102	/* A[1] * A[6] */
2103	LDR	lr, [r1, #24]
2104	ADC	r11, r0, #0x0
2105	UMLAL	r10, r11, r12, lr
2106	ADDS	r3, r3, r11
2107	/* A[1] * A[7] */
2108	LDR	lr, [r1, #28]
2109	ADC	r4, r0, #0x0
2110	UMLAL	r3, r4, r12, lr
2111	/* A[2] * A[3] */
2112	LDR	r12, [r1, #8]
2113	LDR	lr, [r1, #12]
2114	MOV	r11, #0x0
2115	UMLAL	r8, r11, r12, lr
2116	STR	r8, [sp, #20]
2117	ADDS	r9, r9, r11
2118	/* A[2] * A[4] */
2119	LDR	lr, [r1, #16]
2120	ADC	r11, r0, #0x0
2121	UMLAL	r9, r11, r12, lr
2122	STR	r9, [sp, #24]
2123	ADDS	r10, r10, r11
2124	/* A[2] * A[5] */
2125	LDR	lr, [r1, #20]
2126	ADC	r11, r0, #0x0
2127	UMLAL	r10, r11, r12, lr
2128	ADDS	r3, r3, r11
2129	/* A[2] * A[6] */
2130	LDR	lr, [r1, #24]
2131	ADC	r11, r0, #0x0
2132	UMLAL	r3, r11, r12, lr
2133	ADDS	r4, r4, r11
2134	/* A[2] * A[7] */
2135	LDR	lr, [r1, #28]
2136	ADC	r5, r0, #0x0
2137	UMLAL	r4, r5, r12, lr
2138	/* A[3] * A[4] */
2139	LDR	r12, [r1, #12]
2140	LDR	lr, [r1, #16]
2141	MOV	r11, #0x0
2142	UMLAL	r10, r11, r12, lr
2143	STR	r10, [sp, #28]
2144	ADDS	r3, r3, r11
2145	/* A[3] * A[5] */
2146	LDR	lr, [r1, #20]
2147	ADC	r11, r0, #0x0
2148	UMLAL	r3, r11, r12, lr
2149	ADDS	r4, r4, r11
2150	/* A[3] * A[6] */
2151	LDR	lr, [r1, #24]
2152	ADC	r11, r0, #0x0
2153	UMLAL	r4, r11, r12, lr
2154	ADDS	r5, r5, r11
2155	/* A[3] * A[7] */
2156	LDR	lr, [r1, #28]
2157	ADC	r6, r0, #0x0
2158	UMLAL	r5, r6, r12, lr
2159	/* A[4] * A[5] */
2160	LDR	r12, [r1, #16]
2161	LDR	lr, [r1, #20]
2162	MOV	r11, #0x0
2163	UMLAL	r4, r11, r12, lr
2164	ADDS	r5, r5, r11
2165	/* A[4] * A[6] */
2166	LDR	lr, [r1, #24]
2167	ADC	r11, r0, #0x0
2168	UMLAL	r5, r11, r12, lr
2169	ADDS	r6, r6, r11
2170	/* A[4] * A[7] */
2171	LDR	lr, [r1, #28]
2172	ADC	r7, r0, #0x0
2173	UMLAL	r6, r7, r12, lr
2174	/* A[5] * A[6] */
2175	LDR	r12, [r1, #20]
2176	LDR	lr, [r1, #24]
2177	MOV	r11, #0x0
2178	UMLAL	r6, r11, r12, lr
2179	ADDS	r7, r7, r11
2180	/* A[5] * A[7] */
2181	LDR	lr, [r1, #28]
2182	ADC	r8, r0, #0x0
2183	UMLAL	r7, r8, r12, lr
2184	/* A[6] * A[7] */
2185	LDR	r12, [r1, #24]
2186	LDR	lr, [r1, #28]
2187	MOV	r9, #0x0
2188	UMLAL	r8, r9, r12, lr
2189	ADD	lr, sp, #0x20
2190	STM	lr, {r3, r4, r5, r6, r7, r8, r9}
2191	ADD	lr, sp, #0x4
2192	LDM	lr, {r4, r5, r6, r7, r8, r9, r10}
2193	ADDS	r4, r4, r4
2194	ADCS	r5, r5, r5
2195	ADCS	r6, r6, r6
2196	ADCS	r7, r7, r7
2197	ADCS	r8, r8, r8
2198	ADCS	r9, r9, r9
2199	ADCS	r10, r10, r10
2200	STM	lr!, {r4, r5, r6, r7, r8, r9, r10}
2201	LDM	lr, {r3, r4, r5, r6, r7, r8, r9}
2202	ADCS	r3, r3, r3
2203	ADCS	r4, r4, r4
2204	ADCS	r5, r5, r5
2205	ADCS	r6, r6, r6
2206	ADCS	r7, r7, r7
2207	ADCS	r8, r8, r8
2208	ADCS	r9, r9, r9
2209	ADC	r10, r0, #0x0
2210	STM	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
2211	ADD	lr, sp, #0x4
2212	LDM	lr, {r4, r5, r6, r7, r8, r9, r10}
2213	MOV	lr, sp
2214	/* A[0] * A[0] */
2215	LDR	r12, [r1]
2216	UMULL	r3, r11, r12, r12
2217	ADDS	r4, r4, r11
2218	/* A[1] * A[1] */
2219	LDR	r12, [r1, #4]
2220	ADCS	r5, r5, #0x0
2221	ADC	r11, r0, #0x0
2222	UMLAL	r5, r11, r12, r12
2223	ADDS	r6, r6, r11
2224	/* A[2] * A[2] */
2225	LDR	r12, [r1, #8]
2226	ADCS	r7, r7, #0x0
2227	ADC	r11, r0, #0x0
2228	UMLAL	r7, r11, r12, r12
2229	ADDS	r8, r8, r11
2230	/* A[3] * A[3] */
2231	LDR	r12, [r1, #12]
2232	ADCS	r9, r9, #0x0
2233	ADC	r11, r0, #0x0
2234	UMLAL	r9, r11, r12, r12
2235	ADDS	r10, r10, r11
2236	STM	lr!, {r3, r4, r5, r6, r7, r8, r9, r10}
2237	LDM	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
2238	/* A[4] * A[4] */
2239	LDR	r12, [r1, #16]
2240	ADCS	r3, r3, #0x0
2241	ADC	r11, r0, #0x0
2242	UMLAL	r3, r11, r12, r12
2243	ADDS	r4, r4, r11
2244	/* A[5] * A[5] */
2245	LDR	r12, [r1, #20]
2246	ADCS	r5, r5, #0x0
2247	ADC	r11, r0, #0x0
2248	UMLAL	r5, r11, r12, r12
2249	ADDS	r6, r6, r11
2250	/* A[6] * A[6] */
2251	LDR	r12, [r1, #24]
2252	ADCS	r7, r7, #0x0
2253	ADC	r11, r0, #0x0
2254	UMLAL	r7, r11, r12, r12
2255	ADDS	r8, r8, r11
2256	/* A[7] * A[7] */
2257	LDR	r12, [r1, #28]
2258	ADCS	r9, r9, #0x0
2259	ADC	r10, r10, #0x0
2260	UMLAL	r9, r10, r12, r12
2261	/* Reduce */
2262	LDR	r2, [sp, #28]
2263	MOV	lr, sp
2264	MOV	r12, #0x26
2265	UMULL	r10, r11, r10, r12
2266	ADDS	r10, r10, r2
2267	ADC	r11, r11, #0x0
2268	MOV	r12, #0x13
2269	LSL	r11, r11, #1
2270	ORR	r11, r11, r10, LSR #31
2271	MUL	r11, r11, r12
2272	LDM	lr!, {r1, r2}
2273	MOV	r12, #0x26
2274	ADDS	r1, r1, r11
2275	ADC	r11, r0, #0x0
2276	UMLAL	r1, r11, r3, r12
2277	ADDS	r2, r2, r11
2278	ADC	r11, r0, #0x0
2279	UMLAL	r2, r11, r4, r12
2280	LDM	lr!, {r3, r4}
2281	ADDS	r3, r3, r11
2282	ADC	r11, r0, #0x0
2283	UMLAL	r3, r11, r5, r12
2284	ADDS	r4, r4, r11
2285	ADC	r11, r0, #0x0
2286	UMLAL	r4, r11, r6, r12
2287	LDM	lr!, {r5, r6}
2288	ADDS	r5, r5, r11
2289	ADC	r11, r0, #0x0
2290	UMLAL	r5, r11, r7, r12
2291	ADDS	r6, r6, r11
2292	ADC	r11, r0, #0x0
2293	UMLAL	r6, r11, r8, r12
2294	LDM	lr!, {r7, r8}
2295	ADDS	r7, r7, r11
2296	ADC	r11, r0, #0x0
2297	UMLAL	r7, r11, r9, r12
2298	BFC	r10, #31, #1
2299	ADDS	r8, r10, r11
2300	/* Store */
2301	LDR	r0, [sp, #64]
2302	STM	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
2303	ADD	sp, sp, #0x44
2304	POP	{pc}
2305	/* Cycle Count = 355 */
2306	.size	fe_sq_op,.-fe_sq_op
2307#else
2308	.text
2309	.align	4
2310	.globl	fe_sq_op
2311	.type	fe_sq_op, %function
2312fe_sq_op:
2313	PUSH	{lr}
2314	SUB	sp, sp, #0x20
2315	STR	r0, [sp, #28]
2316	LDM	r1, {r0, r1, r2, r3, r4, r5, r6, r7}
2317	/* Square */
2318	UMULL	r9, r10, r0, r0
2319	UMULL	r11, r12, r0, r1
2320	ADDS	r11, r11, r11
2321	MOV	lr, #0x0
2322	UMAAL	r10, r11, lr, lr
2323	STM	sp, {r9, r10}
2324	MOV	r8, lr
2325	UMAAL	r8, r12, r0, r2
2326	ADCS	r8, r8, r8
2327	UMAAL	r8, r11, r1, r1
2328	UMULL	r9, r10, r0, r3
2329	UMAAL	r9, r12, r1, r2
2330	ADCS	r9, r9, r9
2331	UMAAL	r9, r11, lr, lr
2332	STRD	r8, r9, [sp, #8]
2333	MOV	r9, lr
2334	UMAAL	r9, r10, r0, r4
2335	UMAAL	r9, r12, r1, r3
2336	ADCS	r9, r9, r9
2337	UMAAL	r9, r11, r2, r2
2338	STR	r9, [sp, #16]
2339	UMULL	r9, r8, r0, r5
2340	UMAAL	r9, r12, r1, r4
2341	UMAAL	r9, r10, r2, r3
2342	ADCS	r9, r9, r9
2343	UMAAL	r9, r11, lr, lr
2344	STR	r9, [sp, #20]
2345	MOV	r9, lr
2346	UMAAL	r9, r8, r0, r6
2347	UMAAL	r9, r12, r1, r5
2348	UMAAL	r9, r10, r2, r4
2349	ADCS	r9, r9, r9
2350	UMAAL	r9, r11, r3, r3
2351	STR	r9, [sp, #24]
2352	UMULL	r0, r9, r0, r7
2353	UMAAL	r0, r8, r1, r6
2354	UMAAL	r0, r12, r2, r5
2355	UMAAL	r0, r10, r3, r4
2356	ADCS	r0, r0, r0
2357	UMAAL	r0, r11, lr, lr
2358	/* R[7] = r0 */
2359	UMAAL	r9, r8, r1, r7
2360	UMAAL	r9, r10, r2, r6
2361	UMAAL	r12, r9, r3, r5
2362	ADCS	r12, r12, r12
2363	UMAAL	r12, r11, r4, r4
2364	/* R[8] = r12 */
2365	UMAAL	r9, r8, r2, r7
2366	UMAAL	r10, r9, r3, r6
2367	MOV	r2, lr
2368	UMAAL	r10, r2, r4, r5
2369	ADCS	r10, r10, r10
2370	UMAAL	r11, r10, lr, lr
2371	/* R[9] = r11 */
2372	UMAAL	r2, r8, r3, r7
2373	UMAAL	r2, r9, r4, r6
2374	ADCS	r3, r2, r2
2375	UMAAL	r10, r3, r5, r5
2376	/* R[10] = r10 */
2377	MOV	r1, lr
2378	UMAAL	r1, r8, r4, r7
2379	UMAAL	r1, r9, r5, r6
2380	ADCS	r4, r1, r1
2381	UMAAL	r3, r4, lr, lr
2382	/* R[11] = r3 */
2383	UMAAL	r8, r9, r5, r7
2384	ADCS	r8, r8, r8
2385	UMAAL	r4, r8, r6, r6
2386	/* R[12] = r4 */
2387	MOV	r5, lr
2388	UMAAL	r5, r9, r6, r7
2389	ADCS	r5, r5, r5
2390	UMAAL	r8, r5, lr, lr
2391	/* R[13] = r8 */
2392	ADCS	r9, r9, r9
2393	UMAAL	r9, r5, r7, r7
2394	ADCS	r7, r5, lr
2395	/* R[14] = r9 */
2396	/* R[15] = r7 */
2397	/* Reduce */
2398	MOV	r6, #0x25
2399	UMAAL	r7, r0, r7, r6
2400	MOV	r6, #0x13
2401	LSL	r0, r0, #1
2402	ORR	r0, r0, r7, LSR #31
2403	MUL	lr, r0, r6
2404	POP	{r0, r1}
2405	MOV	r6, #0x26
2406	UMAAL	r0, lr, r12, r6
2407	UMAAL	r1, lr, r11, r6
2408	MOV	r12, r3
2409	MOV	r11, r4
2410	POP	{r2, r3, r4}
2411	UMAAL	r2, lr, r10, r6
2412	UMAAL	r3, lr, r12, r6
2413	UMAAL	r4, lr, r11, r6
2414	MOV	r12, r6
2415	POP	{r5, r6}
2416	UMAAL	r5, lr, r8, r12
2417	BFC	r7, #31, #1
2418	UMAAL	r6, lr, r9, r12
2419	ADD	r7, r7, lr
2420	POP	{lr}
2421	/* Store */
2422	STM	lr, {r0, r1, r2, r3, r4, r5, r6, r7}
2423	POP	{pc}
2424	/* Cycle Count = 179 */
2425	.size	fe_sq_op,.-fe_sq_op
2426#endif /* WOLFSSL_ARM_ARCH_7M */
2427	.text
2428	.align	4
2429	.globl	fe_sq
2430	.type	fe_sq, %function
2431fe_sq:
2432	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2433	BL	fe_sq_op
2434	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2435	/* Cycle Count = 24 */
2436	.size	fe_sq,.-fe_sq
2437#ifdef HAVE_CURVE25519
2438#ifdef WOLFSSL_ARM_ARCH_7M
2439	.text
2440	.align	4
2441	.globl	fe_mul121666
2442	.type	fe_mul121666, %function
2443fe_mul121666:
2444	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2445	/* Multiply by 121666 */
2446	LDM	r1, {r2, r3, r4, r5, r6, r7, r8, r9}
2447	MOV	r12, #0xdb42
2448	MOVT	r12, #0x1
2449	UMULL	r2, r10, r2, r12
2450	UMULL	r3, r11, r3, r12
2451	ADDS	r3, r3, r10
2452	ADC	r11, r11, #0x0
2453	UMULL	r4, r10, r4, r12
2454	ADDS	r4, r4, r11
2455	ADC	r10, r10, #0x0
2456	UMULL	r5, r11, r5, r12
2457	ADDS	r5, r5, r10
2458	ADC	r11, r11, #0x0
2459	UMULL	r6, r10, r6, r12
2460	ADDS	r6, r6, r11
2461	ADC	r10, r10, #0x0
2462	UMULL	r7, r11, r7, r12
2463	ADDS	r7, r7, r10
2464	ADC	r11, r11, #0x0
2465	UMULL	r8, r10, r8, r12
2466	ADDS	r8, r8, r11
2467	ADC	r10, r10, #0x0
2468	UMULL	r9, r11, r9, r12
2469	ADDS	r9, r9, r10
2470	MOV	r12, #0x13
2471	ADC	r11, r11, #0x0
2472	LSL	r11, r11, #1
2473	ORR	r11, r11, r9, LSR #31
2474	MUL	r11, r11, r12
2475	ADDS	r2, r2, r11
2476	ADCS	r3, r3, #0x0
2477	ADCS	r4, r4, #0x0
2478	ADCS	r5, r5, #0x0
2479	ADCS	r6, r6, #0x0
2480	ADCS	r7, r7, #0x0
2481	BFC	r9, #31, #1
2482	ADCS	r8, r8, #0x0
2483	ADC	r9, r9, #0x0
2484	STM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
2485	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2486	/* Cycle Count = 75 */
2487	.size	fe_mul121666,.-fe_mul121666
2488#else
2489	.text
2490	.align	4
2491	.globl	fe_mul121666
2492	.type	fe_mul121666, %function
2493fe_mul121666:
2494	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2495	/* Multiply by 121666 */
2496	LDM	r1, {r2, r3, r4, r5, r6, r7, r8, r9}
2497	MOV	r11, #0xdb42
2498	MOVT	r11, #0x1
2499	UMULL	r2, r12, r2, r11
2500	SUB	r10, r11, #0x1
2501	UMAAL	r3, r12, r3, r10
2502	UMAAL	r4, r12, r4, r10
2503	UMAAL	r5, r12, r5, r10
2504	UMAAL	r6, r12, r6, r10
2505	UMAAL	r7, r12, r7, r10
2506	UMAAL	r8, r12, r8, r10
2507	MOV	r11, #0x13
2508	UMAAL	r9, r12, r9, r10
2509	LSL	r12, r12, #1
2510	ORR	r12, r12, r9, LSR #31
2511	MUL	r12, r12, r11
2512	ADDS	r2, r2, r12
2513	ADCS	r3, r3, #0x0
2514	ADCS	r4, r4, #0x0
2515	ADCS	r5, r5, #0x0
2516	ADCS	r6, r6, #0x0
2517	ADCS	r7, r7, #0x0
2518	BFC	r9, #31, #1
2519	ADCS	r8, r8, #0x0
2520	ADC	r9, r9, #0x0
2521	STM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
2522	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2523	/* Cycle Count = 69 */
2524	.size	fe_mul121666,.-fe_mul121666
2525#endif /* WOLFSSL_ARM_ARCH_7M */
2526#ifndef WC_NO_CACHE_RESISTANT
2527	.text
2528	.align	4
2529	.globl	curve25519
2530	.type	curve25519, %function
2531curve25519:
2532	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2533	SUB	sp, sp, #0xbc
2534	STR	r0, [sp, #160]
2535	STR	r1, [sp, #164]
2536	STR	r2, [sp, #168]
2537	MOV	r1, #0x0
2538	STR	r1, [sp, #172]
2539	MOV	r4, #0x1
2540	MOV	r5, #0x0
2541	MOV	r6, #0x0
2542	MOV	r7, #0x0
2543	MOV	r8, #0x0
2544	MOV	r9, #0x0
2545	MOV	r10, #0x0
2546	MOV	r11, #0x0
2547	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
2548	ADD	r3, sp, #0x20
2549	STM	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
2550	MOV	r4, #0x0
2551	MOV	r3, sp
2552	STM	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
2553	ADD	r3, sp, #0x40
2554	/* Copy */
2555	LDM	r2, {r4, r5, r6, r7, r8, r9, r10, r11}
2556	STM	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
2557	MOV	r1, #0x1e
2558	STR	r1, [sp, #180]
2559	MOV	r2, #0x1c
2560	STR	r2, [sp, #176]
2561L_curve25519_words:
2562L_curve25519_bits:
2563	LDR	r1, [sp, #164]
2564	LDR	r2, [r1, r2]
2565	LDR	r1, [sp, #180]
2566	LSR	r2, r2, r1
2567	AND	r2, r2, #0x1
2568	STR	r2, [sp, #184]
2569	LDR	r1, [sp, #172]
2570	EOR	r1, r1, r2
2571	STR	r1, [sp, #172]
2572	LDR	r0, [sp, #160]
2573	/* Conditional Swap */
2574	RSB	r1, r1, #0x0
2575	MOV	r3, r0
2576	ADD	r12, sp, #0x40
2577	LDM	r3, {r4, r5}
2578	LDM	r12, {r6, r7}
2579	EOR	r8, r4, r6
2580	EOR	r9, r5, r7
2581	AND	r8, r8, r1
2582	AND	r9, r9, r1
2583	EOR	r4, r4, r8
2584	EOR	r5, r5, r9
2585	EOR	r6, r6, r8
2586	EOR	r7, r7, r9
2587	STM	r3!, {r4, r5}
2588	STM	r12!, {r6, r7}
2589	LDM	r3, {r4, r5}
2590	LDM	r12, {r6, r7}
2591	EOR	r8, r4, r6
2592	EOR	r9, r5, r7
2593	AND	r8, r8, r1
2594	AND	r9, r9, r1
2595	EOR	r4, r4, r8
2596	EOR	r5, r5, r9
2597	EOR	r6, r6, r8
2598	EOR	r7, r7, r9
2599	STM	r3!, {r4, r5}
2600	STM	r12!, {r6, r7}
2601	LDM	r3, {r4, r5}
2602	LDM	r12, {r6, r7}
2603	EOR	r8, r4, r6
2604	EOR	r9, r5, r7
2605	AND	r8, r8, r1
2606	AND	r9, r9, r1
2607	EOR	r4, r4, r8
2608	EOR	r5, r5, r9
2609	EOR	r6, r6, r8
2610	EOR	r7, r7, r9
2611	STM	r3!, {r4, r5}
2612	STM	r12!, {r6, r7}
2613	LDM	r3, {r4, r5}
2614	LDM	r12, {r6, r7}
2615	EOR	r8, r4, r6
2616	EOR	r9, r5, r7
2617	AND	r8, r8, r1
2618	AND	r9, r9, r1
2619	EOR	r4, r4, r8
2620	EOR	r5, r5, r9
2621	EOR	r6, r6, r8
2622	EOR	r7, r7, r9
2623	STM	r3!, {r4, r5}
2624	STM	r12!, {r6, r7}
2625	LDR	r1, [sp, #172]
2626	/* Conditional Swap */
2627	RSB	r1, r1, #0x0
2628	MOV	r3, sp
2629	ADD	r12, sp, #0x20
2630	LDM	r3, {r4, r5}
2631	LDM	r12, {r6, r7}
2632	EOR	r8, r4, r6
2633	EOR	r9, r5, r7
2634	AND	r8, r8, r1
2635	AND	r9, r9, r1
2636	EOR	r4, r4, r8
2637	EOR	r5, r5, r9
2638	EOR	r6, r6, r8
2639	EOR	r7, r7, r9
2640	STM	r3!, {r4, r5}
2641	STM	r12!, {r6, r7}
2642	LDM	r3, {r4, r5}
2643	LDM	r12, {r6, r7}
2644	EOR	r8, r4, r6
2645	EOR	r9, r5, r7
2646	AND	r8, r8, r1
2647	AND	r9, r9, r1
2648	EOR	r4, r4, r8
2649	EOR	r5, r5, r9
2650	EOR	r6, r6, r8
2651	EOR	r7, r7, r9
2652	STM	r3!, {r4, r5}
2653	STM	r12!, {r6, r7}
2654	LDM	r3, {r4, r5}
2655	LDM	r12, {r6, r7}
2656	EOR	r8, r4, r6
2657	EOR	r9, r5, r7
2658	AND	r8, r8, r1
2659	AND	r9, r9, r1
2660	EOR	r4, r4, r8
2661	EOR	r5, r5, r9
2662	EOR	r6, r6, r8
2663	EOR	r7, r7, r9
2664	STM	r3!, {r4, r5}
2665	STM	r12!, {r6, r7}
2666	LDM	r3, {r4, r5}
2667	LDM	r12, {r6, r7}
2668	EOR	r8, r4, r6
2669	EOR	r9, r5, r7
2670	AND	r8, r8, r1
2671	AND	r9, r9, r1
2672	EOR	r4, r4, r8
2673	EOR	r5, r5, r9
2674	EOR	r6, r6, r8
2675	EOR	r7, r7, r9
2676	STM	r3!, {r4, r5}
2677	STM	r12!, {r6, r7}
2678	LDR	r1, [sp, #184]
2679	STR	r1, [sp, #172]
2680	MOV	r3, sp
2681	LDR	r2, [sp, #160]
2682	ADD	r1, sp, #0x80
2683	LDR	r0, [sp, #160]
2684	BL	fe_add_sub_op
2685	ADD	r3, sp, #0x20
2686	ADD	r2, sp, #0x40
2687	ADD	r1, sp, #0x60
2688	MOV	r0, sp
2689	BL	fe_add_sub_op
2690	LDR	r2, [sp, #160]
2691	ADD	r1, sp, #0x60
2692	ADD	r0, sp, #0x20
2693	BL	fe_mul_op
2694	ADD	r2, sp, #0x80
2695	MOV	r1, sp
2696	MOV	r0, sp
2697	BL	fe_mul_op
2698	ADD	r1, sp, #0x80
2699	ADD	r0, sp, #0x80
2700	BL	fe_sq_op
2701	LDR	r1, [sp, #160]
2702	ADD	r0, sp, #0x60
2703	BL	fe_sq_op
2704	MOV	r3, sp
2705	ADD	r2, sp, #0x20
2706	MOV	r1, sp
2707	ADD	r0, sp, #0x40
2708	BL	fe_add_sub_op
2709	ADD	r2, sp, #0x80
2710	ADD	r1, sp, #0x60
2711	LDR	r0, [sp, #160]
2712	BL	fe_mul_op
2713	ADD	r2, sp, #0x80
2714	ADD	r1, sp, #0x60
2715	ADD	r0, sp, #0x60
2716	BL	fe_sub_op
2717	MOV	r1, sp
2718	MOV	r0, sp
2719	BL	fe_sq_op
2720	ADD	r1, sp, #0x60
2721	ADD	r0, sp, #0x20
2722	BL	fe_mul121666
2723	ADD	r1, sp, #0x40
2724	ADD	r0, sp, #0x40
2725	BL	fe_sq_op
2726	ADD	r2, sp, #0x20
2727	ADD	r1, sp, #0x80
2728	ADD	r0, sp, #0x80
2729	BL	fe_add_op
2730	MOV	r2, sp
2731	LDR	r1, [sp, #168]
2732	ADD	r0, sp, #0x20
2733	BL	fe_mul_op
2734	ADD	r2, sp, #0x80
2735	ADD	r1, sp, #0x60
2736	MOV	r0, sp
2737	BL	fe_mul_op
2738	LDR	r2, [sp, #176]
2739	LDR	r1, [sp, #180]
2740	SUBS	r1, r1, #0x1
2741	STR	r1, [sp, #180]
2742#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2743	BGE	L_curve25519_bits
2744#else
2745	BGE.W	L_curve25519_bits
2746#endif
2747	MOV	r1, #0x1f
2748	STR	r1, [sp, #180]
2749	SUBS	r2, r2, #0x4
2750	STR	r2, [sp, #176]
2751#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2752	BGE	L_curve25519_words
2753#else
2754	BGE.W	L_curve25519_words
2755#endif
2756	/* Invert */
2757	ADD	r1, sp, #0x0
2758	ADD	r0, sp, #0x20
2759	BL	fe_sq_op
2760	ADD	r1, sp, #0x20
2761	ADD	r0, sp, #0x40
2762	BL	fe_sq_op
2763	ADD	r1, sp, #0x40
2764	ADD	r0, sp, #0x40
2765	BL	fe_sq_op
2766	ADD	r2, sp, #0x40
2767	ADD	r1, sp, #0x0
2768	ADD	r0, sp, #0x40
2769	BL	fe_mul_op
2770	ADD	r2, sp, #0x40
2771	ADD	r1, sp, #0x20
2772	ADD	r0, sp, #0x20
2773	BL	fe_mul_op
2774	ADD	r1, sp, #0x20
2775	ADD	r0, sp, #0x60
2776	BL	fe_sq_op
2777	ADD	r2, sp, #0x60
2778	ADD	r1, sp, #0x40
2779	ADD	r0, sp, #0x40
2780	BL	fe_mul_op
2781	ADD	r1, sp, #0x40
2782	ADD	r0, sp, #0x60
2783	BL	fe_sq_op
2784	MOV	r12, #0x4
2785L_curve25519_inv_1:
2786	ADD	r1, sp, #0x60
2787	ADD	r0, sp, #0x60
2788	PUSH	{r12}
2789	BL	fe_sq_op
2790	POP	{r12}
2791	SUBS	r12, r12, #0x1
2792#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2793	BNE	L_curve25519_inv_1
2794#else
2795	BNE.N	L_curve25519_inv_1
2796#endif
2797	ADD	r2, sp, #0x40
2798	ADD	r1, sp, #0x60
2799	ADD	r0, sp, #0x40
2800	BL	fe_mul_op
2801	ADD	r1, sp, #0x40
2802	ADD	r0, sp, #0x60
2803	BL	fe_sq_op
2804	MOV	r12, #0x9
2805L_curve25519_inv_2:
2806	ADD	r1, sp, #0x60
2807	ADD	r0, sp, #0x60
2808	PUSH	{r12}
2809	BL	fe_sq_op
2810	POP	{r12}
2811	SUBS	r12, r12, #0x1
2812#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2813	BNE	L_curve25519_inv_2
2814#else
2815	BNE.N	L_curve25519_inv_2
2816#endif
2817	ADD	r2, sp, #0x40
2818	ADD	r1, sp, #0x60
2819	ADD	r0, sp, #0x60
2820	BL	fe_mul_op
2821	ADD	r1, sp, #0x60
2822	ADD	r0, sp, #0x80
2823	BL	fe_sq_op
2824	MOV	r12, #0x13
2825L_curve25519_inv_3:
2826	ADD	r1, sp, #0x80
2827	ADD	r0, sp, #0x80
2828	PUSH	{r12}
2829	BL	fe_sq_op
2830	POP	{r12}
2831	SUBS	r12, r12, #0x1
2832#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2833	BNE	L_curve25519_inv_3
2834#else
2835	BNE.N	L_curve25519_inv_3
2836#endif
2837	ADD	r2, sp, #0x60
2838	ADD	r1, sp, #0x80
2839	ADD	r0, sp, #0x60
2840	BL	fe_mul_op
2841	MOV	r12, #0xa
2842L_curve25519_inv_4:
2843	ADD	r1, sp, #0x60
2844	ADD	r0, sp, #0x60
2845	PUSH	{r12}
2846	BL	fe_sq_op
2847	POP	{r12}
2848	SUBS	r12, r12, #0x1
2849#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2850	BNE	L_curve25519_inv_4
2851#else
2852	BNE.N	L_curve25519_inv_4
2853#endif
2854	ADD	r2, sp, #0x40
2855	ADD	r1, sp, #0x60
2856	ADD	r0, sp, #0x40
2857	BL	fe_mul_op
2858	ADD	r1, sp, #0x40
2859	ADD	r0, sp, #0x60
2860	BL	fe_sq_op
2861	MOV	r12, #0x31
2862L_curve25519_inv_5:
2863	ADD	r1, sp, #0x60
2864	ADD	r0, sp, #0x60
2865	PUSH	{r12}
2866	BL	fe_sq_op
2867	POP	{r12}
2868	SUBS	r12, r12, #0x1
2869#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2870	BNE	L_curve25519_inv_5
2871#else
2872	BNE.N	L_curve25519_inv_5
2873#endif
2874	ADD	r2, sp, #0x40
2875	ADD	r1, sp, #0x60
2876	ADD	r0, sp, #0x60
2877	BL	fe_mul_op
2878	ADD	r1, sp, #0x60
2879	ADD	r0, sp, #0x80
2880	BL	fe_sq_op
2881	MOV	r12, #0x63
2882L_curve25519_inv_6:
2883	ADD	r1, sp, #0x80
2884	ADD	r0, sp, #0x80
2885	PUSH	{r12}
2886	BL	fe_sq_op
2887	POP	{r12}
2888	SUBS	r12, r12, #0x1
2889#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2890	BNE	L_curve25519_inv_6
2891#else
2892	BNE.N	L_curve25519_inv_6
2893#endif
2894	ADD	r2, sp, #0x60
2895	ADD	r1, sp, #0x80
2896	ADD	r0, sp, #0x60
2897	BL	fe_mul_op
2898	MOV	r12, #0x32
2899L_curve25519_inv_7:
2900	ADD	r1, sp, #0x60
2901	ADD	r0, sp, #0x60
2902	PUSH	{r12}
2903	BL	fe_sq_op
2904	POP	{r12}
2905	SUBS	r12, r12, #0x1
2906#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2907	BNE	L_curve25519_inv_7
2908#else
2909	BNE.N	L_curve25519_inv_7
2910#endif
2911	ADD	r2, sp, #0x40
2912	ADD	r1, sp, #0x60
2913	ADD	r0, sp, #0x40
2914	BL	fe_mul_op
2915	MOV	r12, #0x5
2916L_curve25519_inv_8:
2917	ADD	r1, sp, #0x40
2918	ADD	r0, sp, #0x40
2919	PUSH	{r12}
2920	BL	fe_sq_op
2921	POP	{r12}
2922	SUBS	r12, r12, #0x1
2923#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2924	BNE	L_curve25519_inv_8
2925#else
2926	BNE.N	L_curve25519_inv_8
2927#endif
2928	ADD	r2, sp, #0x20
2929	ADD	r1, sp, #0x40
2930	ADD	r0, sp, #0x0
2931	BL	fe_mul_op
2932	MOV	r2, sp
2933	LDR	r1, [sp, #160]
2934	LDR	r0, [sp, #160]
2935	BL	fe_mul_op
2936	MOV	r0, #0x0
2937	ADD	sp, sp, #0xbc
2938	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
2939	/* Cycle Count = 682 */
2940	.size	curve25519,.-curve25519
2941#else
2942	.text
2943	.align	4
2944	.globl	curve25519
2945	.type	curve25519, %function
2946curve25519:
2947	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
2948	SUB	sp, sp, #0xc0
2949	STR	r0, [sp, #176]
2950	STR	r1, [sp, #160]
2951	STR	r2, [sp, #172]
2952	ADD	r5, sp, #0x40
2953	ADD	r4, sp, #0x20
2954	STR	sp, [sp, #184]
2955	STR	r5, [sp, #180]
2956	STR	r4, [sp, #188]
2957	MOV	r1, #0x0
2958	STR	r1, [sp, #164]
2959	MOV	r4, #0x1
2960	MOV	r5, #0x0
2961	MOV	r6, #0x0
2962	MOV	r7, #0x0
2963	MOV	r8, #0x0
2964	MOV	r9, #0x0
2965	MOV	r10, #0x0
2966	MOV	r11, #0x0
2967	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
2968	ADD	r3, sp, #0x20
2969	STM	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
2970	MOV	r4, #0x0
2971	MOV	r3, sp
2972	STM	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
2973	ADD	r3, sp, #0x40
2974	/* Copy */
2975	LDM	r2, {r4, r5, r6, r7, r8, r9, r10, r11}
2976	STM	r3, {r4, r5, r6, r7, r8, r9, r10, r11}
2977	MOV	r2, #0xfe
2978L_curve25519_bits:
2979	STR	r2, [sp, #168]
2980	LDR	r1, [sp, #160]
2981	AND	r4, r2, #0x1f
2982	LSR	r2, r2, #5
2983	LDR	r2, [r1, r2, LSL #2]
2984	RSB	r4, r4, #0x1f
2985	LSL	r2, r2, r4
2986	LDR	r1, [sp, #164]
2987	EOR	r1, r1, r2
2988	ASR	r1, r1, #31
2989	STR	r2, [sp, #164]
2990	/* Conditional Swap */
2991	ADD	r11, sp, #0xb0
2992	LDM	r11, {r4, r5, r6, r7}
2993	EOR	r8, r4, r5
2994	EOR	r9, r6, r7
2995	AND	r8, r8, r1
2996	AND	r9, r9, r1
2997	EOR	r4, r4, r8
2998	EOR	r5, r5, r8
2999	EOR	r6, r6, r9
3000	EOR	r7, r7, r9
3001	STM	r11, {r4, r5, r6, r7}
3002	/* Ladder step */
3003	LDR	r3, [sp, #184]
3004	LDR	r2, [sp, #176]
3005	ADD	r1, sp, #0x80
3006	LDR	r0, [sp, #176]
3007	BL	fe_add_sub_op
3008	LDR	r3, [sp, #188]
3009	LDR	r2, [sp, #180]
3010	ADD	r1, sp, #0x60
3011	LDR	r0, [sp, #184]
3012	BL	fe_add_sub_op
3013	LDR	r2, [sp, #176]
3014	ADD	r1, sp, #0x60
3015	LDR	r0, [sp, #188]
3016	BL	fe_mul_op
3017	ADD	r2, sp, #0x80
3018	LDR	r1, [sp, #184]
3019	LDR	r0, [sp, #184]
3020	BL	fe_mul_op
3021	ADD	r1, sp, #0x80
3022	ADD	r0, sp, #0x60
3023	BL	fe_sq_op
3024	LDR	r1, [sp, #176]
3025	ADD	r0, sp, #0x80
3026	BL	fe_sq_op
3027	LDR	r3, [sp, #184]
3028	LDR	r2, [sp, #188]
3029	LDR	r1, [sp, #184]
3030	LDR	r0, [sp, #180]
3031	BL	fe_add_sub_op
3032	ADD	r2, sp, #0x60
3033	ADD	r1, sp, #0x80
3034	LDR	r0, [sp, #176]
3035	BL	fe_mul_op
3036	ADD	r2, sp, #0x60
3037	ADD	r1, sp, #0x80
3038	ADD	r0, sp, #0x80
3039	BL	fe_sub_op
3040	LDR	r1, [sp, #184]
3041	LDR	r0, [sp, #184]
3042	BL	fe_sq_op
3043	ADD	r1, sp, #0x80
3044	LDR	r0, [sp, #188]
3045	BL	fe_mul121666
3046	LDR	r1, [sp, #180]
3047	LDR	r0, [sp, #180]
3048	BL	fe_sq_op
3049	LDR	r2, [sp, #188]
3050	ADD	r1, sp, #0x60
3051	ADD	r0, sp, #0x60
3052	BL	fe_add_op
3053	LDR	r2, [sp, #184]
3054	LDR	r1, [sp, #172]
3055	LDR	r0, [sp, #188]
3056	BL	fe_mul_op
3057	ADD	r2, sp, #0x60
3058	ADD	r1, sp, #0x80
3059	LDR	r0, [sp, #184]
3060	BL	fe_mul_op
3061	LDR	r2, [sp, #168]
3062	SUBS	r2, r2, #0x1
3063#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3064	BGE	L_curve25519_bits
3065#else
3066	BGE.N	L_curve25519_bits
3067#endif
3068	/*   Cycle Count: 171 */
3069	LDR	r1, [sp, #184]
3070	/* Copy */
3071	LDM	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
3072	STM	sp, {r4, r5, r6, r7, r8, r9, r10, r11}
3073	/* Invert */
3074	ADD	r1, sp, #0x0
3075	ADD	r0, sp, #0x20
3076	BL	fe_sq_op
3077	ADD	r1, sp, #0x20
3078	ADD	r0, sp, #0x40
3079	BL	fe_sq_op
3080	ADD	r1, sp, #0x40
3081	ADD	r0, sp, #0x40
3082	BL	fe_sq_op
3083	ADD	r2, sp, #0x40
3084	ADD	r1, sp, #0x0
3085	ADD	r0, sp, #0x40
3086	BL	fe_mul_op
3087	ADD	r2, sp, #0x40
3088	ADD	r1, sp, #0x20
3089	ADD	r0, sp, #0x20
3090	BL	fe_mul_op
3091	ADD	r1, sp, #0x20
3092	ADD	r0, sp, #0x60
3093	BL	fe_sq_op
3094	ADD	r2, sp, #0x60
3095	ADD	r1, sp, #0x40
3096	ADD	r0, sp, #0x40
3097	BL	fe_mul_op
3098	ADD	r1, sp, #0x40
3099	ADD	r0, sp, #0x60
3100	BL	fe_sq_op
3101	MOV	r12, #0x4
3102L_curve25519_inv_1:
3103	ADD	r1, sp, #0x60
3104	ADD	r0, sp, #0x60
3105	PUSH	{r12}
3106	BL	fe_sq_op
3107	POP	{r12}
3108	SUBS	r12, r12, #0x1
3109#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3110	BNE	L_curve25519_inv_1
3111#else
3112	BNE.N	L_curve25519_inv_1
3113#endif
3114	ADD	r2, sp, #0x40
3115	ADD	r1, sp, #0x60
3116	ADD	r0, sp, #0x40
3117	BL	fe_mul_op
3118	ADD	r1, sp, #0x40
3119	ADD	r0, sp, #0x60
3120	BL	fe_sq_op
3121	MOV	r12, #0x9
3122L_curve25519_inv_2:
3123	ADD	r1, sp, #0x60
3124	ADD	r0, sp, #0x60
3125	PUSH	{r12}
3126	BL	fe_sq_op
3127	POP	{r12}
3128	SUBS	r12, r12, #0x1
3129#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3130	BNE	L_curve25519_inv_2
3131#else
3132	BNE.N	L_curve25519_inv_2
3133#endif
3134	ADD	r2, sp, #0x40
3135	ADD	r1, sp, #0x60
3136	ADD	r0, sp, #0x60
3137	BL	fe_mul_op
3138	ADD	r1, sp, #0x60
3139	ADD	r0, sp, #0x80
3140	BL	fe_sq_op
3141	MOV	r12, #0x13
3142L_curve25519_inv_3:
3143	ADD	r1, sp, #0x80
3144	ADD	r0, sp, #0x80
3145	PUSH	{r12}
3146	BL	fe_sq_op
3147	POP	{r12}
3148	SUBS	r12, r12, #0x1
3149#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3150	BNE	L_curve25519_inv_3
3151#else
3152	BNE.N	L_curve25519_inv_3
3153#endif
3154	ADD	r2, sp, #0x60
3155	ADD	r1, sp, #0x80
3156	ADD	r0, sp, #0x60
3157	BL	fe_mul_op
3158	MOV	r12, #0xa
3159L_curve25519_inv_4:
3160	ADD	r1, sp, #0x60
3161	ADD	r0, sp, #0x60
3162	PUSH	{r12}
3163	BL	fe_sq_op
3164	POP	{r12}
3165	SUBS	r12, r12, #0x1
3166#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3167	BNE	L_curve25519_inv_4
3168#else
3169	BNE.N	L_curve25519_inv_4
3170#endif
3171	ADD	r2, sp, #0x40
3172	ADD	r1, sp, #0x60
3173	ADD	r0, sp, #0x40
3174	BL	fe_mul_op
3175	ADD	r1, sp, #0x40
3176	ADD	r0, sp, #0x60
3177	BL	fe_sq_op
3178	MOV	r12, #0x31
3179L_curve25519_inv_5:
3180	ADD	r1, sp, #0x60
3181	ADD	r0, sp, #0x60
3182	PUSH	{r12}
3183	BL	fe_sq_op
3184	POP	{r12}
3185	SUBS	r12, r12, #0x1
3186#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3187	BNE	L_curve25519_inv_5
3188#else
3189	BNE.N	L_curve25519_inv_5
3190#endif
3191	ADD	r2, sp, #0x40
3192	ADD	r1, sp, #0x60
3193	ADD	r0, sp, #0x60
3194	BL	fe_mul_op
3195	ADD	r1, sp, #0x60
3196	ADD	r0, sp, #0x80
3197	BL	fe_sq_op
3198	MOV	r12, #0x63
3199L_curve25519_inv_6:
3200	ADD	r1, sp, #0x80
3201	ADD	r0, sp, #0x80
3202	PUSH	{r12}
3203	BL	fe_sq_op
3204	POP	{r12}
3205	SUBS	r12, r12, #0x1
3206#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3207	BNE	L_curve25519_inv_6
3208#else
3209	BNE.N	L_curve25519_inv_6
3210#endif
3211	ADD	r2, sp, #0x60
3212	ADD	r1, sp, #0x80
3213	ADD	r0, sp, #0x60
3214	BL	fe_mul_op
3215	MOV	r12, #0x32
3216L_curve25519_inv_7:
3217	ADD	r1, sp, #0x60
3218	ADD	r0, sp, #0x60
3219	PUSH	{r12}
3220	BL	fe_sq_op
3221	POP	{r12}
3222	SUBS	r12, r12, #0x1
3223#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3224	BNE	L_curve25519_inv_7
3225#else
3226	BNE.N	L_curve25519_inv_7
3227#endif
3228	ADD	r2, sp, #0x40
3229	ADD	r1, sp, #0x60
3230	ADD	r0, sp, #0x40
3231	BL	fe_mul_op
3232	MOV	r12, #0x5
3233L_curve25519_inv_8:
3234	ADD	r1, sp, #0x40
3235	ADD	r0, sp, #0x40
3236	PUSH	{r12}
3237	BL	fe_sq_op
3238	POP	{r12}
3239	SUBS	r12, r12, #0x1
3240#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3241	BNE	L_curve25519_inv_8
3242#else
3243	BNE.N	L_curve25519_inv_8
3244#endif
3245	ADD	r2, sp, #0x20
3246	ADD	r1, sp, #0x40
3247	ADD	r0, sp, #0x0
3248	BL	fe_mul_op
3249	LDR	r2, [sp, #184]
3250	LDR	r1, [sp, #176]
3251	LDR	r0, [sp, #176]
3252	BL	fe_mul_op
3253	/* Ensure result is less than modulus */
3254	LDR	r0, [sp, #176]
3255	LDM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
3256	MOV	r2, #0x13
3257	AND	r2, r2, r11, ASR #31
3258	ADDS	r4, r4, r2
3259	ADCS	r5, r5, #0x0
3260	ADCS	r6, r6, #0x0
3261	ADCS	r7, r7, #0x0
3262	ADCS	r8, r8, #0x0
3263	ADCS	r9, r9, #0x0
3264	BFC	r11, #31, #1
3265	ADCS	r10, r10, #0x0
3266	ADC	r11, r11, #0x0
3267	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
3268	MOV	r0, #0x0
3269	ADD	sp, sp, #0xc0
3270	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
3271	/* Cycle Count = 589 */
3272	.size	curve25519,.-curve25519
3273#endif /* WC_NO_CACHE_RESISTANT */
3274#endif /* HAVE_CURVE25519 */
3275#if defined(HAVE_ED25519) || defined(WOLFSSL_CURVE25519_USE_ED25519)
3276	.text
3277	.align	4
3278	.globl	fe_invert
3279	.type	fe_invert, %function
3280fe_invert:
3281	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
3282	SUB	sp, sp, #0x88
3283	/* Invert */
3284	STR	r0, [sp, #128]
3285	STR	r1, [sp, #132]
3286	LDR	r1, [sp, #132]
3287	MOV	r0, sp
3288	BL	fe_sq_op
3289	MOV	r1, sp
3290	ADD	r0, sp, #0x20
3291	BL	fe_sq_op
3292	ADD	r1, sp, #0x20
3293	ADD	r0, sp, #0x20
3294	BL	fe_sq_op
3295	ADD	r2, sp, #0x20
3296	LDR	r1, [sp, #132]
3297	ADD	r0, sp, #0x20
3298	BL	fe_mul_op
3299	ADD	r2, sp, #0x20
3300	MOV	r1, sp
3301	MOV	r0, sp
3302	BL	fe_mul_op
3303	MOV	r1, sp
3304	ADD	r0, sp, #0x40
3305	BL	fe_sq_op
3306	ADD	r2, sp, #0x40
3307	ADD	r1, sp, #0x20
3308	ADD	r0, sp, #0x20
3309	BL	fe_mul_op
3310	ADD	r1, sp, #0x20
3311	ADD	r0, sp, #0x40
3312	BL	fe_sq_op
3313	MOV	r12, #0x4
3314L_fe_invert1:
3315	ADD	r1, sp, #0x40
3316	ADD	r0, sp, #0x40
3317	PUSH	{r12}
3318	BL	fe_sq_op
3319	POP	{r12}
3320	SUBS	r12, r12, #0x1
3321#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3322	BNE	L_fe_invert1
3323#else
3324	BNE.N	L_fe_invert1
3325#endif
3326	ADD	r2, sp, #0x20
3327	ADD	r1, sp, #0x40
3328	ADD	r0, sp, #0x20
3329	BL	fe_mul_op
3330	ADD	r1, sp, #0x20
3331	ADD	r0, sp, #0x40
3332	BL	fe_sq_op
3333	MOV	r12, #0x9
3334L_fe_invert2:
3335	ADD	r1, sp, #0x40
3336	ADD	r0, sp, #0x40
3337	PUSH	{r12}
3338	BL	fe_sq_op
3339	POP	{r12}
3340	SUBS	r12, r12, #0x1
3341#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3342	BNE	L_fe_invert2
3343#else
3344	BNE.N	L_fe_invert2
3345#endif
3346	ADD	r2, sp, #0x20
3347	ADD	r1, sp, #0x40
3348	ADD	r0, sp, #0x40
3349	BL	fe_mul_op
3350	ADD	r1, sp, #0x40
3351	ADD	r0, sp, #0x60
3352	BL	fe_sq_op
3353	MOV	r12, #0x13
3354L_fe_invert3:
3355	ADD	r1, sp, #0x60
3356	ADD	r0, sp, #0x60
3357	PUSH	{r12}
3358	BL	fe_sq_op
3359	POP	{r12}
3360	SUBS	r12, r12, #0x1
3361#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3362	BNE	L_fe_invert3
3363#else
3364	BNE.N	L_fe_invert3
3365#endif
3366	ADD	r2, sp, #0x40
3367	ADD	r1, sp, #0x60
3368	ADD	r0, sp, #0x40
3369	BL	fe_mul_op
3370	MOV	r12, #0xa
3371L_fe_invert4:
3372	ADD	r1, sp, #0x40
3373	ADD	r0, sp, #0x40
3374	PUSH	{r12}
3375	BL	fe_sq_op
3376	POP	{r12}
3377	SUBS	r12, r12, #0x1
3378#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3379	BNE	L_fe_invert4
3380#else
3381	BNE.N	L_fe_invert4
3382#endif
3383	ADD	r2, sp, #0x20
3384	ADD	r1, sp, #0x40
3385	ADD	r0, sp, #0x20
3386	BL	fe_mul_op
3387	ADD	r1, sp, #0x20
3388	ADD	r0, sp, #0x40
3389	BL	fe_sq_op
3390	MOV	r12, #0x31
3391L_fe_invert5:
3392	ADD	r1, sp, #0x40
3393	ADD	r0, sp, #0x40
3394	PUSH	{r12}
3395	BL	fe_sq_op
3396	POP	{r12}
3397	SUBS	r12, r12, #0x1
3398#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3399	BNE	L_fe_invert5
3400#else
3401	BNE.N	L_fe_invert5
3402#endif
3403	ADD	r2, sp, #0x20
3404	ADD	r1, sp, #0x40
3405	ADD	r0, sp, #0x40
3406	BL	fe_mul_op
3407	ADD	r1, sp, #0x40
3408	ADD	r0, sp, #0x60
3409	BL	fe_sq_op
3410	MOV	r12, #0x63
3411L_fe_invert6:
3412	ADD	r1, sp, #0x60
3413	ADD	r0, sp, #0x60
3414	PUSH	{r12}
3415	BL	fe_sq_op
3416	POP	{r12}
3417	SUBS	r12, r12, #0x1
3418#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3419	BNE	L_fe_invert6
3420#else
3421	BNE.N	L_fe_invert6
3422#endif
3423	ADD	r2, sp, #0x40
3424	ADD	r1, sp, #0x60
3425	ADD	r0, sp, #0x40
3426	BL	fe_mul_op
3427	MOV	r12, #0x32
3428L_fe_invert7:
3429	ADD	r1, sp, #0x40
3430	ADD	r0, sp, #0x40
3431	PUSH	{r12}
3432	BL	fe_sq_op
3433	POP	{r12}
3434	SUBS	r12, r12, #0x1
3435#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3436	BNE	L_fe_invert7
3437#else
3438	BNE.N	L_fe_invert7
3439#endif
3440	ADD	r2, sp, #0x20
3441	ADD	r1, sp, #0x40
3442	ADD	r0, sp, #0x20
3443	BL	fe_mul_op
3444	MOV	r12, #0x5
3445L_fe_invert8:
3446	ADD	r1, sp, #0x20
3447	ADD	r0, sp, #0x20
3448	PUSH	{r12}
3449	BL	fe_sq_op
3450	POP	{r12}
3451	SUBS	r12, r12, #0x1
3452#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3453	BNE	L_fe_invert8
3454#else
3455	BNE.N	L_fe_invert8
3456#endif
3457	MOV	r2, sp
3458	ADD	r1, sp, #0x20
3459	LDR	r0, [sp, #128]
3460	BL	fe_mul_op
3461	LDR	r1, [sp, #132]
3462	LDR	r0, [sp, #128]
3463	ADD	sp, sp, #0x88
3464	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
3465	/* Cycle Count = 292 */
3466	.size	fe_invert,.-fe_invert
3467#ifdef WOLFSSL_ARM_ARCH_7M
3468	.text
3469	.align	4
3470	.globl	fe_sq2
3471	.type	fe_sq2, %function
3472fe_sq2:
3473	PUSH	{lr}
3474	SUB	sp, sp, #0x44
3475	STR	r0, [sp, #64]
3476	/* Square * 2 */
3477	MOV	r0, #0x0
3478	LDR	r12, [r1]
3479	/* A[0] * A[1] */
3480	LDR	lr, [r1, #4]
3481	UMULL	r4, r5, r12, lr
3482	/* A[0] * A[3] */
3483	LDR	lr, [r1, #12]
3484	UMULL	r6, r7, r12, lr
3485	/* A[0] * A[5] */
3486	LDR	lr, [r1, #20]
3487	UMULL	r8, r9, r12, lr
3488	/* A[0] * A[7] */
3489	LDR	lr, [r1, #28]
3490	UMULL	r10, r3, r12, lr
3491	/* A[0] * A[2] */
3492	LDR	lr, [r1, #8]
3493	MOV	r11, #0x0
3494	UMLAL	r5, r11, r12, lr
3495	ADDS	r6, r6, r11
3496	/* A[0] * A[4] */
3497	LDR	lr, [r1, #16]
3498	ADCS	r7, r7, #0x0
3499	ADC	r11, r0, #0x0
3500	UMLAL	r7, r11, r12, lr
3501	ADDS	r8, r8, r11
3502	/* A[0] * A[6] */
3503	LDR	lr, [r1, #24]
3504	ADCS	r9, r9, #0x0
3505	ADC	r11, r0, #0x0
3506	UMLAL	r9, r11, r12, lr
3507	ADDS	r10, r10, r11
3508	ADCS	r3, r3, #0x0
3509	STR	r4, [sp, #4]
3510	STR	r5, [sp, #8]
3511	/* A[1] * A[2] */
3512	LDR	r12, [r1, #4]
3513	LDR	lr, [r1, #8]
3514	MOV	r11, #0x0
3515	UMLAL	r6, r11, r12, lr
3516	STR	r6, [sp, #12]
3517	ADDS	r7, r7, r11
3518	/* A[1] * A[3] */
3519	LDR	lr, [r1, #12]
3520	ADC	r11, r0, #0x0
3521	UMLAL	r7, r11, r12, lr
3522	STR	r7, [sp, #16]
3523	ADDS	r8, r8, r11
3524	/* A[1] * A[4] */
3525	LDR	lr, [r1, #16]
3526	ADC	r11, r0, #0x0
3527	UMLAL	r8, r11, r12, lr
3528	ADDS	r9, r9, r11
3529	/* A[1] * A[5] */
3530	LDR	lr, [r1, #20]
3531	ADC	r11, r0, #0x0
3532	UMLAL	r9, r11, r12, lr
3533	ADDS	r10, r10, r11
3534	/* A[1] * A[6] */
3535	LDR	lr, [r1, #24]
3536	ADC	r11, r0, #0x0
3537	UMLAL	r10, r11, r12, lr
3538	ADDS	r3, r3, r11
3539	/* A[1] * A[7] */
3540	LDR	lr, [r1, #28]
3541	ADC	r4, r0, #0x0
3542	UMLAL	r3, r4, r12, lr
3543	/* A[2] * A[3] */
3544	LDR	r12, [r1, #8]
3545	LDR	lr, [r1, #12]
3546	MOV	r11, #0x0
3547	UMLAL	r8, r11, r12, lr
3548	STR	r8, [sp, #20]
3549	ADDS	r9, r9, r11
3550	/* A[2] * A[4] */
3551	LDR	lr, [r1, #16]
3552	ADC	r11, r0, #0x0
3553	UMLAL	r9, r11, r12, lr
3554	STR	r9, [sp, #24]
3555	ADDS	r10, r10, r11
3556	/* A[2] * A[5] */
3557	LDR	lr, [r1, #20]
3558	ADC	r11, r0, #0x0
3559	UMLAL	r10, r11, r12, lr
3560	ADDS	r3, r3, r11
3561	/* A[2] * A[6] */
3562	LDR	lr, [r1, #24]
3563	ADC	r11, r0, #0x0
3564	UMLAL	r3, r11, r12, lr
3565	ADDS	r4, r4, r11
3566	/* A[2] * A[7] */
3567	LDR	lr, [r1, #28]
3568	ADC	r5, r0, #0x0
3569	UMLAL	r4, r5, r12, lr
3570	/* A[3] * A[4] */
3571	LDR	r12, [r1, #12]
3572	LDR	lr, [r1, #16]
3573	MOV	r11, #0x0
3574	UMLAL	r10, r11, r12, lr
3575	STR	r10, [sp, #28]
3576	ADDS	r3, r3, r11
3577	/* A[3] * A[5] */
3578	LDR	lr, [r1, #20]
3579	ADC	r11, r0, #0x0
3580	UMLAL	r3, r11, r12, lr
3581	ADDS	r4, r4, r11
3582	/* A[3] * A[6] */
3583	LDR	lr, [r1, #24]
3584	ADC	r11, r0, #0x0
3585	UMLAL	r4, r11, r12, lr
3586	ADDS	r5, r5, r11
3587	/* A[3] * A[7] */
3588	LDR	lr, [r1, #28]
3589	ADC	r6, r0, #0x0
3590	UMLAL	r5, r6, r12, lr
3591	/* A[4] * A[5] */
3592	LDR	r12, [r1, #16]
3593	LDR	lr, [r1, #20]
3594	MOV	r11, #0x0
3595	UMLAL	r4, r11, r12, lr
3596	ADDS	r5, r5, r11
3597	/* A[4] * A[6] */
3598	LDR	lr, [r1, #24]
3599	ADC	r11, r0, #0x0
3600	UMLAL	r5, r11, r12, lr
3601	ADDS	r6, r6, r11
3602	/* A[4] * A[7] */
3603	LDR	lr, [r1, #28]
3604	ADC	r7, r0, #0x0
3605	UMLAL	r6, r7, r12, lr
3606	/* A[5] * A[6] */
3607	LDR	r12, [r1, #20]
3608	LDR	lr, [r1, #24]
3609	MOV	r11, #0x0
3610	UMLAL	r6, r11, r12, lr
3611	ADDS	r7, r7, r11
3612	/* A[5] * A[7] */
3613	LDR	lr, [r1, #28]
3614	ADC	r8, r0, #0x0
3615	UMLAL	r7, r8, r12, lr
3616	/* A[6] * A[7] */
3617	LDR	r12, [r1, #24]
3618	LDR	lr, [r1, #28]
3619	MOV	r9, #0x0
3620	UMLAL	r8, r9, r12, lr
3621	ADD	lr, sp, #0x20
3622	STM	lr, {r3, r4, r5, r6, r7, r8, r9}
3623	ADD	lr, sp, #0x4
3624	LDM	lr, {r4, r5, r6, r7, r8, r9, r10}
3625	ADDS	r4, r4, r4
3626	ADCS	r5, r5, r5
3627	ADCS	r6, r6, r6
3628	ADCS	r7, r7, r7
3629	ADCS	r8, r8, r8
3630	ADCS	r9, r9, r9
3631	ADCS	r10, r10, r10
3632	STM	lr!, {r4, r5, r6, r7, r8, r9, r10}
3633	LDM	lr, {r3, r4, r5, r6, r7, r8, r9}
3634	ADCS	r3, r3, r3
3635	ADCS	r4, r4, r4
3636	ADCS	r5, r5, r5
3637	ADCS	r6, r6, r6
3638	ADCS	r7, r7, r7
3639	ADCS	r8, r8, r8
3640	ADCS	r9, r9, r9
3641	ADC	r10, r0, #0x0
3642	STM	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
3643	ADD	lr, sp, #0x4
3644	LDM	lr, {r4, r5, r6, r7, r8, r9, r10}
3645	MOV	lr, sp
3646	/* A[0] * A[0] */
3647	LDR	r12, [r1]
3648	UMULL	r3, r11, r12, r12
3649	ADDS	r4, r4, r11
3650	/* A[1] * A[1] */
3651	LDR	r12, [r1, #4]
3652	ADCS	r5, r5, #0x0
3653	ADC	r11, r0, #0x0
3654	UMLAL	r5, r11, r12, r12
3655	ADDS	r6, r6, r11
3656	/* A[2] * A[2] */
3657	LDR	r12, [r1, #8]
3658	ADCS	r7, r7, #0x0
3659	ADC	r11, r0, #0x0
3660	UMLAL	r7, r11, r12, r12
3661	ADDS	r8, r8, r11
3662	/* A[3] * A[3] */
3663	LDR	r12, [r1, #12]
3664	ADCS	r9, r9, #0x0
3665	ADC	r11, r0, #0x0
3666	UMLAL	r9, r11, r12, r12
3667	ADDS	r10, r10, r11
3668	STM	lr!, {r3, r4, r5, r6, r7, r8, r9, r10}
3669	LDM	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
3670	/* A[4] * A[4] */
3671	LDR	r12, [r1, #16]
3672	ADCS	r3, r3, #0x0
3673	ADC	r11, r0, #0x0
3674	UMLAL	r3, r11, r12, r12
3675	ADDS	r4, r4, r11
3676	/* A[5] * A[5] */
3677	LDR	r12, [r1, #20]
3678	ADCS	r5, r5, #0x0
3679	ADC	r11, r0, #0x0
3680	UMLAL	r5, r11, r12, r12
3681	ADDS	r6, r6, r11
3682	/* A[6] * A[6] */
3683	LDR	r12, [r1, #24]
3684	ADCS	r7, r7, #0x0
3685	ADC	r11, r0, #0x0
3686	UMLAL	r7, r11, r12, r12
3687	ADDS	r8, r8, r11
3688	/* A[7] * A[7] */
3689	LDR	r12, [r1, #28]
3690	ADCS	r9, r9, #0x0
3691	ADC	r10, r10, #0x0
3692	UMLAL	r9, r10, r12, r12
3693	/* Reduce */
3694	LDR	r2, [sp, #28]
3695	MOV	lr, sp
3696	MOV	r12, #0x26
3697	UMULL	r10, r11, r10, r12
3698	ADDS	r10, r10, r2
3699	ADC	r11, r11, #0x0
3700	MOV	r12, #0x13
3701	LSL	r11, r11, #1
3702	ORR	r11, r11, r10, LSR #31
3703	MUL	r11, r11, r12
3704	LDM	lr!, {r1, r2}
3705	MOV	r12, #0x26
3706	ADDS	r1, r1, r11
3707	ADC	r11, r0, #0x0
3708	UMLAL	r1, r11, r3, r12
3709	ADDS	r2, r2, r11
3710	ADC	r11, r0, #0x0
3711	UMLAL	r2, r11, r4, r12
3712	LDM	lr!, {r3, r4}
3713	ADDS	r3, r3, r11
3714	ADC	r11, r0, #0x0
3715	UMLAL	r3, r11, r5, r12
3716	ADDS	r4, r4, r11
3717	ADC	r11, r0, #0x0
3718	UMLAL	r4, r11, r6, r12
3719	LDM	lr!, {r5, r6}
3720	ADDS	r5, r5, r11
3721	ADC	r11, r0, #0x0
3722	UMLAL	r5, r11, r7, r12
3723	ADDS	r6, r6, r11
3724	ADC	r11, r0, #0x0
3725	UMLAL	r6, r11, r8, r12
3726	LDM	lr!, {r7, r8}
3727	ADDS	r7, r7, r11
3728	ADC	r11, r0, #0x0
3729	UMLAL	r7, r11, r9, r12
3730	BFC	r10, #31, #1
3731	ADDS	r8, r10, r11
3732	/* Reduce if top bit set */
3733	MOV	r12, #0x13
3734	AND	r11, r12, r8, ASR #31
3735	ADDS	r1, r1, r11
3736	ADCS	r2, r2, #0x0
3737	ADCS	r3, r3, #0x0
3738	ADCS	r4, r4, #0x0
3739	ADCS	r5, r5, #0x0
3740	ADCS	r6, r6, #0x0
3741	BFC	r8, #31, #1
3742	ADCS	r7, r7, #0x0
3743	ADC	r8, r8, #0x0
3744	/* Double */
3745	ADDS	r1, r1, r1
3746	ADCS	r2, r2, r2
3747	ADCS	r3, r3, r3
3748	ADCS	r4, r4, r4
3749	ADCS	r5, r5, r5
3750	ADCS	r6, r6, r6
3751	ADCS	r7, r7, r7
3752	ADC	r8, r8, r8
3753	/* Reduce if top bit set */
3754	MOV	r12, #0x13
3755	AND	r11, r12, r8, ASR #31
3756	ADDS	r1, r1, r11
3757	ADCS	r2, r2, #0x0
3758	ADCS	r3, r3, #0x0
3759	ADCS	r4, r4, #0x0
3760	ADCS	r5, r5, #0x0
3761	ADCS	r6, r6, #0x0
3762	BFC	r8, #31, #1
3763	ADCS	r7, r7, #0x0
3764	ADC	r8, r8, #0x0
3765	/* Store */
3766	LDR	r0, [sp, #64]
3767	STM	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
3768	ADD	sp, sp, #0x44
3769	POP	{pc}
3770	/* Cycle Count = 385 */
3771	.size	fe_sq2,.-fe_sq2
3772#else
3773	.text
3774	.align	4
3775	.globl	fe_sq2
3776	.type	fe_sq2, %function
3777fe_sq2:
3778	PUSH	{lr}
3779	SUB	sp, sp, #0x24
3780	STRD	r0, r1, [sp, #28]
3781	LDM	r1, {r0, r1, r2, r3, r4, r5, r6, r7}
3782	/* Square * 2 */
3783	UMULL	r9, r10, r0, r0
3784	UMULL	r11, r12, r0, r1
3785	ADDS	r11, r11, r11
3786	MOV	lr, #0x0
3787	UMAAL	r10, r11, lr, lr
3788	STM	sp, {r9, r10}
3789	MOV	r8, lr
3790	UMAAL	r8, r12, r0, r2
3791	ADCS	r8, r8, r8
3792	UMAAL	r8, r11, r1, r1
3793	UMULL	r9, r10, r0, r3
3794	UMAAL	r9, r12, r1, r2
3795	ADCS	r9, r9, r9
3796	UMAAL	r9, r11, lr, lr
3797	STRD	r8, r9, [sp, #8]
3798	MOV	r9, lr
3799	UMAAL	r9, r10, r0, r4
3800	UMAAL	r9, r12, r1, r3
3801	ADCS	r9, r9, r9
3802	UMAAL	r9, r11, r2, r2
3803	STR	r9, [sp, #16]
3804	UMULL	r9, r8, r0, r5
3805	UMAAL	r9, r12, r1, r4
3806	UMAAL	r9, r10, r2, r3
3807	ADCS	r9, r9, r9
3808	UMAAL	r9, r11, lr, lr
3809	STR	r9, [sp, #20]
3810	MOV	r9, lr
3811	UMAAL	r9, r8, r0, r6
3812	UMAAL	r9, r12, r1, r5
3813	UMAAL	r9, r10, r2, r4
3814	ADCS	r9, r9, r9
3815	UMAAL	r9, r11, r3, r3
3816	STR	r9, [sp, #24]
3817	UMULL	r0, r9, r0, r7
3818	UMAAL	r0, r8, r1, r6
3819	UMAAL	r0, r12, r2, r5
3820	UMAAL	r0, r10, r3, r4
3821	ADCS	r0, r0, r0
3822	UMAAL	r0, r11, lr, lr
3823	/* R[7] = r0 */
3824	UMAAL	r9, r8, r1, r7
3825	UMAAL	r9, r10, r2, r6
3826	UMAAL	r12, r9, r3, r5
3827	ADCS	r12, r12, r12
3828	UMAAL	r12, r11, r4, r4
3829	/* R[8] = r12 */
3830	UMAAL	r9, r8, r2, r7
3831	UMAAL	r10, r9, r3, r6
3832	MOV	r2, lr
3833	UMAAL	r10, r2, r4, r5
3834	ADCS	r10, r10, r10
3835	UMAAL	r11, r10, lr, lr
3836	/* R[9] = r11 */
3837	UMAAL	r2, r8, r3, r7
3838	UMAAL	r2, r9, r4, r6
3839	ADCS	r3, r2, r2
3840	UMAAL	r10, r3, r5, r5
3841	/* R[10] = r10 */
3842	MOV	r1, lr
3843	UMAAL	r1, r8, r4, r7
3844	UMAAL	r1, r9, r5, r6
3845	ADCS	r4, r1, r1
3846	UMAAL	r3, r4, lr, lr
3847	/* R[11] = r3 */
3848	UMAAL	r8, r9, r5, r7
3849	ADCS	r8, r8, r8
3850	UMAAL	r4, r8, r6, r6
3851	/* R[12] = r4 */
3852	MOV	r5, lr
3853	UMAAL	r5, r9, r6, r7
3854	ADCS	r5, r5, r5
3855	UMAAL	r8, r5, lr, lr
3856	/* R[13] = r8 */
3857	ADCS	r9, r9, r9
3858	UMAAL	r9, r5, r7, r7
3859	ADCS	r7, r5, lr
3860	/* R[14] = r9 */
3861	/* R[15] = r7 */
3862	/* Reduce */
3863	MOV	r6, #0x25
3864	UMAAL	r7, r0, r7, r6
3865	MOV	r6, #0x13
3866	LSL	r0, r0, #1
3867	ORR	r0, r0, r7, LSR #31
3868	MUL	lr, r0, r6
3869	POP	{r0, r1}
3870	MOV	r6, #0x26
3871	UMAAL	r0, lr, r12, r6
3872	UMAAL	r1, lr, r11, r6
3873	MOV	r12, r3
3874	MOV	r11, r4
3875	POP	{r2, r3, r4}
3876	UMAAL	r2, lr, r10, r6
3877	UMAAL	r3, lr, r12, r6
3878	UMAAL	r4, lr, r11, r6
3879	MOV	r12, r6
3880	POP	{r5, r6}
3881	UMAAL	r5, lr, r8, r12
3882	BFC	r7, #31, #1
3883	UMAAL	r6, lr, r9, r12
3884	ADD	r7, r7, lr
3885	/* Reduce if top bit set */
3886	MOV	r11, #0x13
3887	AND	r12, r11, r7, ASR #31
3888	ADDS	r0, r0, r12
3889	ADCS	r1, r1, #0x0
3890	ADCS	r2, r2, #0x0
3891	ADCS	r3, r3, #0x0
3892	ADCS	r4, r4, #0x0
3893	ADCS	r5, r5, #0x0
3894	BFC	r7, #31, #1
3895	ADCS	r6, r6, #0x0
3896	ADC	r7, r7, #0x0
3897	/* Double */
3898	ADDS	r0, r0, r0
3899	ADCS	r1, r1, r1
3900	ADCS	r2, r2, r2
3901	ADCS	r3, r3, r3
3902	ADCS	r4, r4, r4
3903	ADCS	r5, r5, r5
3904	ADCS	r6, r6, r6
3905	ADC	r7, r7, r7
3906	/* Reduce if top bit set */
3907	MOV	r11, #0x13
3908	AND	r12, r11, r7, ASR #31
3909	ADDS	r0, r0, r12
3910	ADCS	r1, r1, #0x0
3911	ADCS	r2, r2, #0x0
3912	ADCS	r3, r3, #0x0
3913	ADCS	r4, r4, #0x0
3914	ADCS	r5, r5, #0x0
3915	BFC	r7, #31, #1
3916	ADCS	r6, r6, #0x0
3917	ADC	r7, r7, #0x0
3918	POP	{r12, lr}
3919	/* Store */
3920	STM	r12, {r0, r1, r2, r3, r4, r5, r6, r7}
3921	MOV	r0, r12
3922	MOV	r1, lr
3923	POP	{pc}
3924	/* Cycle Count = 213 */
3925	.size	fe_sq2,.-fe_sq2
3926#endif /* WOLFSSL_ARM_ARCH_7M */
3927	.text
3928	.align	4
3929	.globl	fe_pow22523
3930	.type	fe_pow22523, %function
3931fe_pow22523:
3932	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
3933	SUB	sp, sp, #0x68
3934	/* pow22523 */
3935	STR	r0, [sp, #96]
3936	STR	r1, [sp, #100]
3937	LDR	r1, [sp, #100]
3938	MOV	r0, sp
3939	BL	fe_sq_op
3940	MOV	r1, sp
3941	ADD	r0, sp, #0x20
3942	BL	fe_sq_op
3943	ADD	r1, sp, #0x20
3944	ADD	r0, sp, #0x20
3945	BL	fe_sq_op
3946	ADD	r2, sp, #0x20
3947	LDR	r1, [sp, #100]
3948	ADD	r0, sp, #0x20
3949	BL	fe_mul_op
3950	ADD	r2, sp, #0x20
3951	MOV	r1, sp
3952	MOV	r0, sp
3953	BL	fe_mul_op
3954	MOV	r1, sp
3955	MOV	r0, sp
3956	BL	fe_sq_op
3957	MOV	r2, sp
3958	ADD	r1, sp, #0x20
3959	MOV	r0, sp
3960	BL	fe_mul_op
3961	MOV	r1, sp
3962	ADD	r0, sp, #0x20
3963	BL	fe_sq_op
3964	MOV	r12, #0x4
3965L_fe_pow22523_1:
3966	ADD	r1, sp, #0x20
3967	ADD	r0, sp, #0x20
3968	PUSH	{r12}
3969	BL	fe_sq_op
3970	POP	{r12}
3971	SUBS	r12, r12, #0x1
3972#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3973	BNE	L_fe_pow22523_1
3974#else
3975	BNE.N	L_fe_pow22523_1
3976#endif
3977	MOV	r2, sp
3978	ADD	r1, sp, #0x20
3979	MOV	r0, sp
3980	BL	fe_mul_op
3981	MOV	r1, sp
3982	ADD	r0, sp, #0x20
3983	BL	fe_sq_op
3984	MOV	r12, #0x9
3985L_fe_pow22523_2:
3986	ADD	r1, sp, #0x20
3987	ADD	r0, sp, #0x20
3988	PUSH	{r12}
3989	BL	fe_sq_op
3990	POP	{r12}
3991	SUBS	r12, r12, #0x1
3992#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3993	BNE	L_fe_pow22523_2
3994#else
3995	BNE.N	L_fe_pow22523_2
3996#endif
3997	MOV	r2, sp
3998	ADD	r1, sp, #0x20
3999	ADD	r0, sp, #0x20
4000	BL	fe_mul_op
4001	ADD	r1, sp, #0x20
4002	ADD	r0, sp, #0x40
4003	BL	fe_sq_op
4004	MOV	r12, #0x13
4005L_fe_pow22523_3:
4006	ADD	r1, sp, #0x40
4007	ADD	r0, sp, #0x40
4008	PUSH	{r12}
4009	BL	fe_sq_op
4010	POP	{r12}
4011	SUBS	r12, r12, #0x1
4012#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
4013	BNE	L_fe_pow22523_3
4014#else
4015	BNE.N	L_fe_pow22523_3
4016#endif
4017	ADD	r2, sp, #0x20
4018	ADD	r1, sp, #0x40
4019	ADD	r0, sp, #0x20
4020	BL	fe_mul_op
4021	MOV	r12, #0xa
4022L_fe_pow22523_4:
4023	ADD	r1, sp, #0x20
4024	ADD	r0, sp, #0x20
4025	PUSH	{r12}
4026	BL	fe_sq_op
4027	POP	{r12}
4028	SUBS	r12, r12, #0x1
4029#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
4030	BNE	L_fe_pow22523_4
4031#else
4032	BNE.N	L_fe_pow22523_4
4033#endif
4034	MOV	r2, sp
4035	ADD	r1, sp, #0x20
4036	MOV	r0, sp
4037	BL	fe_mul_op
4038	MOV	r1, sp
4039	ADD	r0, sp, #0x20
4040	BL	fe_sq_op
4041	MOV	r12, #0x31
4042L_fe_pow22523_5:
4043	ADD	r1, sp, #0x20
4044	ADD	r0, sp, #0x20
4045	PUSH	{r12}
4046	BL	fe_sq_op
4047	POP	{r12}
4048	SUBS	r12, r12, #0x1
4049#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
4050	BNE	L_fe_pow22523_5
4051#else
4052	BNE.N	L_fe_pow22523_5
4053#endif
4054	MOV	r2, sp
4055	ADD	r1, sp, #0x20
4056	ADD	r0, sp, #0x20
4057	BL	fe_mul_op
4058	ADD	r1, sp, #0x20
4059	ADD	r0, sp, #0x40
4060	BL	fe_sq_op
4061	MOV	r12, #0x63
4062L_fe_pow22523_6:
4063	ADD	r1, sp, #0x40
4064	ADD	r0, sp, #0x40
4065	PUSH	{r12}
4066	BL	fe_sq_op
4067	POP	{r12}
4068	SUBS	r12, r12, #0x1
4069#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
4070	BNE	L_fe_pow22523_6
4071#else
4072	BNE.N	L_fe_pow22523_6
4073#endif
4074	ADD	r2, sp, #0x20
4075	ADD	r1, sp, #0x40
4076	ADD	r0, sp, #0x20
4077	BL	fe_mul_op
4078	MOV	r12, #0x32
4079L_fe_pow22523_7:
4080	ADD	r1, sp, #0x20
4081	ADD	r0, sp, #0x20
4082	PUSH	{r12}
4083	BL	fe_sq_op
4084	POP	{r12}
4085	SUBS	r12, r12, #0x1
4086#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
4087	BNE	L_fe_pow22523_7
4088#else
4089	BNE.N	L_fe_pow22523_7
4090#endif
4091	MOV	r2, sp
4092	ADD	r1, sp, #0x20
4093	MOV	r0, sp
4094	BL	fe_mul_op
4095	MOV	r12, #0x2
4096L_fe_pow22523_8:
4097	MOV	r1, sp
4098	MOV	r0, sp
4099	PUSH	{r12}
4100	BL	fe_sq_op
4101	POP	{r12}
4102	SUBS	r12, r12, #0x1
4103#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
4104	BNE	L_fe_pow22523_8
4105#else
4106	BNE.N	L_fe_pow22523_8
4107#endif
4108	LDR	r2, [sp, #100]
4109	MOV	r1, sp
4110	LDR	r0, [sp, #96]
4111	BL	fe_mul_op
4112	LDR	r1, [sp, #100]
4113	LDR	r0, [sp, #96]
4114	ADD	sp, sp, #0x68
4115	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4116	/* Cycle Count = 293 */
4117	.size	fe_pow22523,.-fe_pow22523
4118	.text
4119	.align	4
4120	.globl	ge_p1p1_to_p2
4121	.type	ge_p1p1_to_p2, %function
4122ge_p1p1_to_p2:
4123	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4124	SUB	sp, sp, #0x8
4125	STR	r0, [sp]
4126	STR	r1, [sp, #4]
4127	ADD	r2, r1, #0x60
4128	BL	fe_mul_op
4129	LDR	r0, [sp]
4130	LDR	r1, [sp, #4]
4131	ADD	r2, r1, #0x40
4132	ADD	r1, r1, #0x20
4133	ADD	r0, r0, #0x20
4134	BL	fe_mul_op
4135	LDR	r0, [sp]
4136	LDR	r1, [sp, #4]
4137	ADD	r2, r1, #0x60
4138	ADD	r1, r1, #0x40
4139	ADD	r0, r0, #0x40
4140	BL	fe_mul_op
4141	ADD	sp, sp, #0x8
4142	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4143	/* Cycle Count = 53 */
4144	.size	ge_p1p1_to_p2,.-ge_p1p1_to_p2
4145	.text
4146	.align	4
4147	.globl	ge_p1p1_to_p3
4148	.type	ge_p1p1_to_p3, %function
4149ge_p1p1_to_p3:
4150	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4151	SUB	sp, sp, #0x8
4152	STR	r0, [sp]
4153	STR	r1, [sp, #4]
4154	ADD	r2, r1, #0x60
4155	BL	fe_mul_op
4156	LDR	r0, [sp]
4157	LDR	r1, [sp, #4]
4158	ADD	r2, r1, #0x40
4159	ADD	r1, r1, #0x20
4160	ADD	r0, r0, #0x20
4161	BL	fe_mul_op
4162	LDR	r0, [sp]
4163	LDR	r1, [sp, #4]
4164	ADD	r2, r1, #0x60
4165	ADD	r1, r1, #0x40
4166	ADD	r0, r0, #0x40
4167	BL	fe_mul_op
4168	LDR	r0, [sp]
4169	LDR	r1, [sp, #4]
4170	ADD	r2, r1, #0x20
4171	ADD	r0, r0, #0x60
4172	BL	fe_mul_op
4173	ADD	sp, sp, #0x8
4174	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4175	/* Cycle Count = 63 */
4176	.size	ge_p1p1_to_p3,.-ge_p1p1_to_p3
4177	.text
4178	.align	4
4179	.globl	ge_p2_dbl
4180	.type	ge_p2_dbl, %function
4181ge_p2_dbl:
4182	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4183	SUB	sp, sp, #0x8
4184	STR	r0, [sp]
4185	STR	r1, [sp, #4]
4186	BL	fe_sq_op
4187	LDR	r0, [sp]
4188	LDR	r1, [sp, #4]
4189	ADD	r1, r1, #0x20
4190	ADD	r0, r0, #0x40
4191	BL	fe_sq_op
4192	LDR	r0, [sp]
4193	LDR	r1, [sp, #4]
4194	ADD	r2, r1, #0x20
4195	ADD	r0, r0, #0x20
4196	BL	fe_add_op
4197	MOV	r1, r0
4198	ADD	r0, r0, #0x40
4199	BL	fe_sq_op
4200	LDR	r0, [sp]
4201	MOV	r3, r0
4202	ADD	r2, r0, #0x40
4203	ADD	r1, r0, #0x40
4204	ADD	r0, r0, #0x20
4205	BL	fe_add_sub_op
4206	MOV	r2, r0
4207	ADD	r1, r0, #0x40
4208	SUB	r0, r0, #0x20
4209	BL	fe_sub_op
4210	LDR	r1, [sp, #4]
4211	ADD	r1, r1, #0x40
4212	ADD	r0, r0, #0x60
4213	BL	fe_sq2
4214	SUB	r2, r0, #0x20
4215	MOV	r1, r0
4216	BL	fe_sub_op
4217	ADD	sp, sp, #0x8
4218	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4219	/* Cycle Count = 87 */
4220	.size	ge_p2_dbl,.-ge_p2_dbl
4221	.text
4222	.align	4
4223	.globl	ge_madd
4224	.type	ge_madd, %function
4225ge_madd:
4226	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4227	SUB	sp, sp, #0xc
4228	STR	r0, [sp]
4229	STR	r1, [sp, #4]
4230	STR	r2, [sp, #8]
4231	MOV	r2, r1
4232	ADD	r1, r1, #0x20
4233	BL	fe_add_op
4234	LDR	r1, [sp, #4]
4235	MOV	r2, r1
4236	ADD	r1, r1, #0x20
4237	ADD	r0, r0, #0x20
4238	BL	fe_sub_op
4239	LDR	r2, [sp, #8]
4240	SUB	r1, r0, #0x20
4241	ADD	r0, r0, #0x20
4242	BL	fe_mul_op
4243	LDR	r0, [sp]
4244	LDR	r2, [sp, #8]
4245	ADD	r2, r2, #0x20
4246	ADD	r1, r0, #0x20
4247	ADD	r0, r0, #0x20
4248	BL	fe_mul_op
4249	LDR	r0, [sp]
4250	LDR	r1, [sp, #8]
4251	LDR	r2, [sp, #4]
4252	ADD	r2, r2, #0x60
4253	ADD	r1, r1, #0x40
4254	ADD	r0, r0, #0x60
4255	BL	fe_mul_op
4256	LDR	r0, [sp]
4257	ADD	r3, r0, #0x20
4258	ADD	r2, r0, #0x40
4259	MOV	r1, r0
4260	ADD	r0, r0, #0x20
4261	BL	fe_add_sub_op
4262	LDR	r1, [sp, #4]
4263	ADD	r1, r1, #0x40
4264	ADD	r0, r0, #0x20
4265	/* Double */
4266	LDM	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
4267	ADDS	r4, r4, r4
4268	ADCS	r5, r5, r5
4269	ADCS	r6, r6, r6
4270	ADCS	r7, r7, r7
4271	ADCS	r8, r8, r8
4272	ADCS	r9, r9, r9
4273	ADCS	r10, r10, r10
4274	MOV	lr, #0x0
4275	ADCS	r11, r11, r11
4276	ADC	lr, lr, #0x0
4277	MOV	r12, #0x13
4278	LSL	lr, lr, #1
4279	ORR	lr, lr, r11, LSR #31
4280	MUL	r12, lr, r12
4281	ADDS	r4, r4, r12
4282	ADCS	r5, r5, #0x0
4283	ADCS	r6, r6, #0x0
4284	ADCS	r7, r7, #0x0
4285	ADCS	r8, r8, #0x0
4286	ADCS	r9, r9, #0x0
4287	BFC	r11, #31, #1
4288	ADCS	r10, r10, #0x0
4289	ADC	r11, r11, #0x0
4290	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
4291	/* Done Double */
4292	ADD	r3, r0, #0x20
4293	ADD	r1, r0, #0x20
4294	BL	fe_add_sub_op
4295	ADD	sp, sp, #0xc
4296	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4297	/* Cycle Count = 136 */
4298	.size	ge_madd,.-ge_madd
4299	.text
4300	.align	4
4301	.globl	ge_msub
4302	.type	ge_msub, %function
4303ge_msub:
4304	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4305	SUB	sp, sp, #0xc
4306	STR	r0, [sp]
4307	STR	r1, [sp, #4]
4308	STR	r2, [sp, #8]
4309	MOV	r2, r1
4310	ADD	r1, r1, #0x20
4311	BL	fe_add_op
4312	LDR	r1, [sp, #4]
4313	MOV	r2, r1
4314	ADD	r1, r1, #0x20
4315	ADD	r0, r0, #0x20
4316	BL	fe_sub_op
4317	LDR	r2, [sp, #8]
4318	ADD	r2, r2, #0x20
4319	SUB	r1, r0, #0x20
4320	ADD	r0, r0, #0x20
4321	BL	fe_mul_op
4322	LDR	r0, [sp]
4323	LDR	r2, [sp, #8]
4324	ADD	r1, r0, #0x20
4325	ADD	r0, r0, #0x20
4326	BL	fe_mul_op
4327	LDR	r0, [sp]
4328	LDR	r1, [sp, #8]
4329	LDR	r2, [sp, #4]
4330	ADD	r2, r2, #0x60
4331	ADD	r1, r1, #0x40
4332	ADD	r0, r0, #0x60
4333	BL	fe_mul_op
4334	LDR	r0, [sp]
4335	ADD	r3, r0, #0x20
4336	ADD	r2, r0, #0x40
4337	MOV	r1, r0
4338	ADD	r0, r0, #0x20
4339	BL	fe_add_sub_op
4340	LDR	r1, [sp, #4]
4341	ADD	r1, r1, #0x40
4342	ADD	r0, r0, #0x20
4343	/* Double */
4344	LDM	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
4345	ADDS	r4, r4, r4
4346	ADCS	r5, r5, r5
4347	ADCS	r6, r6, r6
4348	ADCS	r7, r7, r7
4349	ADCS	r8, r8, r8
4350	ADCS	r9, r9, r9
4351	ADCS	r10, r10, r10
4352	MOV	lr, #0x0
4353	ADCS	r11, r11, r11
4354	ADC	lr, lr, #0x0
4355	MOV	r12, #0x13
4356	LSL	lr, lr, #1
4357	ORR	lr, lr, r11, LSR #31
4358	MUL	r12, lr, r12
4359	ADDS	r4, r4, r12
4360	ADCS	r5, r5, #0x0
4361	ADCS	r6, r6, #0x0
4362	ADCS	r7, r7, #0x0
4363	ADCS	r8, r8, #0x0
4364	ADCS	r9, r9, #0x0
4365	BFC	r11, #31, #1
4366	ADCS	r10, r10, #0x0
4367	ADC	r11, r11, #0x0
4368	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
4369	/* Done Double */
4370	ADD	r3, r0, #0x20
4371	MOV	r1, r0
4372	ADD	r0, r0, #0x20
4373	BL	fe_add_sub_op
4374	ADD	sp, sp, #0xc
4375	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4376	/* Cycle Count = 137 */
4377	.size	ge_msub,.-ge_msub
4378	.text
4379	.align	4
4380	.globl	ge_add
4381	.type	ge_add, %function
4382ge_add:
4383	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4384	SUB	sp, sp, #0x2c
4385	STR	r0, [sp]
4386	STR	r1, [sp, #4]
4387	STR	r2, [sp, #8]
4388	MOV	r3, r1
4389	ADD	r2, r1, #0x20
4390	ADD	r1, r0, #0x20
4391	BL	fe_add_sub_op
4392	LDR	r2, [sp, #8]
4393	MOV	r1, r0
4394	ADD	r0, r0, #0x40
4395	BL	fe_mul_op
4396	LDR	r0, [sp]
4397	LDR	r2, [sp, #8]
4398	ADD	r2, r2, #0x20
4399	ADD	r1, r0, #0x20
4400	ADD	r0, r0, #0x20
4401	BL	fe_mul_op
4402	LDR	r0, [sp]
4403	LDR	r1, [sp, #8]
4404	LDR	r2, [sp, #4]
4405	ADD	r2, r2, #0x60
4406	ADD	r1, r1, #0x60
4407	ADD	r0, r0, #0x60
4408	BL	fe_mul_op
4409	LDR	r0, [sp]
4410	LDR	r1, [sp, #4]
4411	LDR	r2, [sp, #8]
4412	ADD	r2, r2, #0x40
4413	ADD	r1, r1, #0x40
4414	BL	fe_mul_op
4415	LDR	r1, [sp]
4416	ADD	r0, sp, #0xc
4417	/* Double */
4418	LDM	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
4419	ADDS	r4, r4, r4
4420	ADCS	r5, r5, r5
4421	ADCS	r6, r6, r6
4422	ADCS	r7, r7, r7
4423	ADCS	r8, r8, r8
4424	ADCS	r9, r9, r9
4425	ADCS	r10, r10, r10
4426	MOV	lr, #0x0
4427	ADCS	r11, r11, r11
4428	ADC	lr, lr, #0x0
4429	MOV	r12, #0x13
4430	LSL	lr, lr, #1
4431	ORR	lr, lr, r11, LSR #31
4432	MUL	r12, lr, r12
4433	ADDS	r4, r4, r12
4434	ADCS	r5, r5, #0x0
4435	ADCS	r6, r6, #0x0
4436	ADCS	r7, r7, #0x0
4437	ADCS	r8, r8, #0x0
4438	ADCS	r9, r9, #0x0
4439	BFC	r11, #31, #1
4440	ADCS	r10, r10, #0x0
4441	ADC	r11, r11, #0x0
4442	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
4443	/* Done Double */
4444	ADD	r3, r1, #0x20
4445	ADD	r2, r1, #0x40
4446	ADD	r0, r1, #0x20
4447	BL	fe_add_sub_op
4448	ADD	r3, r0, #0x40
4449	ADD	r2, sp, #0xc
4450	ADD	r1, r0, #0x40
4451	ADD	r0, r0, #0x20
4452	BL	fe_add_sub_op
4453	ADD	sp, sp, #0x2c
4454	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4455	/* Cycle Count = 138 */
4456	.size	ge_add,.-ge_add
4457	.text
4458	.align	4
4459	.globl	ge_sub
4460	.type	ge_sub, %function
4461ge_sub:
4462	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4463	SUB	sp, sp, #0x2c
4464	STR	r0, [sp]
4465	STR	r1, [sp, #4]
4466	STR	r2, [sp, #8]
4467	MOV	r3, r1
4468	ADD	r2, r1, #0x20
4469	ADD	r1, r0, #0x20
4470	BL	fe_add_sub_op
4471	LDR	r2, [sp, #8]
4472	ADD	r2, r2, #0x20
4473	MOV	r1, r0
4474	ADD	r0, r0, #0x40
4475	BL	fe_mul_op
4476	LDR	r0, [sp]
4477	LDR	r2, [sp, #8]
4478	ADD	r1, r0, #0x20
4479	ADD	r0, r0, #0x20
4480	BL	fe_mul_op
4481	LDR	r0, [sp]
4482	LDR	r1, [sp, #8]
4483	LDR	r2, [sp, #4]
4484	ADD	r2, r2, #0x60
4485	ADD	r1, r1, #0x60
4486	ADD	r0, r0, #0x60
4487	BL	fe_mul_op
4488	LDR	r0, [sp]
4489	LDR	r1, [sp, #4]
4490	LDR	r2, [sp, #8]
4491	ADD	r2, r2, #0x40
4492	ADD	r1, r1, #0x40
4493	BL	fe_mul_op
4494	LDR	r1, [sp]
4495	ADD	r0, sp, #0xc
4496	/* Double */
4497	LDM	r1, {r4, r5, r6, r7, r8, r9, r10, r11}
4498	ADDS	r4, r4, r4
4499	ADCS	r5, r5, r5
4500	ADCS	r6, r6, r6
4501	ADCS	r7, r7, r7
4502	ADCS	r8, r8, r8
4503	ADCS	r9, r9, r9
4504	ADCS	r10, r10, r10
4505	MOV	lr, #0x0
4506	ADCS	r11, r11, r11
4507	ADC	lr, lr, #0x0
4508	MOV	r12, #0x13
4509	LSL	lr, lr, #1
4510	ORR	lr, lr, r11, LSR #31
4511	MUL	r12, lr, r12
4512	ADDS	r4, r4, r12
4513	ADCS	r5, r5, #0x0
4514	ADCS	r6, r6, #0x0
4515	ADCS	r7, r7, #0x0
4516	ADCS	r8, r8, #0x0
4517	ADCS	r9, r9, #0x0
4518	BFC	r11, #31, #1
4519	ADCS	r10, r10, #0x0
4520	ADC	r11, r11, #0x0
4521	STM	r0, {r4, r5, r6, r7, r8, r9, r10, r11}
4522	/* Done Double */
4523	ADD	r3, r1, #0x20
4524	ADD	r2, r1, #0x40
4525	ADD	r0, r1, #0x20
4526	BL	fe_add_sub_op
4527	ADD	r3, r0, #0x40
4528	ADD	r2, sp, #0xc
4529	ADD	r1, r0, #0x20
4530	ADD	r0, r0, #0x40
4531	BL	fe_add_sub_op
4532	ADD	sp, sp, #0x2c
4533	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4534	/* Cycle Count = 138 */
4535	.size	ge_sub,.-ge_sub
4536#endif /* HAVE_ED25519 || WOLFSSL_CURVE25519_USE_ED25519 */
4537#ifdef HAVE_ED25519
4538#ifdef WOLFSSL_ARM_ARCH_7M
4539	.text
4540	.align	4
4541	.globl	sc_reduce
4542	.type	sc_reduce, %function
4543sc_reduce:
4544	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4545	SUB	sp, sp, #0x38
4546	STR	r0, [sp, #52]
4547	/* Load bits 252-511 */
4548	ADD	r0, r0, #0x1c
4549	LDM	r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9}
4550	LSR	lr, r9, #24
4551	LSL	r9, r9, #4
4552	ORR	r9, r9, r8, LSR #28
4553	LSL	r8, r8, #4
4554	ORR	r8, r8, r7, LSR #28
4555	LSL	r7, r7, #4
4556	ORR	r7, r7, r6, LSR #28
4557	LSL	r6, r6, #4
4558	ORR	r6, r6, r5, LSR #28
4559	LSL	r5, r5, #4
4560	ORR	r5, r5, r4, LSR #28
4561	LSL	r4, r4, #4
4562	ORR	r4, r4, r3, LSR #28
4563	LSL	r3, r3, #4
4564	ORR	r3, r3, r2, LSR #28
4565	LSL	r2, r2, #4
4566	ORR	r2, r2, r1, LSR #28
4567	BFC	r9, #28, #4
4568	SUB	r0, r0, #0x1c
4569	/* Add order times bits 504..511 */
4570	MOV	r10, #0x2c13
4571	MOVT	r10, #0xa30a
4572	MOV	r11, #0x9ce5
4573	MOVT	r11, #0xa7ed
4574	MOV	r1, #0x0
4575	UMLAL	r2, r1, r10, lr
4576	ADDS	r3, r3, r1
4577	MOV	r1, #0x0
4578	ADC	r1, r1, #0x0
4579	UMLAL	r3, r1, r11, lr
4580	MOV	r10, #0x6329
4581	MOVT	r10, #0x5d08
4582	MOV	r11, #0x621
4583	MOVT	r11, #0xeb21
4584	ADDS	r4, r4, r1
4585	MOV	r1, #0x0
4586	ADC	r1, r1, #0x0
4587	UMLAL	r4, r1, r10, lr
4588	ADDS	r5, r5, r1
4589	MOV	r1, #0x0
4590	ADC	r1, r1, #0x0
4591	UMLAL	r5, r1, r11, lr
4592	ADDS	r6, r6, r1
4593	ADCS	r7, r7, #0x0
4594	ADCS	r8, r8, #0x0
4595	ADC	r9, r9, #0x0
4596	SUBS	r6, r6, lr
4597	SBCS	r7, r7, #0x0
4598	SBCS	r8, r8, #0x0
4599	SBC	r9, r9, #0x0
4600	/* Sub product of top 8 words and order */
4601	MOV	r12, sp
4602	MOV	r1, #0x2c13
4603	MOVT	r1, #0xa30a
4604	MOV	lr, #0x0
4605	LDM	r0!, {r10, r11}
4606	UMLAL	r10, lr, r2, r1
4607	ADDS	r11, r11, lr
4608	MOV	lr, #0x0
4609	ADC	lr, lr, #0x0
4610	UMLAL	r11, lr, r3, r1
4611	STM	r12!, {r10, r11}
4612	LDM	r0!, {r10, r11}
4613	ADDS	r10, r10, lr
4614	MOV	lr, #0x0
4615	ADC	lr, lr, #0x0
4616	UMLAL	r10, lr, r4, r1
4617	ADDS	r11, r11, lr
4618	MOV	lr, #0x0
4619	ADC	lr, lr, #0x0
4620	UMLAL	r11, lr, r5, r1
4621	STM	r12!, {r10, r11}
4622	LDM	r0!, {r10, r11}
4623	ADDS	r10, r10, lr
4624	MOV	lr, #0x0
4625	ADC	lr, lr, #0x0
4626	UMLAL	r10, lr, r6, r1
4627	ADDS	r11, r11, lr
4628	MOV	lr, #0x0
4629	ADC	lr, lr, #0x0
4630	UMLAL	r11, lr, r7, r1
4631	STM	r12!, {r10, r11}
4632	LDM	r0!, {r10, r11}
4633	ADDS	r10, r10, lr
4634	MOV	lr, #0x0
4635	ADC	lr, lr, #0x0
4636	UMLAL	r10, lr, r8, r1
4637	BFC	r11, #28, #4
4638	ADDS	r11, r11, lr
4639	MOV	lr, #0x0
4640	ADC	lr, lr, #0x0
4641	UMLAL	r11, lr, r9, r1
4642	STM	r12!, {r10, r11, lr}
4643	SUB	r0, r0, #0x10
4644	SUB	r12, r12, #0x20
4645	MOV	r1, #0x9ce5
4646	MOVT	r1, #0xa7ed
4647	MOV	lr, #0x0
4648	LDM	r12, {r10, r11}
4649	UMLAL	r10, lr, r2, r1
4650	ADDS	r11, r11, lr
4651	MOV	lr, #0x0
4652	ADC	lr, lr, #0x0
4653	UMLAL	r11, lr, r3, r1
4654	STM	r12!, {r10, r11}
4655	LDM	r12, {r10, r11}
4656	ADDS	r10, r10, lr
4657	MOV	lr, #0x0
4658	ADC	lr, lr, #0x0
4659	UMLAL	r10, lr, r4, r1
4660	ADDS	r11, r11, lr
4661	MOV	lr, #0x0
4662	ADC	lr, lr, #0x0
4663	UMLAL	r11, lr, r5, r1
4664	STM	r12!, {r10, r11}
4665	LDM	r12, {r10, r11}
4666	ADDS	r10, r10, lr
4667	MOV	lr, #0x0
4668	ADC	lr, lr, #0x0
4669	UMLAL	r10, lr, r6, r1
4670	ADDS	r11, r11, lr
4671	MOV	lr, #0x0
4672	ADC	lr, lr, #0x0
4673	UMLAL	r11, lr, r7, r1
4674	STM	r12!, {r10, r11}
4675	LDM	r12, {r10, r11}
4676	ADDS	r10, r10, lr
4677	MOV	lr, #0x0
4678	ADC	lr, lr, #0x0
4679	UMLAL	r10, lr, r8, r1
4680	ADDS	r11, r11, lr
4681	MOV	lr, #0x0
4682	ADC	lr, lr, #0x0
4683	UMLAL	r11, lr, r9, r1
4684	STM	r12!, {r10, r11, lr}
4685	SUB	r12, r12, #0x20
4686	MOV	r1, #0x6329
4687	MOVT	r1, #0x5d08
4688	MOV	lr, #0x0
4689	LDM	r12, {r10, r11}
4690	UMLAL	r10, lr, r2, r1
4691	ADDS	r11, r11, lr
4692	MOV	lr, #0x0
4693	ADC	lr, lr, #0x0
4694	UMLAL	r11, lr, r3, r1
4695	STM	r12!, {r10, r11}
4696	LDM	r12, {r10, r11}
4697	ADDS	r10, r10, lr
4698	MOV	lr, #0x0
4699	ADC	lr, lr, #0x0
4700	UMLAL	r10, lr, r4, r1
4701	ADDS	r11, r11, lr
4702	MOV	lr, #0x0
4703	ADC	lr, lr, #0x0
4704	UMLAL	r11, lr, r5, r1
4705	STM	r12!, {r10, r11}
4706	LDM	r12, {r10, r11}
4707	ADDS	r10, r10, lr
4708	MOV	lr, #0x0
4709	ADC	lr, lr, #0x0
4710	UMLAL	r10, lr, r6, r1
4711	ADDS	r11, r11, lr
4712	MOV	lr, #0x0
4713	ADC	lr, lr, #0x0
4714	UMLAL	r11, lr, r7, r1
4715	STM	r12!, {r10, r11}
4716	LDM	r12, {r10, r11}
4717	ADDS	r10, r10, lr
4718	MOV	lr, #0x0
4719	ADC	lr, lr, #0x0
4720	UMLAL	r10, lr, r8, r1
4721	ADDS	r11, r11, lr
4722	MOV	lr, #0x0
4723	ADC	lr, lr, #0x0
4724	UMLAL	r11, lr, r9, r1
4725	STM	r12!, {r10, r11, lr}
4726	SUB	r12, r12, #0x20
4727	MOV	r1, #0x621
4728	MOVT	r1, #0xeb21
4729	MOV	lr, #0x0
4730	LDM	r12, {r10, r11}
4731	UMLAL	r10, lr, r2, r1
4732	ADDS	r11, r11, lr
4733	MOV	lr, #0x0
4734	ADC	lr, lr, #0x0
4735	UMLAL	r11, lr, r3, r1
4736	STM	r12!, {r10, r11}
4737	LDM	r12, {r10, r11}
4738	ADDS	r10, r10, lr
4739	MOV	lr, #0x0
4740	ADC	lr, lr, #0x0
4741	UMLAL	r10, lr, r4, r1
4742	ADDS	r11, r11, lr
4743	MOV	lr, #0x0
4744	ADC	lr, lr, #0x0
4745	UMLAL	r11, lr, r5, r1
4746	STM	r12!, {r10, r11}
4747	LDM	r12, {r10, r11}
4748	ADDS	r10, r10, lr
4749	MOV	lr, #0x0
4750	ADC	lr, lr, #0x0
4751	UMLAL	r10, lr, r6, r1
4752	ADDS	r11, r11, lr
4753	MOV	lr, #0x0
4754	ADC	lr, lr, #0x0
4755	UMLAL	r11, lr, r7, r1
4756	STM	r12!, {r10, r11}
4757	LDM	r12, {r10, r11}
4758	ADDS	r10, r10, lr
4759	MOV	lr, #0x0
4760	ADC	lr, lr, #0x0
4761	UMLAL	r10, lr, r8, r1
4762	ADDS	r11, r11, lr
4763	MOV	lr, #0x0
4764	ADC	lr, lr, #0x0
4765	UMLAL	r11, lr, r9, r1
4766	STM	r12!, {r10, r11, lr}
4767	SUB	r12, r12, #0x20
4768	/* Subtract at 4 * 32 */
4769	LDM	r12, {r10, r11}
4770	SUBS	r10, r10, r2
4771	SBCS	r11, r11, r3
4772	STM	r12!, {r10, r11}
4773	LDM	r12, {r10, r11}
4774	SBCS	r10, r10, r4
4775	SBCS	r11, r11, r5
4776	STM	r12!, {r10, r11}
4777	LDM	r12, {r10, r11}
4778	SBCS	r10, r10, r6
4779	SBCS	r11, r11, r7
4780	STM	r12!, {r10, r11}
4781	LDM	r12, {r10, r11}
4782	SBCS	r10, r10, r8
4783	SBC	r11, r11, r9
4784	STM	r12!, {r10, r11}
4785	SUB	r12, r12, #0x24
4786	ASR	lr, r11, #25
4787	/* Conditionally subtract order starting at bit 125 */
4788	MOV	r1, #0xa0000000
4789	MOV	r2, #0xba7d
4790	MOVT	r2, #0x4b9e
4791	MOV	r3, #0x4c63
4792	MOVT	r3, #0xcb02
4793	MOV	r4, #0xf39a
4794	MOVT	r4, #0xd45e
4795	MOV	r5, #0xdf3b
4796	MOVT	r5, #0x29b
4797	MOV	r9, #0x2000000
4798	AND	r1, r1, lr
4799	AND	r2, r2, lr
4800	AND	r3, r3, lr
4801	AND	r4, r4, lr
4802	AND	r5, r5, lr
4803	AND	r9, r9, lr
4804	LDM	r12, {r10, r11}
4805	ADDS	r10, r10, r1
4806	ADCS	r11, r11, r2
4807	STM	r12!, {r10, r11}
4808	LDM	r12, {r10, r11}
4809	ADCS	r10, r10, r3
4810	ADCS	r11, r11, r4
4811	STM	r12!, {r10, r11}
4812	LDM	r12, {r10, r11}
4813	ADCS	r10, r10, r5
4814	ADCS	r11, r11, #0x0
4815	STM	r12!, {r10, r11}
4816	LDM	r12, {r10, r11}
4817	ADCS	r10, r10, #0x0
4818	ADCS	r11, r11, #0x0
4819	STM	r12!, {r10, r11}
4820	LDM	r12, {r10}
4821	ADCS	r10, r10, #0x0
4822	STM	r12!, {r10}
4823	SUB	r0, r0, #0x10
4824	MOV	r12, sp
4825	/* Load bits 252-376 */
4826	ADD	r12, r12, #0x1c
4827	LDM	r12, {r1, r2, r3, r4, r5}
4828	LSL	r5, r5, #4
4829	ORR	r5, r5, r4, LSR #28
4830	LSL	r4, r4, #4
4831	ORR	r4, r4, r3, LSR #28
4832	LSL	r3, r3, #4
4833	ORR	r3, r3, r2, LSR #28
4834	LSL	r2, r2, #4
4835	ORR	r2, r2, r1, LSR #28
4836	BFC	r5, #29, #3
4837	SUB	r12, r12, #0x1c
4838	/* Sub product of top 4 words and order */
4839	MOV	r0, sp
4840	/*   * -5cf5d3ed */
4841	MOV	r1, #0x2c13
4842	MOVT	r1, #0xa30a
4843	MOV	lr, #0x0
4844	LDM	r0, {r6, r7, r8, r9}
4845	UMLAL	r6, lr, r2, r1
4846	ADDS	r7, r7, lr
4847	MOV	lr, #0x0
4848	ADC	lr, lr, #0x0
4849	UMLAL	r7, lr, r3, r1
4850	ADDS	r8, r8, lr
4851	MOV	lr, #0x0
4852	ADC	lr, lr, #0x0
4853	UMLAL	r8, lr, r4, r1
4854	ADDS	r9, r9, lr
4855	MOV	lr, #0x0
4856	ADC	lr, lr, #0x0
4857	UMLAL	r9, lr, r5, r1
4858	STM	r0, {r6, r7, r8, r9}
4859	ADD	r0, r0, #0x4
4860	/*   * -5812631b */
4861	MOV	r1, #0x9ce5
4862	MOVT	r1, #0xa7ed
4863	MOV	r10, #0x0
4864	LDM	r0, {r6, r7, r8, r9}
4865	UMLAL	r6, r10, r2, r1
4866	ADDS	r7, r7, r10
4867	MOV	r10, #0x0
4868	ADC	r10, r10, #0x0
4869	UMLAL	r7, r10, r3, r1
4870	ADDS	r8, r8, r10
4871	MOV	r10, #0x0
4872	ADC	r10, r10, #0x0
4873	UMLAL	r8, r10, r4, r1
4874	ADDS	r9, r9, r10
4875	MOV	r10, #0x0
4876	ADC	r10, r10, #0x0
4877	UMLAL	r9, r10, r5, r1
4878	STM	r0, {r6, r7, r8, r9}
4879	ADD	r0, r0, #0x4
4880	/*   * -a2f79cd7 */
4881	MOV	r1, #0x6329
4882	MOVT	r1, #0x5d08
4883	MOV	r11, #0x0
4884	LDM	r0, {r6, r7, r8, r9}
4885	UMLAL	r6, r11, r2, r1
4886	ADDS	r7, r7, r11
4887	MOV	r11, #0x0
4888	ADC	r11, r11, #0x0
4889	UMLAL	r7, r11, r3, r1
4890	ADDS	r8, r8, r11
4891	MOV	r11, #0x0
4892	ADC	r11, r11, #0x0
4893	UMLAL	r8, r11, r4, r1
4894	ADDS	r9, r9, r11
4895	MOV	r11, #0x0
4896	ADC	r11, r11, #0x0
4897	UMLAL	r9, r11, r5, r1
4898	STM	r0, {r6, r7, r8, r9}
4899	ADD	r0, r0, #0x4
4900	/*   * -14def9df */
4901	MOV	r1, #0x621
4902	MOVT	r1, #0xeb21
4903	MOV	r12, #0x0
4904	LDM	r0, {r6, r7, r8, r9}
4905	UMLAL	r6, r12, r2, r1
4906	ADDS	r7, r7, r12
4907	MOV	r12, #0x0
4908	ADC	r12, r12, #0x0
4909	UMLAL	r7, r12, r3, r1
4910	ADDS	r8, r8, r12
4911	MOV	r12, #0x0
4912	ADC	r12, r12, #0x0
4913	UMLAL	r8, r12, r4, r1
4914	ADDS	r9, r9, r12
4915	MOV	r12, #0x0
4916	ADC	r12, r12, #0x0
4917	UMLAL	r9, r12, r5, r1
4918	STM	r0, {r6, r7, r8, r9}
4919	ADD	r0, r0, #0x4
4920	/* Add overflows at 4 * 32 */
4921	LDM	r0, {r6, r7, r8, r9}
4922	BFC	r9, #28, #4
4923	ADDS	r6, r6, lr
4924	ADCS	r7, r7, r10
4925	ADCS	r8, r8, r11
4926	ADC	r9, r9, r12
4927	/* Subtract top at 4 * 32 */
4928	SUBS	r6, r6, r2
4929	SBCS	r7, r7, r3
4930	SBCS	r8, r8, r4
4931	SBCS	r9, r9, r5
4932	SBC	r1, r1, r1
4933	SUB	r0, r0, #0x10
4934	LDM	r0, {r2, r3, r4, r5}
4935	MOV	r10, #0xd3ed
4936	MOVT	r10, #0x5cf5
4937	MOV	r11, #0x631a
4938	MOVT	r11, #0x5812
4939	MOV	r12, #0x9cd6
4940	MOVT	r12, #0xa2f7
4941	MOV	lr, #0xf9de
4942	MOVT	lr, #0x14de
4943	AND	r10, r10, r1
4944	AND	r11, r11, r1
4945	AND	r12, r12, r1
4946	AND	lr, lr, r1
4947	ADDS	r2, r2, r10
4948	ADCS	r3, r3, r11
4949	ADCS	r4, r4, r12
4950	ADCS	r5, r5, lr
4951	ADCS	r6, r6, #0x0
4952	ADCS	r7, r7, #0x0
4953	AND	r1, r1, #0x10000000
4954	ADCS	r8, r8, #0x0
4955	ADC	r9, r9, r1
4956	BFC	r9, #28, #4
4957	/* Store result */
4958	LDR	r0, [sp, #52]
4959	STM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
4960	ADD	sp, sp, #0x38
4961	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
4962	/* Cycle Count = 588 */
4963	.size	sc_reduce,.-sc_reduce
4964#else
4965	.text
4966	.align	4
4967	.globl	sc_reduce
4968	.type	sc_reduce, %function
4969sc_reduce:
4970	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
4971	SUB	sp, sp, #0x38
4972	STR	r0, [sp, #52]
4973	/* Load bits 252-511 */
4974	ADD	r0, r0, #0x1c
4975	LDM	r0, {r1, r2, r3, r4, r5, r6, r7, r8, r9}
4976	LSR	lr, r9, #24
4977	LSL	r9, r9, #4
4978	ORR	r9, r9, r8, LSR #28
4979	LSL	r8, r8, #4
4980	ORR	r8, r8, r7, LSR #28
4981	LSL	r7, r7, #4
4982	ORR	r7, r7, r6, LSR #28
4983	LSL	r6, r6, #4
4984	ORR	r6, r6, r5, LSR #28
4985	LSL	r5, r5, #4
4986	ORR	r5, r5, r4, LSR #28
4987	LSL	r4, r4, #4
4988	ORR	r4, r4, r3, LSR #28
4989	LSL	r3, r3, #4
4990	ORR	r3, r3, r2, LSR #28
4991	LSL	r2, r2, #4
4992	ORR	r2, r2, r1, LSR #28
4993	BFC	r9, #28, #4
4994	SUB	r0, r0, #0x1c
4995	/* Add order times bits 504..511 */
4996	MOV	r10, #0x2c13
4997	MOVT	r10, #0xa30a
4998	MOV	r11, #0x9ce5
4999	MOVT	r11, #0xa7ed
5000	MOV	r1, #0x0
5001	UMLAL	r2, r1, r10, lr
5002	UMAAL	r3, r1, r11, lr
5003	MOV	r10, #0x6329
5004	MOVT	r10, #0x5d08
5005	MOV	r11, #0x621
5006	MOVT	r11, #0xeb21
5007	UMAAL	r4, r1, r10, lr
5008	UMAAL	r5, r1, r11, lr
5009	ADDS	r6, r6, r1
5010	ADCS	r7, r7, #0x0
5011	ADCS	r8, r8, #0x0
5012	ADC	r9, r9, #0x0
5013	SUBS	r6, r6, lr
5014	SBCS	r7, r7, #0x0
5015	SBCS	r8, r8, #0x0
5016	SBC	r9, r9, #0x0
5017	/* Sub product of top 8 words and order */
5018	MOV	r12, sp
5019	MOV	r1, #0x2c13
5020	MOVT	r1, #0xa30a
5021	MOV	lr, #0x0
5022	LDM	r0!, {r10, r11}
5023	UMLAL	r10, lr, r2, r1
5024	UMAAL	r11, lr, r3, r1
5025	STM	r12!, {r10, r11}
5026	LDM	r0!, {r10, r11}
5027	UMAAL	r10, lr, r4, r1
5028	UMAAL	r11, lr, r5, r1
5029	STM	r12!, {r10, r11}
5030	LDM	r0!, {r10, r11}
5031	UMAAL	r10, lr, r6, r1
5032	UMAAL	r11, lr, r7, r1
5033	STM	r12!, {r10, r11}
5034	LDM	r0!, {r10, r11}
5035	UMAAL	r10, lr, r8, r1
5036	BFC	r11, #28, #4
5037	UMAAL	r11, lr, r9, r1
5038	STM	r12!, {r10, r11, lr}
5039	SUB	r0, r0, #0x10
5040	SUB	r12, r12, #0x20
5041	MOV	r1, #0x9ce5
5042	MOVT	r1, #0xa7ed
5043	MOV	lr, #0x0
5044	LDM	r12, {r10, r11}
5045	UMLAL	r10, lr, r2, r1
5046	UMAAL	r11, lr, r3, r1
5047	STM	r12!, {r10, r11}
5048	LDM	r12, {r10, r11}
5049	UMAAL	r10, lr, r4, r1
5050	UMAAL	r11, lr, r5, r1
5051	STM	r12!, {r10, r11}
5052	LDM	r12, {r10, r11}
5053	UMAAL	r10, lr, r6, r1
5054	UMAAL	r11, lr, r7, r1
5055	STM	r12!, {r10, r11}
5056	LDM	r12, {r10, r11}
5057	UMAAL	r10, lr, r8, r1
5058	UMAAL	r11, lr, r9, r1
5059	STM	r12!, {r10, r11, lr}
5060	SUB	r12, r12, #0x20
5061	MOV	r1, #0x6329
5062	MOVT	r1, #0x5d08
5063	MOV	lr, #0x0
5064	LDM	r12, {r10, r11}
5065	UMLAL	r10, lr, r2, r1
5066	UMAAL	r11, lr, r3, r1
5067	STM	r12!, {r10, r11}
5068	LDM	r12, {r10, r11}
5069	UMAAL	r10, lr, r4, r1
5070	UMAAL	r11, lr, r5, r1
5071	STM	r12!, {r10, r11}
5072	LDM	r12, {r10, r11}
5073	UMAAL	r10, lr, r6, r1
5074	UMAAL	r11, lr, r7, r1
5075	STM	r12!, {r10, r11}
5076	LDM	r12, {r10, r11}
5077	UMAAL	r10, lr, r8, r1
5078	UMAAL	r11, lr, r9, r1
5079	STM	r12!, {r10, r11, lr}
5080	SUB	r12, r12, #0x20
5081	MOV	r1, #0x621
5082	MOVT	r1, #0xeb21
5083	MOV	lr, #0x0
5084	LDM	r12, {r10, r11}
5085	UMLAL	r10, lr, r2, r1
5086	UMAAL	r11, lr, r3, r1
5087	STM	r12!, {r10, r11}
5088	LDM	r12, {r10, r11}
5089	UMAAL	r10, lr, r4, r1
5090	UMAAL	r11, lr, r5, r1
5091	STM	r12!, {r10, r11}
5092	LDM	r12, {r10, r11}
5093	UMAAL	r10, lr, r6, r1
5094	UMAAL	r11, lr, r7, r1
5095	STM	r12!, {r10, r11}
5096	LDM	r12, {r10, r11}
5097	UMAAL	r10, lr, r8, r1
5098	UMAAL	r11, lr, r9, r1
5099	STM	r12!, {r10, r11, lr}
5100	SUB	r12, r12, #0x20
5101	/* Subtract at 4 * 32 */
5102	LDM	r12, {r10, r11}
5103	SUBS	r10, r10, r2
5104	SBCS	r11, r11, r3
5105	STM	r12!, {r10, r11}
5106	LDM	r12, {r10, r11}
5107	SBCS	r10, r10, r4
5108	SBCS	r11, r11, r5
5109	STM	r12!, {r10, r11}
5110	LDM	r12, {r10, r11}
5111	SBCS	r10, r10, r6
5112	SBCS	r11, r11, r7
5113	STM	r12!, {r10, r11}
5114	LDM	r12, {r10, r11}
5115	SBCS	r10, r10, r8
5116	SBC	r11, r11, r9
5117	STM	r12!, {r10, r11}
5118	SUB	r12, r12, #0x24
5119	ASR	lr, r11, #25
5120	/* Conditionally subtract order starting at bit 125 */
5121	MOV	r1, #0xa0000000
5122	MOV	r2, #0xba7d
5123	MOVT	r2, #0x4b9e
5124	MOV	r3, #0x4c63
5125	MOVT	r3, #0xcb02
5126	MOV	r4, #0xf39a
5127	MOVT	r4, #0xd45e
5128	MOV	r5, #0xdf3b
5129	MOVT	r5, #0x29b
5130	MOV	r9, #0x2000000
5131	AND	r1, r1, lr
5132	AND	r2, r2, lr
5133	AND	r3, r3, lr
5134	AND	r4, r4, lr
5135	AND	r5, r5, lr
5136	AND	r9, r9, lr
5137	LDM	r12, {r10, r11}
5138	ADDS	r10, r10, r1
5139	ADCS	r11, r11, r2
5140	STM	r12!, {r10, r11}
5141	LDM	r12, {r10, r11}
5142	ADCS	r10, r10, r3
5143	ADCS	r11, r11, r4
5144	STM	r12!, {r10, r11}
5145	LDM	r12, {r10, r11}
5146	ADCS	r10, r10, r5
5147	ADCS	r11, r11, #0x0
5148	STM	r12!, {r10, r11}
5149	LDM	r12, {r10, r11}
5150	ADCS	r10, r10, #0x0
5151	ADCS	r11, r11, #0x0
5152	STM	r12!, {r10, r11}
5153	LDM	r12, {r10}
5154	ADCS	r10, r10, #0x0
5155	STM	r12!, {r10}
5156	SUB	r0, r0, #0x10
5157	MOV	r12, sp
5158	/* Load bits 252-376 */
5159	ADD	r12, r12, #0x1c
5160	LDM	r12, {r1, r2, r3, r4, r5}
5161	LSL	r5, r5, #4
5162	ORR	r5, r5, r4, LSR #28
5163	LSL	r4, r4, #4
5164	ORR	r4, r4, r3, LSR #28
5165	LSL	r3, r3, #4
5166	ORR	r3, r3, r2, LSR #28
5167	LSL	r2, r2, #4
5168	ORR	r2, r2, r1, LSR #28
5169	BFC	r5, #29, #3
5170	SUB	r12, r12, #0x1c
5171	/* Sub product of top 4 words and order */
5172	MOV	r0, sp
5173	/*   * -5cf5d3ed */
5174	MOV	r1, #0x2c13
5175	MOVT	r1, #0xa30a
5176	MOV	lr, #0x0
5177	LDM	r0, {r6, r7, r8, r9}
5178	UMLAL	r6, lr, r2, r1
5179	UMAAL	r7, lr, r3, r1
5180	UMAAL	r8, lr, r4, r1
5181	UMAAL	r9, lr, r5, r1
5182	STM	r0, {r6, r7, r8, r9}
5183	ADD	r0, r0, #0x4
5184	/*   * -5812631b */
5185	MOV	r1, #0x9ce5
5186	MOVT	r1, #0xa7ed
5187	MOV	r10, #0x0
5188	LDM	r0, {r6, r7, r8, r9}
5189	UMLAL	r6, r10, r2, r1
5190	UMAAL	r7, r10, r3, r1
5191	UMAAL	r8, r10, r4, r1
5192	UMAAL	r9, r10, r5, r1
5193	STM	r0, {r6, r7, r8, r9}
5194	ADD	r0, r0, #0x4
5195	/*   * -a2f79cd7 */
5196	MOV	r1, #0x6329
5197	MOVT	r1, #0x5d08
5198	MOV	r11, #0x0
5199	LDM	r0, {r6, r7, r8, r9}
5200	UMLAL	r6, r11, r2, r1
5201	UMAAL	r7, r11, r3, r1
5202	UMAAL	r8, r11, r4, r1
5203	UMAAL	r9, r11, r5, r1
5204	STM	r0, {r6, r7, r8, r9}
5205	ADD	r0, r0, #0x4
5206	/*   * -14def9df */
5207	MOV	r1, #0x621
5208	MOVT	r1, #0xeb21
5209	MOV	r12, #0x0
5210	LDM	r0, {r6, r7, r8, r9}
5211	UMLAL	r6, r12, r2, r1
5212	UMAAL	r7, r12, r3, r1
5213	UMAAL	r8, r12, r4, r1
5214	UMAAL	r9, r12, r5, r1
5215	STM	r0, {r6, r7, r8, r9}
5216	ADD	r0, r0, #0x4
5217	/* Add overflows at 4 * 32 */
5218	LDM	r0, {r6, r7, r8, r9}
5219	BFC	r9, #28, #4
5220	ADDS	r6, r6, lr
5221	ADCS	r7, r7, r10
5222	ADCS	r8, r8, r11
5223	ADC	r9, r9, r12
5224	/* Subtract top at 4 * 32 */
5225	SUBS	r6, r6, r2
5226	SBCS	r7, r7, r3
5227	SBCS	r8, r8, r4
5228	SBCS	r9, r9, r5
5229	SBC	r1, r1, r1
5230	SUB	r0, r0, #0x10
5231	LDM	r0, {r2, r3, r4, r5}
5232	MOV	r10, #0xd3ed
5233	MOVT	r10, #0x5cf5
5234	MOV	r11, #0x631a
5235	MOVT	r11, #0x5812
5236	MOV	r12, #0x9cd6
5237	MOVT	r12, #0xa2f7
5238	MOV	lr, #0xf9de
5239	MOVT	lr, #0x14de
5240	AND	r10, r10, r1
5241	AND	r11, r11, r1
5242	AND	r12, r12, r1
5243	AND	lr, lr, r1
5244	ADDS	r2, r2, r10
5245	ADCS	r3, r3, r11
5246	ADCS	r4, r4, r12
5247	ADCS	r5, r5, lr
5248	ADCS	r6, r6, #0x0
5249	ADCS	r7, r7, #0x0
5250	AND	r1, r1, #0x10000000
5251	ADCS	r8, r8, #0x0
5252	ADC	r9, r9, r1
5253	BFC	r9, #28, #4
5254	/* Store result */
5255	LDR	r0, [sp, #52]
5256	STM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
5257	ADD	sp, sp, #0x38
5258	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
5259	/* Cycle Count = 502 */
5260	.size	sc_reduce,.-sc_reduce
5261#endif /* WOLFSSL_ARM_ARCH_7M */
5262#ifdef HAVE_ED25519_SIGN
5263#ifdef WOLFSSL_ARM_ARCH_7M
5264	.text
5265	.align	4
5266	.globl	sc_muladd
5267	.type	sc_muladd, %function
5268sc_muladd:
5269	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
5270	SUB	sp, sp, #0x50
5271	ADD	lr, sp, #0x44
5272	STM	lr, {r0, r1, r3}
5273	MOV	r0, #0x0
5274	LDR	r12, [r1]
5275	/* A[0] * B[0] */
5276	LDR	lr, [r2]
5277	UMULL	r3, r4, r12, lr
5278	/* A[0] * B[2] */
5279	LDR	lr, [r2, #8]
5280	UMULL	r5, r6, r12, lr
5281	/* A[0] * B[4] */
5282	LDR	lr, [r2, #16]
5283	UMULL	r7, r8, r12, lr
5284	/* A[0] * B[6] */
5285	LDR	lr, [r2, #24]
5286	UMULL	r9, r10, r12, lr
5287	STR	r3, [sp]
5288	/* A[0] * B[1] */
5289	LDR	lr, [r2, #4]
5290	MOV	r11, r0
5291	UMLAL	r4, r11, r12, lr
5292	ADDS	r5, r5, r11
5293	/* A[0] * B[3] */
5294	LDR	lr, [r2, #12]
5295	ADCS	r6, r6, #0x0
5296	ADC	r11, r0, #0x0
5297	UMLAL	r6, r11, r12, lr
5298	ADDS	r7, r7, r11
5299	/* A[0] * B[5] */
5300	LDR	lr, [r2, #20]
5301	ADCS	r8, r8, #0x0
5302	ADC	r11, r0, #0x0
5303	UMLAL	r8, r11, r12, lr
5304	ADDS	r9, r9, r11
5305	/* A[0] * B[7] */
5306	LDR	lr, [r2, #28]
5307	ADCS	r10, r10, #0x0
5308	ADC	r3, r0, #0x0
5309	UMLAL	r10, r3, r12, lr
5310	/* A[1] * B[0] */
5311	LDR	r12, [r1, #4]
5312	LDR	lr, [r2]
5313	MOV	r11, #0x0
5314	UMLAL	r4, r11, r12, lr
5315	STR	r4, [sp, #4]
5316	ADDS	r5, r5, r11
5317	/* A[1] * B[1] */
5318	LDR	lr, [r2, #4]
5319	ADC	r11, r0, #0x0
5320	UMLAL	r5, r11, r12, lr
5321	ADDS	r6, r6, r11
5322	/* A[1] * B[2] */
5323	LDR	lr, [r2, #8]
5324	ADC	r11, r0, #0x0
5325	UMLAL	r6, r11, r12, lr
5326	ADDS	r7, r7, r11
5327	/* A[1] * B[3] */
5328	LDR	lr, [r2, #12]
5329	ADC	r11, r0, #0x0
5330	UMLAL	r7, r11, r12, lr
5331	ADDS	r8, r8, r11
5332	/* A[1] * B[4] */
5333	LDR	lr, [r2, #16]
5334	ADC	r11, r0, #0x0
5335	UMLAL	r8, r11, r12, lr
5336	ADDS	r9, r9, r11
5337	/* A[1] * B[5] */
5338	LDR	lr, [r2, #20]
5339	ADC	r11, r0, #0x0
5340	UMLAL	r9, r11, r12, lr
5341	ADDS	r10, r10, r11
5342	/* A[1] * B[6] */
5343	LDR	lr, [r2, #24]
5344	ADC	r11, r0, #0x0
5345	UMLAL	r10, r11, r12, lr
5346	ADDS	r3, r3, r11
5347	/* A[1] * B[7] */
5348	LDR	lr, [r2, #28]
5349	ADC	r4, r0, #0x0
5350	UMLAL	r3, r4, r12, lr
5351	/* A[2] * B[0] */
5352	LDR	r12, [r1, #8]
5353	LDR	lr, [r2]
5354	MOV	r11, #0x0
5355	UMLAL	r5, r11, r12, lr
5356	STR	r5, [sp, #8]
5357	ADDS	r6, r6, r11
5358	/* A[2] * B[1] */
5359	LDR	lr, [r2, #4]
5360	ADC	r11, r0, #0x0
5361	UMLAL	r6, r11, r12, lr
5362	ADDS	r7, r7, r11
5363	/* A[2] * B[2] */
5364	LDR	lr, [r2, #8]
5365	ADC	r11, r0, #0x0
5366	UMLAL	r7, r11, r12, lr
5367	ADDS	r8, r8, r11
5368	/* A[2] * B[3] */
5369	LDR	lr, [r2, #12]
5370	ADC	r11, r0, #0x0
5371	UMLAL	r8, r11, r12, lr
5372	ADDS	r9, r9, r11
5373	/* A[2] * B[4] */
5374	LDR	lr, [r2, #16]
5375	ADC	r11, r0, #0x0
5376	UMLAL	r9, r11, r12, lr
5377	ADDS	r10, r10, r11
5378	/* A[2] * B[5] */
5379	LDR	lr, [r2, #20]
5380	ADC	r11, r0, #0x0
5381	UMLAL	r10, r11, r12, lr
5382	ADDS	r3, r3, r11
5383	/* A[2] * B[6] */
5384	LDR	lr, [r2, #24]
5385	ADC	r11, r0, #0x0
5386	UMLAL	r3, r11, r12, lr
5387	ADDS	r4, r4, r11
5388	/* A[2] * B[7] */
5389	LDR	lr, [r2, #28]
5390	ADC	r5, r0, #0x0
5391	UMLAL	r4, r5, r12, lr
5392	/* A[3] * B[0] */
5393	LDR	r12, [r1, #12]
5394	LDR	lr, [r2]
5395	MOV	r11, #0x0
5396	UMLAL	r6, r11, r12, lr
5397	STR	r6, [sp, #12]
5398	ADDS	r7, r7, r11
5399	/* A[3] * B[1] */
5400	LDR	lr, [r2, #4]
5401	ADC	r11, r0, #0x0
5402	UMLAL	r7, r11, r12, lr
5403	ADDS	r8, r8, r11
5404	/* A[3] * B[2] */
5405	LDR	lr, [r2, #8]
5406	ADC	r11, r0, #0x0
5407	UMLAL	r8, r11, r12, lr
5408	ADDS	r9, r9, r11
5409	/* A[3] * B[3] */
5410	LDR	lr, [r2, #12]
5411	ADC	r11, r0, #0x0
5412	UMLAL	r9, r11, r12, lr
5413	ADDS	r10, r10, r11
5414	/* A[3] * B[4] */
5415	LDR	lr, [r2, #16]
5416	ADC	r11, r0, #0x0
5417	UMLAL	r10, r11, r12, lr
5418	ADDS	r3, r3, r11
5419	/* A[3] * B[5] */
5420	LDR	lr, [r2, #20]
5421	ADC	r11, r0, #0x0
5422	UMLAL	r3, r11, r12, lr
5423	ADDS	r4, r4, r11
5424	/* A[3] * B[6] */
5425	LDR	lr, [r2, #24]
5426	ADC	r11, r0, #0x0
5427	UMLAL	r4, r11, r12, lr
5428	ADDS	r5, r5, r11
5429	/* A[3] * B[7] */
5430	LDR	lr, [r2, #28]
5431	ADC	r6, r0, #0x0
5432	UMLAL	r5, r6, r12, lr
5433	/* A[4] * B[0] */
5434	LDR	r12, [r1, #16]
5435	LDR	lr, [r2]
5436	MOV	r11, #0x0
5437	UMLAL	r7, r11, r12, lr
5438	STR	r7, [sp, #16]
5439	ADDS	r8, r8, r11
5440	/* A[4] * B[1] */
5441	LDR	lr, [r2, #4]
5442	ADC	r11, r0, #0x0
5443	UMLAL	r8, r11, r12, lr
5444	ADDS	r9, r9, r11
5445	/* A[4] * B[2] */
5446	LDR	lr, [r2, #8]
5447	ADC	r11, r0, #0x0
5448	UMLAL	r9, r11, r12, lr
5449	ADDS	r10, r10, r11
5450	/* A[4] * B[3] */
5451	LDR	lr, [r2, #12]
5452	ADC	r11, r0, #0x0
5453	UMLAL	r10, r11, r12, lr
5454	ADDS	r3, r3, r11
5455	/* A[4] * B[4] */
5456	LDR	lr, [r2, #16]
5457	ADC	r11, r0, #0x0
5458	UMLAL	r3, r11, r12, lr
5459	ADDS	r4, r4, r11
5460	/* A[4] * B[5] */
5461	LDR	lr, [r2, #20]
5462	ADC	r11, r0, #0x0
5463	UMLAL	r4, r11, r12, lr
5464	ADDS	r5, r5, r11
5465	/* A[4] * B[6] */
5466	LDR	lr, [r2, #24]
5467	ADC	r11, r0, #0x0
5468	UMLAL	r5, r11, r12, lr
5469	ADDS	r6, r6, r11
5470	/* A[4] * B[7] */
5471	LDR	lr, [r2, #28]
5472	ADC	r7, r0, #0x0
5473	UMLAL	r6, r7, r12, lr
5474	/* A[5] * B[0] */
5475	LDR	r12, [r1, #20]
5476	LDR	lr, [r2]
5477	MOV	r11, #0x0
5478	UMLAL	r8, r11, r12, lr
5479	STR	r8, [sp, #20]
5480	ADDS	r9, r9, r11
5481	/* A[5] * B[1] */
5482	LDR	lr, [r2, #4]
5483	ADC	r11, r0, #0x0
5484	UMLAL	r9, r11, r12, lr
5485	ADDS	r10, r10, r11
5486	/* A[5] * B[2] */
5487	LDR	lr, [r2, #8]
5488	ADC	r11, r0, #0x0
5489	UMLAL	r10, r11, r12, lr
5490	ADDS	r3, r3, r11
5491	/* A[5] * B[3] */
5492	LDR	lr, [r2, #12]
5493	ADC	r11, r0, #0x0
5494	UMLAL	r3, r11, r12, lr
5495	ADDS	r4, r4, r11
5496	/* A[5] * B[4] */
5497	LDR	lr, [r2, #16]
5498	ADC	r11, r0, #0x0
5499	UMLAL	r4, r11, r12, lr
5500	ADDS	r5, r5, r11
5501	/* A[5] * B[5] */
5502	LDR	lr, [r2, #20]
5503	ADC	r11, r0, #0x0
5504	UMLAL	r5, r11, r12, lr
5505	ADDS	r6, r6, r11
5506	/* A[5] * B[6] */
5507	LDR	lr, [r2, #24]
5508	ADC	r11, r0, #0x0
5509	UMLAL	r6, r11, r12, lr
5510	ADDS	r7, r7, r11
5511	/* A[5] * B[7] */
5512	LDR	lr, [r2, #28]
5513	ADC	r8, r0, #0x0
5514	UMLAL	r7, r8, r12, lr
5515	/* A[6] * B[0] */
5516	LDR	r12, [r1, #24]
5517	LDR	lr, [r2]
5518	MOV	r11, #0x0
5519	UMLAL	r9, r11, r12, lr
5520	STR	r9, [sp, #24]
5521	ADDS	r10, r10, r11
5522	/* A[6] * B[1] */
5523	LDR	lr, [r2, #4]
5524	ADC	r11, r0, #0x0
5525	UMLAL	r10, r11, r12, lr
5526	ADDS	r3, r3, r11
5527	/* A[6] * B[2] */
5528	LDR	lr, [r2, #8]
5529	ADC	r11, r0, #0x0
5530	UMLAL	r3, r11, r12, lr
5531	ADDS	r4, r4, r11
5532	/* A[6] * B[3] */
5533	LDR	lr, [r2, #12]
5534	ADC	r11, r0, #0x0
5535	UMLAL	r4, r11, r12, lr
5536	ADDS	r5, r5, r11
5537	/* A[6] * B[4] */
5538	LDR	lr, [r2, #16]
5539	ADC	r11, r0, #0x0
5540	UMLAL	r5, r11, r12, lr
5541	ADDS	r6, r6, r11
5542	/* A[6] * B[5] */
5543	LDR	lr, [r2, #20]
5544	ADC	r11, r0, #0x0
5545	UMLAL	r6, r11, r12, lr
5546	ADDS	r7, r7, r11
5547	/* A[6] * B[6] */
5548	LDR	lr, [r2, #24]
5549	ADC	r11, r0, #0x0
5550	UMLAL	r7, r11, r12, lr
5551	ADDS	r8, r8, r11
5552	/* A[6] * B[7] */
5553	LDR	lr, [r2, #28]
5554	ADC	r9, r0, #0x0
5555	UMLAL	r8, r9, r12, lr
5556	/* A[7] * B[0] */
5557	LDR	r12, [r1, #28]
5558	LDR	lr, [r2]
5559	MOV	r11, #0x0
5560	UMLAL	r10, r11, r12, lr
5561	STR	r10, [sp, #28]
5562	ADDS	r3, r3, r11
5563	/* A[7] * B[1] */
5564	LDR	lr, [r2, #4]
5565	ADC	r11, r0, #0x0
5566	UMLAL	r3, r11, r12, lr
5567	ADDS	r4, r4, r11
5568	/* A[7] * B[2] */
5569	LDR	lr, [r2, #8]
5570	ADC	r11, r0, #0x0
5571	UMLAL	r4, r11, r12, lr
5572	ADDS	r5, r5, r11
5573	/* A[7] * B[3] */
5574	LDR	lr, [r2, #12]
5575	ADC	r11, r0, #0x0
5576	UMLAL	r5, r11, r12, lr
5577	ADDS	r6, r6, r11
5578	/* A[7] * B[4] */
5579	LDR	lr, [r2, #16]
5580	ADC	r11, r0, #0x0
5581	UMLAL	r6, r11, r12, lr
5582	ADDS	r7, r7, r11
5583	/* A[7] * B[5] */
5584	LDR	lr, [r2, #20]
5585	ADC	r11, r0, #0x0
5586	UMLAL	r7, r11, r12, lr
5587	ADDS	r8, r8, r11
5588	/* A[7] * B[6] */
5589	LDR	lr, [r2, #24]
5590	ADC	r11, r0, #0x0
5591	UMLAL	r8, r11, r12, lr
5592	ADDS	r9, r9, r11
5593	/* A[7] * B[7] */
5594	LDR	lr, [r2, #28]
5595	ADC	r10, r0, #0x0
5596	UMLAL	r9, r10, r12, lr
5597	ADD	lr, sp, #0x20
5598	STM	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
5599	MOV	r0, sp
5600	/* Add c to a * b */
5601	LDR	lr, [sp, #76]
5602	LDM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
5603	LDM	lr!, {r1, r10, r11, r12}
5604	ADDS	r2, r2, r1
5605	ADCS	r3, r3, r10
5606	ADCS	r4, r4, r11
5607	ADCS	r5, r5, r12
5608	LDM	lr!, {r1, r10, r11, r12}
5609	ADCS	r6, r6, r1
5610	ADCS	r7, r7, r10
5611	ADCS	r8, r8, r11
5612	ADCS	r9, r9, r12
5613	MOV	r1, r9
5614	STM	r0!, {r2, r3, r4, r5, r6, r7, r8, r9}
5615	LDM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
5616	ADCS	r2, r2, #0x0
5617	ADCS	r3, r3, #0x0
5618	ADCS	r4, r4, #0x0
5619	ADCS	r5, r5, #0x0
5620	ADCS	r6, r6, #0x0
5621	ADCS	r7, r7, #0x0
5622	ADCS	r8, r8, #0x0
5623	ADC	r9, r9, #0x0
5624	SUB	r0, r0, #0x20
5625	/* Get 252..503 and 504..507 */
5626	LSR	lr, r9, #24
5627	LSL	r9, r9, #4
5628	ORR	r9, r9, r8, LSR #28
5629	LSL	r8, r8, #4
5630	ORR	r8, r8, r7, LSR #28
5631	LSL	r7, r7, #4
5632	ORR	r7, r7, r6, LSR #28
5633	LSL	r6, r6, #4
5634	ORR	r6, r6, r5, LSR #28
5635	LSL	r5, r5, #4
5636	ORR	r5, r5, r4, LSR #28
5637	LSL	r4, r4, #4
5638	ORR	r4, r4, r3, LSR #28
5639	LSL	r3, r3, #4
5640	ORR	r3, r3, r2, LSR #28
5641	LSL	r2, r2, #4
5642	ORR	r2, r2, r1, LSR #28
5643	BFC	r9, #28, #4
5644	/* Add order times bits 504..507 */
5645	MOV	r10, #0x2c13
5646	MOVT	r10, #0xa30a
5647	MOV	r11, #0x9ce5
5648	MOVT	r11, #0xa7ed
5649	MOV	r1, #0x0
5650	UMLAL	r2, r1, r10, lr
5651	ADDS	r3, r3, r1
5652	MOV	r1, #0x0
5653	ADC	r1, r1, #0x0
5654	UMLAL	r3, r1, r11, lr
5655	MOV	r10, #0x6329
5656	MOVT	r10, #0x5d08
5657	MOV	r11, #0x621
5658	MOVT	r11, #0xeb21
5659	ADDS	r4, r4, r1
5660	MOV	r1, #0x0
5661	ADC	r1, r1, #0x0
5662	UMLAL	r4, r1, r10, lr
5663	ADDS	r5, r5, r1
5664	MOV	r1, #0x0
5665	ADC	r1, r1, #0x0
5666	UMLAL	r5, r1, r11, lr
5667	ADDS	r6, r6, r1
5668	ADCS	r7, r7, #0x0
5669	ADCS	r8, r8, #0x0
5670	ADC	r9, r9, #0x0
5671	SUBS	r6, r6, lr
5672	SBCS	r7, r7, #0x0
5673	SBCS	r8, r8, #0x0
5674	SBC	r9, r9, #0x0
5675	/* Sub product of top 8 words and order */
5676	MOV	r12, sp
5677	MOV	r1, #0x2c13
5678	MOVT	r1, #0xa30a
5679	MOV	lr, #0x0
5680	LDM	r0!, {r10, r11}
5681	UMLAL	r10, lr, r2, r1
5682	ADDS	r11, r11, lr
5683	MOV	lr, #0x0
5684	ADC	lr, lr, #0x0
5685	UMLAL	r11, lr, r3, r1
5686	STM	r12!, {r10, r11}
5687	LDM	r0!, {r10, r11}
5688	ADDS	r10, r10, lr
5689	MOV	lr, #0x0
5690	ADC	lr, lr, #0x0
5691	UMLAL	r10, lr, r4, r1
5692	ADDS	r11, r11, lr
5693	MOV	lr, #0x0
5694	ADC	lr, lr, #0x0
5695	UMLAL	r11, lr, r5, r1
5696	STM	r12!, {r10, r11}
5697	LDM	r0!, {r10, r11}
5698	ADDS	r10, r10, lr
5699	MOV	lr, #0x0
5700	ADC	lr, lr, #0x0
5701	UMLAL	r10, lr, r6, r1
5702	ADDS	r11, r11, lr
5703	MOV	lr, #0x0
5704	ADC	lr, lr, #0x0
5705	UMLAL	r11, lr, r7, r1
5706	STM	r12!, {r10, r11}
5707	LDM	r0!, {r10, r11}
5708	ADDS	r10, r10, lr
5709	MOV	lr, #0x0
5710	ADC	lr, lr, #0x0
5711	UMLAL	r10, lr, r8, r1
5712	BFC	r11, #28, #4
5713	ADDS	r11, r11, lr
5714	MOV	lr, #0x0
5715	ADC	lr, lr, #0x0
5716	UMLAL	r11, lr, r9, r1
5717	STM	r12!, {r10, r11, lr}
5718	SUB	r0, r0, #0x10
5719	SUB	r12, r12, #0x20
5720	MOV	r1, #0x9ce5
5721	MOVT	r1, #0xa7ed
5722	MOV	lr, #0x0
5723	LDM	r12, {r10, r11}
5724	UMLAL	r10, lr, r2, r1
5725	ADDS	r11, r11, lr
5726	MOV	lr, #0x0
5727	ADC	lr, lr, #0x0
5728	UMLAL	r11, lr, r3, r1
5729	STM	r12!, {r10, r11}
5730	LDM	r12, {r10, r11}
5731	ADDS	r10, r10, lr
5732	MOV	lr, #0x0
5733	ADC	lr, lr, #0x0
5734	UMLAL	r10, lr, r4, r1
5735	ADDS	r11, r11, lr
5736	MOV	lr, #0x0
5737	ADC	lr, lr, #0x0
5738	UMLAL	r11, lr, r5, r1
5739	STM	r12!, {r10, r11}
5740	LDM	r12, {r10, r11}
5741	ADDS	r10, r10, lr
5742	MOV	lr, #0x0
5743	ADC	lr, lr, #0x0
5744	UMLAL	r10, lr, r6, r1
5745	ADDS	r11, r11, lr
5746	MOV	lr, #0x0
5747	ADC	lr, lr, #0x0
5748	UMLAL	r11, lr, r7, r1
5749	STM	r12!, {r10, r11}
5750	LDM	r12, {r10, r11}
5751	ADDS	r10, r10, lr
5752	MOV	lr, #0x0
5753	ADC	lr, lr, #0x0
5754	UMLAL	r10, lr, r8, r1
5755	ADDS	r11, r11, lr
5756	MOV	lr, #0x0
5757	ADC	lr, lr, #0x0
5758	UMLAL	r11, lr, r9, r1
5759	STM	r12!, {r10, r11, lr}
5760	SUB	r12, r12, #0x20
5761	MOV	r1, #0x6329
5762	MOVT	r1, #0x5d08
5763	MOV	lr, #0x0
5764	LDM	r12, {r10, r11}
5765	UMLAL	r10, lr, r2, r1
5766	ADDS	r11, r11, lr
5767	MOV	lr, #0x0
5768	ADC	lr, lr, #0x0
5769	UMLAL	r11, lr, r3, r1
5770	STM	r12!, {r10, r11}
5771	LDM	r12, {r10, r11}
5772	ADDS	r10, r10, lr
5773	MOV	lr, #0x0
5774	ADC	lr, lr, #0x0
5775	UMLAL	r10, lr, r4, r1
5776	ADDS	r11, r11, lr
5777	MOV	lr, #0x0
5778	ADC	lr, lr, #0x0
5779	UMLAL	r11, lr, r5, r1
5780	STM	r12!, {r10, r11}
5781	LDM	r12, {r10, r11}
5782	ADDS	r10, r10, lr
5783	MOV	lr, #0x0
5784	ADC	lr, lr, #0x0
5785	UMLAL	r10, lr, r6, r1
5786	ADDS	r11, r11, lr
5787	MOV	lr, #0x0
5788	ADC	lr, lr, #0x0
5789	UMLAL	r11, lr, r7, r1
5790	STM	r12!, {r10, r11}
5791	LDM	r12, {r10, r11}
5792	ADDS	r10, r10, lr
5793	MOV	lr, #0x0
5794	ADC	lr, lr, #0x0
5795	UMLAL	r10, lr, r8, r1
5796	ADDS	r11, r11, lr
5797	MOV	lr, #0x0
5798	ADC	lr, lr, #0x0
5799	UMLAL	r11, lr, r9, r1
5800	STM	r12!, {r10, r11, lr}
5801	SUB	r12, r12, #0x20
5802	MOV	r1, #0x621
5803	MOVT	r1, #0xeb21
5804	MOV	lr, #0x0
5805	LDM	r12, {r10, r11}
5806	UMLAL	r10, lr, r2, r1
5807	ADDS	r11, r11, lr
5808	MOV	lr, #0x0
5809	ADC	lr, lr, #0x0
5810	UMLAL	r11, lr, r3, r1
5811	STM	r12!, {r10, r11}
5812	LDM	r12, {r10, r11}
5813	ADDS	r10, r10, lr
5814	MOV	lr, #0x0
5815	ADC	lr, lr, #0x0
5816	UMLAL	r10, lr, r4, r1
5817	ADDS	r11, r11, lr
5818	MOV	lr, #0x0
5819	ADC	lr, lr, #0x0
5820	UMLAL	r11, lr, r5, r1
5821	STM	r12!, {r10, r11}
5822	LDM	r12, {r10, r11}
5823	ADDS	r10, r10, lr
5824	MOV	lr, #0x0
5825	ADC	lr, lr, #0x0
5826	UMLAL	r10, lr, r6, r1
5827	ADDS	r11, r11, lr
5828	MOV	lr, #0x0
5829	ADC	lr, lr, #0x0
5830	UMLAL	r11, lr, r7, r1
5831	STM	r12!, {r10, r11}
5832	LDM	r12, {r10, r11}
5833	ADDS	r10, r10, lr
5834	MOV	lr, #0x0
5835	ADC	lr, lr, #0x0
5836	UMLAL	r10, lr, r8, r1
5837	ADDS	r11, r11, lr
5838	MOV	lr, #0x0
5839	ADC	lr, lr, #0x0
5840	UMLAL	r11, lr, r9, r1
5841	STM	r12!, {r10, r11, lr}
5842	SUB	r12, r12, #0x20
5843	/* Subtract at 4 * 32 */
5844	LDM	r12, {r10, r11}
5845	SUBS	r10, r10, r2
5846	SBCS	r11, r11, r3
5847	STM	r12!, {r10, r11}
5848	LDM	r12, {r10, r11}
5849	SBCS	r10, r10, r4
5850	SBCS	r11, r11, r5
5851	STM	r12!, {r10, r11}
5852	LDM	r12, {r10, r11}
5853	SBCS	r10, r10, r6
5854	SBCS	r11, r11, r7
5855	STM	r12!, {r10, r11}
5856	LDM	r12, {r10, r11}
5857	SBCS	r10, r10, r8
5858	SBC	r11, r11, r9
5859	STM	r12!, {r10, r11}
5860	SUB	r12, r12, #0x24
5861	ASR	lr, r11, #25
5862	/* Conditionally subtract order starting at bit 125 */
5863	MOV	r1, #0xa0000000
5864	MOV	r2, #0xba7d
5865	MOVT	r2, #0x4b9e
5866	MOV	r3, #0x4c63
5867	MOVT	r3, #0xcb02
5868	MOV	r4, #0xf39a
5869	MOVT	r4, #0xd45e
5870	MOV	r5, #0xdf3b
5871	MOVT	r5, #0x29b
5872	MOV	r9, #0x2000000
5873	AND	r1, r1, lr
5874	AND	r2, r2, lr
5875	AND	r3, r3, lr
5876	AND	r4, r4, lr
5877	AND	r5, r5, lr
5878	AND	r9, r9, lr
5879	LDM	r12, {r10, r11}
5880	ADDS	r10, r10, r1
5881	ADCS	r11, r11, r2
5882	STM	r12!, {r10, r11}
5883	LDM	r12, {r10, r11}
5884	ADCS	r10, r10, r3
5885	ADCS	r11, r11, r4
5886	STM	r12!, {r10, r11}
5887	LDM	r12, {r10, r11}
5888	ADCS	r10, r10, r5
5889	ADCS	r11, r11, #0x0
5890	STM	r12!, {r10, r11}
5891	LDM	r12, {r10, r11}
5892	ADCS	r10, r10, #0x0
5893	ADCS	r11, r11, #0x0
5894	STM	r12!, {r10, r11}
5895	LDM	r12, {r10}
5896	ADCS	r10, r10, #0x0
5897	STM	r12!, {r10}
5898	SUB	r0, r0, #0x10
5899	MOV	r12, sp
5900	/* Load bits 252-376 */
5901	ADD	r12, r12, #0x1c
5902	LDM	r12, {r1, r2, r3, r4, r5}
5903	LSL	r5, r5, #4
5904	ORR	r5, r5, r4, LSR #28
5905	LSL	r4, r4, #4
5906	ORR	r4, r4, r3, LSR #28
5907	LSL	r3, r3, #4
5908	ORR	r3, r3, r2, LSR #28
5909	LSL	r2, r2, #4
5910	ORR	r2, r2, r1, LSR #28
5911	BFC	r5, #29, #3
5912	SUB	r12, r12, #0x1c
5913	/* Sub product of top 4 words and order */
5914	MOV	r0, sp
5915	/*   * -5cf5d3ed */
5916	MOV	r1, #0x2c13
5917	MOVT	r1, #0xa30a
5918	MOV	lr, #0x0
5919	LDM	r0, {r6, r7, r8, r9}
5920	UMLAL	r6, lr, r2, r1
5921	ADDS	r7, r7, lr
5922	MOV	lr, #0x0
5923	ADC	lr, lr, #0x0
5924	UMLAL	r7, lr, r3, r1
5925	ADDS	r8, r8, lr
5926	MOV	lr, #0x0
5927	ADC	lr, lr, #0x0
5928	UMLAL	r8, lr, r4, r1
5929	ADDS	r9, r9, lr
5930	MOV	lr, #0x0
5931	ADC	lr, lr, #0x0
5932	UMLAL	r9, lr, r5, r1
5933	STM	r0, {r6, r7, r8, r9}
5934	ADD	r0, r0, #0x4
5935	/*   * -5812631b */
5936	MOV	r1, #0x9ce5
5937	MOVT	r1, #0xa7ed
5938	MOV	r10, #0x0
5939	LDM	r0, {r6, r7, r8, r9}
5940	UMLAL	r6, r10, r2, r1
5941	ADDS	r7, r7, r10
5942	MOV	r10, #0x0
5943	ADC	r10, r10, #0x0
5944	UMLAL	r7, r10, r3, r1
5945	ADDS	r8, r8, r10
5946	MOV	r10, #0x0
5947	ADC	r10, r10, #0x0
5948	UMLAL	r8, r10, r4, r1
5949	ADDS	r9, r9, r10
5950	MOV	r10, #0x0
5951	ADC	r10, r10, #0x0
5952	UMLAL	r9, r10, r5, r1
5953	STM	r0, {r6, r7, r8, r9}
5954	ADD	r0, r0, #0x4
5955	/*   * -a2f79cd7 */
5956	MOV	r1, #0x6329
5957	MOVT	r1, #0x5d08
5958	MOV	r11, #0x0
5959	LDM	r0, {r6, r7, r8, r9}
5960	UMLAL	r6, r11, r2, r1
5961	ADDS	r7, r7, r11
5962	MOV	r11, #0x0
5963	ADC	r11, r11, #0x0
5964	UMLAL	r7, r11, r3, r1
5965	ADDS	r8, r8, r11
5966	MOV	r11, #0x0
5967	ADC	r11, r11, #0x0
5968	UMLAL	r8, r11, r4, r1
5969	ADDS	r9, r9, r11
5970	MOV	r11, #0x0
5971	ADC	r11, r11, #0x0
5972	UMLAL	r9, r11, r5, r1
5973	STM	r0, {r6, r7, r8, r9}
5974	ADD	r0, r0, #0x4
5975	/*   * -14def9df */
5976	MOV	r1, #0x621
5977	MOVT	r1, #0xeb21
5978	MOV	r12, #0x0
5979	LDM	r0, {r6, r7, r8, r9}
5980	UMLAL	r6, r12, r2, r1
5981	ADDS	r7, r7, r12
5982	MOV	r12, #0x0
5983	ADC	r12, r12, #0x0
5984	UMLAL	r7, r12, r3, r1
5985	ADDS	r8, r8, r12
5986	MOV	r12, #0x0
5987	ADC	r12, r12, #0x0
5988	UMLAL	r8, r12, r4, r1
5989	ADDS	r9, r9, r12
5990	MOV	r12, #0x0
5991	ADC	r12, r12, #0x0
5992	UMLAL	r9, r12, r5, r1
5993	STM	r0, {r6, r7, r8, r9}
5994	ADD	r0, r0, #0x4
5995	/* Add overflows at 4 * 32 */
5996	LDM	r0, {r6, r7, r8, r9}
5997	BFC	r9, #28, #4
5998	ADDS	r6, r6, lr
5999	ADCS	r7, r7, r10
6000	ADCS	r8, r8, r11
6001	ADC	r9, r9, r12
6002	/* Subtract top at 4 * 32 */
6003	SUBS	r6, r6, r2
6004	SBCS	r7, r7, r3
6005	SBCS	r8, r8, r4
6006	SBCS	r9, r9, r5
6007	SBC	r1, r1, r1
6008	SUB	r0, r0, #0x10
6009	LDM	r0, {r2, r3, r4, r5}
6010	MOV	r10, #0xd3ed
6011	MOVT	r10, #0x5cf5
6012	MOV	r11, #0x631a
6013	MOVT	r11, #0x5812
6014	MOV	r12, #0x9cd6
6015	MOVT	r12, #0xa2f7
6016	MOV	lr, #0xf9de
6017	MOVT	lr, #0x14de
6018	AND	r10, r10, r1
6019	AND	r11, r11, r1
6020	AND	r12, r12, r1
6021	AND	lr, lr, r1
6022	ADDS	r2, r2, r10
6023	ADCS	r3, r3, r11
6024	ADCS	r4, r4, r12
6025	ADCS	r5, r5, lr
6026	ADCS	r6, r6, #0x0
6027	ADCS	r7, r7, #0x0
6028	AND	r1, r1, #0x10000000
6029	ADCS	r8, r8, #0x0
6030	ADC	r9, r9, r1
6031	BFC	r9, #28, #4
6032	LDR	r0, [sp, #68]
6033	/* Store result */
6034	STR	r2, [r0]
6035	STR	r3, [r0, #4]
6036	STR	r4, [r0, #8]
6037	STR	r5, [r0, #12]
6038	STR	r6, [r0, #16]
6039	STR	r7, [r0, #20]
6040	STR	r8, [r0, #24]
6041	STR	r9, [r0, #28]
6042	ADD	sp, sp, #0x50
6043	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
6044	/* Cycle Count = 994 */
6045	.size	sc_muladd,.-sc_muladd
6046#else
6047	.text
6048	.align	4
6049	.globl	sc_muladd
6050	.type	sc_muladd, %function
6051sc_muladd:
6052	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
6053	SUB	sp, sp, #0x50
6054	ADD	lr, sp, #0x44
6055	STM	lr, {r0, r1, r3}
6056	MOV	lr, r2
6057	LDM	r1, {r0, r1, r2, r3}
6058	LDM	lr!, {r4, r5, r6}
6059	UMULL	r10, r11, r0, r4
6060	UMULL	r12, r7, r1, r4
6061	UMAAL	r11, r12, r0, r5
6062	UMULL	r8, r9, r2, r4
6063	UMAAL	r12, r8, r1, r5
6064	UMAAL	r12, r7, r0, r6
6065	UMAAL	r8, r9, r3, r4
6066	STM	sp, {r10, r11, r12}
6067	UMAAL	r7, r8, r2, r5
6068	LDM	lr!, {r4}
6069	UMULL	r10, r11, r1, r6
6070	UMAAL	r8, r9, r2, r6
6071	UMAAL	r7, r10, r0, r4
6072	UMAAL	r8, r11, r3, r5
6073	STR	r7, [sp, #12]
6074	UMAAL	r8, r10, r1, r4
6075	UMAAL	r9, r11, r3, r6
6076	UMAAL	r9, r10, r2, r4
6077	UMAAL	r10, r11, r3, r4
6078	LDM	lr, {r4, r5, r6, r7}
6079	MOV	r12, #0x0
6080	UMLAL	r8, r12, r0, r4
6081	UMAAL	r9, r12, r1, r4
6082	UMAAL	r10, r12, r2, r4
6083	UMAAL	r11, r12, r3, r4
6084	MOV	r4, #0x0
6085	UMLAL	r9, r4, r0, r5
6086	UMAAL	r10, r4, r1, r5
6087	UMAAL	r11, r4, r2, r5
6088	UMAAL	r12, r4, r3, r5
6089	MOV	r5, #0x0
6090	UMLAL	r10, r5, r0, r6
6091	UMAAL	r11, r5, r1, r6
6092	UMAAL	r12, r5, r2, r6
6093	UMAAL	r4, r5, r3, r6
6094	MOV	r6, #0x0
6095	UMLAL	r11, r6, r0, r7
6096	LDR	r0, [sp, #72]
6097	UMAAL	r12, r6, r1, r7
6098	ADD	r0, r0, #0x10
6099	UMAAL	r4, r6, r2, r7
6100	SUB	lr, lr, #0x10
6101	UMAAL	r5, r6, r3, r7
6102	LDM	r0, {r0, r1, r2, r3}
6103	STR	r6, [sp, #64]
6104	LDM	lr!, {r6}
6105	MOV	r7, #0x0
6106	UMLAL	r8, r7, r0, r6
6107	UMAAL	r9, r7, r1, r6
6108	STR	r8, [sp, #16]
6109	UMAAL	r10, r7, r2, r6
6110	UMAAL	r11, r7, r3, r6
6111	LDM	lr!, {r6}
6112	MOV	r8, #0x0
6113	UMLAL	r9, r8, r0, r6
6114	UMAAL	r10, r8, r1, r6
6115	STR	r9, [sp, #20]
6116	UMAAL	r11, r8, r2, r6
6117	UMAAL	r12, r8, r3, r6
6118	LDM	lr!, {r6}
6119	MOV	r9, #0x0
6120	UMLAL	r10, r9, r0, r6
6121	UMAAL	r11, r9, r1, r6
6122	STR	r10, [sp, #24]
6123	UMAAL	r12, r9, r2, r6
6124	UMAAL	r4, r9, r3, r6
6125	LDM	lr!, {r6}
6126	MOV	r10, #0x0
6127	UMLAL	r11, r10, r0, r6
6128	UMAAL	r12, r10, r1, r6
6129	STR	r11, [sp, #28]
6130	UMAAL	r4, r10, r2, r6
6131	UMAAL	r5, r10, r3, r6
6132	LDM	lr!, {r11}
6133	UMAAL	r12, r7, r0, r11
6134	UMAAL	r4, r7, r1, r11
6135	LDR	r6, [sp, #64]
6136	UMAAL	r5, r7, r2, r11
6137	UMAAL	r6, r7, r3, r11
6138	LDM	lr!, {r11}
6139	UMAAL	r4, r8, r0, r11
6140	UMAAL	r5, r8, r1, r11
6141	UMAAL	r6, r8, r2, r11
6142	UMAAL	r7, r8, r3, r11
6143	LDM	lr, {r11, lr}
6144	UMAAL	r5, r9, r0, r11
6145	UMAAL	r6, r10, r0, lr
6146	UMAAL	r6, r9, r1, r11
6147	UMAAL	r7, r10, r1, lr
6148	UMAAL	r7, r9, r2, r11
6149	UMAAL	r8, r10, r2, lr
6150	UMAAL	r8, r9, r3, r11
6151	UMAAL	r9, r10, r3, lr
6152	MOV	r3, r12
6153	ADD	lr, sp, #0x20
6154	STM	lr, {r3, r4, r5, r6, r7, r8, r9, r10}
6155	MOV	r0, sp
6156	/* Add c to a * b */
6157	LDR	lr, [sp, #76]
6158	LDM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
6159	LDM	lr!, {r1, r10, r11, r12}
6160	ADDS	r2, r2, r1
6161	ADCS	r3, r3, r10
6162	ADCS	r4, r4, r11
6163	ADCS	r5, r5, r12
6164	LDM	lr!, {r1, r10, r11, r12}
6165	ADCS	r6, r6, r1
6166	ADCS	r7, r7, r10
6167	ADCS	r8, r8, r11
6168	ADCS	r9, r9, r12
6169	MOV	r1, r9
6170	STM	r0!, {r2, r3, r4, r5, r6, r7, r8, r9}
6171	LDM	r0, {r2, r3, r4, r5, r6, r7, r8, r9}
6172	ADCS	r2, r2, #0x0
6173	ADCS	r3, r3, #0x0
6174	ADCS	r4, r4, #0x0
6175	ADCS	r5, r5, #0x0
6176	ADCS	r6, r6, #0x0
6177	ADCS	r7, r7, #0x0
6178	ADCS	r8, r8, #0x0
6179	ADC	r9, r9, #0x0
6180	SUB	r0, r0, #0x20
6181	/* Get 252..503 and 504..507 */
6182	LSR	lr, r9, #24
6183	LSL	r9, r9, #4
6184	ORR	r9, r9, r8, LSR #28
6185	LSL	r8, r8, #4
6186	ORR	r8, r8, r7, LSR #28
6187	LSL	r7, r7, #4
6188	ORR	r7, r7, r6, LSR #28
6189	LSL	r6, r6, #4
6190	ORR	r6, r6, r5, LSR #28
6191	LSL	r5, r5, #4
6192	ORR	r5, r5, r4, LSR #28
6193	LSL	r4, r4, #4
6194	ORR	r4, r4, r3, LSR #28
6195	LSL	r3, r3, #4
6196	ORR	r3, r3, r2, LSR #28
6197	LSL	r2, r2, #4
6198	ORR	r2, r2, r1, LSR #28
6199	BFC	r9, #28, #4
6200	/* Add order times bits 504..507 */
6201	MOV	r10, #0x2c13
6202	MOVT	r10, #0xa30a
6203	MOV	r11, #0x9ce5
6204	MOVT	r11, #0xa7ed
6205	MOV	r1, #0x0
6206	UMLAL	r2, r1, r10, lr
6207	UMAAL	r3, r1, r11, lr
6208	MOV	r10, #0x6329
6209	MOVT	r10, #0x5d08
6210	MOV	r11, #0x621
6211	MOVT	r11, #0xeb21
6212	UMAAL	r4, r1, r10, lr
6213	UMAAL	r5, r1, r11, lr
6214	ADDS	r6, r6, r1
6215	ADCS	r7, r7, #0x0
6216	ADCS	r8, r8, #0x0
6217	ADC	r9, r9, #0x0
6218	SUBS	r6, r6, lr
6219	SBCS	r7, r7, #0x0
6220	SBCS	r8, r8, #0x0
6221	SBC	r9, r9, #0x0
6222	/* Sub product of top 8 words and order */
6223	MOV	r12, sp
6224	MOV	r1, #0x2c13
6225	MOVT	r1, #0xa30a
6226	MOV	lr, #0x0
6227	LDM	r0!, {r10, r11}
6228	UMLAL	r10, lr, r2, r1
6229	UMAAL	r11, lr, r3, r1
6230	STM	r12!, {r10, r11}
6231	LDM	r0!, {r10, r11}
6232	UMAAL	r10, lr, r4, r1
6233	UMAAL	r11, lr, r5, r1
6234	STM	r12!, {r10, r11}
6235	LDM	r0!, {r10, r11}
6236	UMAAL	r10, lr, r6, r1
6237	UMAAL	r11, lr, r7, r1
6238	STM	r12!, {r10, r11}
6239	LDM	r0!, {r10, r11}
6240	UMAAL	r10, lr, r8, r1
6241	BFC	r11, #28, #4
6242	UMAAL	r11, lr, r9, r1
6243	STM	r12!, {r10, r11, lr}
6244	SUB	r0, r0, #0x10
6245	SUB	r12, r12, #0x20
6246	MOV	r1, #0x9ce5
6247	MOVT	r1, #0xa7ed
6248	MOV	lr, #0x0
6249	LDM	r12, {r10, r11}
6250	UMLAL	r10, lr, r2, r1
6251	UMAAL	r11, lr, r3, r1
6252	STM	r12!, {r10, r11}
6253	LDM	r12, {r10, r11}
6254	UMAAL	r10, lr, r4, r1
6255	UMAAL	r11, lr, r5, r1
6256	STM	r12!, {r10, r11}
6257	LDM	r12, {r10, r11}
6258	UMAAL	r10, lr, r6, r1
6259	UMAAL	r11, lr, r7, r1
6260	STM	r12!, {r10, r11}
6261	LDM	r12, {r10, r11}
6262	UMAAL	r10, lr, r8, r1
6263	UMAAL	r11, lr, r9, r1
6264	STM	r12!, {r10, r11, lr}
6265	SUB	r12, r12, #0x20
6266	MOV	r1, #0x6329
6267	MOVT	r1, #0x5d08
6268	MOV	lr, #0x0
6269	LDM	r12, {r10, r11}
6270	UMLAL	r10, lr, r2, r1
6271	UMAAL	r11, lr, r3, r1
6272	STM	r12!, {r10, r11}
6273	LDM	r12, {r10, r11}
6274	UMAAL	r10, lr, r4, r1
6275	UMAAL	r11, lr, r5, r1
6276	STM	r12!, {r10, r11}
6277	LDM	r12, {r10, r11}
6278	UMAAL	r10, lr, r6, r1
6279	UMAAL	r11, lr, r7, r1
6280	STM	r12!, {r10, r11}
6281	LDM	r12, {r10, r11}
6282	UMAAL	r10, lr, r8, r1
6283	UMAAL	r11, lr, r9, r1
6284	STM	r12!, {r10, r11, lr}
6285	SUB	r12, r12, #0x20
6286	MOV	r1, #0x621
6287	MOVT	r1, #0xeb21
6288	MOV	lr, #0x0
6289	LDM	r12, {r10, r11}
6290	UMLAL	r10, lr, r2, r1
6291	UMAAL	r11, lr, r3, r1
6292	STM	r12!, {r10, r11}
6293	LDM	r12, {r10, r11}
6294	UMAAL	r10, lr, r4, r1
6295	UMAAL	r11, lr, r5, r1
6296	STM	r12!, {r10, r11}
6297	LDM	r12, {r10, r11}
6298	UMAAL	r10, lr, r6, r1
6299	UMAAL	r11, lr, r7, r1
6300	STM	r12!, {r10, r11}
6301	LDM	r12, {r10, r11}
6302	UMAAL	r10, lr, r8, r1
6303	UMAAL	r11, lr, r9, r1
6304	STM	r12!, {r10, r11, lr}
6305	SUB	r12, r12, #0x20
6306	/* Subtract at 4 * 32 */
6307	LDM	r12, {r10, r11}
6308	SUBS	r10, r10, r2
6309	SBCS	r11, r11, r3
6310	STM	r12!, {r10, r11}
6311	LDM	r12, {r10, r11}
6312	SBCS	r10, r10, r4
6313	SBCS	r11, r11, r5
6314	STM	r12!, {r10, r11}
6315	LDM	r12, {r10, r11}
6316	SBCS	r10, r10, r6
6317	SBCS	r11, r11, r7
6318	STM	r12!, {r10, r11}
6319	LDM	r12, {r10, r11}
6320	SBCS	r10, r10, r8
6321	SBC	r11, r11, r9
6322	STM	r12!, {r10, r11}
6323	SUB	r12, r12, #0x24
6324	ASR	lr, r11, #25
6325	/* Conditionally subtract order starting at bit 125 */
6326	MOV	r1, #0xa0000000
6327	MOV	r2, #0xba7d
6328	MOVT	r2, #0x4b9e
6329	MOV	r3, #0x4c63
6330	MOVT	r3, #0xcb02
6331	MOV	r4, #0xf39a
6332	MOVT	r4, #0xd45e
6333	MOV	r5, #0xdf3b
6334	MOVT	r5, #0x29b
6335	MOV	r9, #0x2000000
6336	AND	r1, r1, lr
6337	AND	r2, r2, lr
6338	AND	r3, r3, lr
6339	AND	r4, r4, lr
6340	AND	r5, r5, lr
6341	AND	r9, r9, lr
6342	LDM	r12, {r10, r11}
6343	ADDS	r10, r10, r1
6344	ADCS	r11, r11, r2
6345	STM	r12!, {r10, r11}
6346	LDM	r12, {r10, r11}
6347	ADCS	r10, r10, r3
6348	ADCS	r11, r11, r4
6349	STM	r12!, {r10, r11}
6350	LDM	r12, {r10, r11}
6351	ADCS	r10, r10, r5
6352	ADCS	r11, r11, #0x0
6353	STM	r12!, {r10, r11}
6354	LDM	r12, {r10, r11}
6355	ADCS	r10, r10, #0x0
6356	ADCS	r11, r11, #0x0
6357	STM	r12!, {r10, r11}
6358	LDM	r12, {r10}
6359	ADCS	r10, r10, #0x0
6360	STM	r12!, {r10}
6361	SUB	r0, r0, #0x10
6362	MOV	r12, sp
6363	/* Load bits 252-376 */
6364	ADD	r12, r12, #0x1c
6365	LDM	r12, {r1, r2, r3, r4, r5}
6366	LSL	r5, r5, #4
6367	ORR	r5, r5, r4, LSR #28
6368	LSL	r4, r4, #4
6369	ORR	r4, r4, r3, LSR #28
6370	LSL	r3, r3, #4
6371	ORR	r3, r3, r2, LSR #28
6372	LSL	r2, r2, #4
6373	ORR	r2, r2, r1, LSR #28
6374	BFC	r5, #29, #3
6375	SUB	r12, r12, #0x1c
6376	/* Sub product of top 4 words and order */
6377	MOV	r0, sp
6378	/*   * -5cf5d3ed */
6379	MOV	r1, #0x2c13
6380	MOVT	r1, #0xa30a
6381	MOV	lr, #0x0
6382	LDM	r0, {r6, r7, r8, r9}
6383	UMLAL	r6, lr, r2, r1
6384	UMAAL	r7, lr, r3, r1
6385	UMAAL	r8, lr, r4, r1
6386	UMAAL	r9, lr, r5, r1
6387	STM	r0, {r6, r7, r8, r9}
6388	ADD	r0, r0, #0x4
6389	/*   * -5812631b */
6390	MOV	r1, #0x9ce5
6391	MOVT	r1, #0xa7ed
6392	MOV	r10, #0x0
6393	LDM	r0, {r6, r7, r8, r9}
6394	UMLAL	r6, r10, r2, r1
6395	UMAAL	r7, r10, r3, r1
6396	UMAAL	r8, r10, r4, r1
6397	UMAAL	r9, r10, r5, r1
6398	STM	r0, {r6, r7, r8, r9}
6399	ADD	r0, r0, #0x4
6400	/*   * -a2f79cd7 */
6401	MOV	r1, #0x6329
6402	MOVT	r1, #0x5d08
6403	MOV	r11, #0x0
6404	LDM	r0, {r6, r7, r8, r9}
6405	UMLAL	r6, r11, r2, r1
6406	UMAAL	r7, r11, r3, r1
6407	UMAAL	r8, r11, r4, r1
6408	UMAAL	r9, r11, r5, r1
6409	STM	r0, {r6, r7, r8, r9}
6410	ADD	r0, r0, #0x4
6411	/*   * -14def9df */
6412	MOV	r1, #0x621
6413	MOVT	r1, #0xeb21
6414	MOV	r12, #0x0
6415	LDM	r0, {r6, r7, r8, r9}
6416	UMLAL	r6, r12, r2, r1
6417	UMAAL	r7, r12, r3, r1
6418	UMAAL	r8, r12, r4, r1
6419	UMAAL	r9, r12, r5, r1
6420	STM	r0, {r6, r7, r8, r9}
6421	ADD	r0, r0, #0x4
6422	/* Add overflows at 4 * 32 */
6423	LDM	r0, {r6, r7, r8, r9}
6424	BFC	r9, #28, #4
6425	ADDS	r6, r6, lr
6426	ADCS	r7, r7, r10
6427	ADCS	r8, r8, r11
6428	ADC	r9, r9, r12
6429	/* Subtract top at 4 * 32 */
6430	SUBS	r6, r6, r2
6431	SBCS	r7, r7, r3
6432	SBCS	r8, r8, r4
6433	SBCS	r9, r9, r5
6434	SBC	r1, r1, r1
6435	SUB	r0, r0, #0x10
6436	LDM	r0, {r2, r3, r4, r5}
6437	MOV	r10, #0xd3ed
6438	MOVT	r10, #0x5cf5
6439	MOV	r11, #0x631a
6440	MOVT	r11, #0x5812
6441	MOV	r12, #0x9cd6
6442	MOVT	r12, #0xa2f7
6443	MOV	lr, #0xf9de
6444	MOVT	lr, #0x14de
6445	AND	r10, r10, r1
6446	AND	r11, r11, r1
6447	AND	r12, r12, r1
6448	AND	lr, lr, r1
6449	ADDS	r2, r2, r10
6450	ADCS	r3, r3, r11
6451	ADCS	r4, r4, r12
6452	ADCS	r5, r5, lr
6453	ADCS	r6, r6, #0x0
6454	ADCS	r7, r7, #0x0
6455	AND	r1, r1, #0x10000000
6456	ADCS	r8, r8, #0x0
6457	ADC	r9, r9, r1
6458	BFC	r9, #28, #4
6459	LDR	r0, [sp, #68]
6460	/* Store result */
6461	STR	r2, [r0]
6462	STR	r3, [r0, #4]
6463	STR	r4, [r0, #8]
6464	STR	r5, [r0, #12]
6465	STR	r6, [r0, #16]
6466	STR	r7, [r0, #20]
6467	STR	r8, [r0, #24]
6468	STR	r9, [r0, #28]
6469	ADD	sp, sp, #0x50
6470	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
6471	/* Cycle Count = 752 */
6472	.size	sc_muladd,.-sc_muladd
6473#endif /* WOLFSSL_ARM_ARCH_7M */
6474#endif /* HAVE_ED25519_SIGN */
6475#endif /* HAVE_ED25519 */
6476
6477#endif /* !CURVE25519_SMALL || !ED25519_SMALL */
6478#endif /* HAVE_CURVE25519 || HAVE_ED25519 */
6479#endif /* WOLFSSL_ARMASM_THUMB2 */
6480#endif /* WOLFSSL_ARMASM */
6481
6482#if defined(__linux__) && defined(__ELF__)
6483.section	.note.GNU-stack,"",%progbits
6484#endif
6485#endif /* !WOLFSSL_ARMASM_INLINE */