luna - wolfssl/wolfcrypt/src/port/arm/thumb2-sha512-asm.S

   1/* thumb2-sha512-asm
   2 *
   3 * Copyright (C) 2006-2026 wolfSSL Inc.
   4 *
   5 * This file is part of wolfSSL.
   6 *
   7 * wolfSSL is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 3 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * wolfSSL is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  20 */
  21
  22/* Generated using (from wolfssl):
  23 *   cd ../scripts
  24 *   ruby ./sha2/sha512.rb \
  25 *       thumb2 ../wolfssl/wolfcrypt/src/port/arm/thumb2-sha512-asm.S
  26 */
  27
  28#include <wolfssl/wolfcrypt/libwolfssl_sources_asm.h>
  29
  30#ifdef WOLFSSL_ARMASM
  31#ifdef WOLFSSL_ARMASM_THUMB2
  32#ifndef WOLFSSL_ARMASM_INLINE
  33	.thumb
  34	.syntax unified
  35#if defined(WOLFSSL_SHA512) || defined(WOLFSSL_SHA384)
  36#ifdef WOLFSSL_ARMASM_NO_NEON
  37#ifndef __APPLE__
  38	.text
  39	.type	L_SHA512_transform_len_k, %object
  40	.size	L_SHA512_transform_len_k, 640
  41#else
  42	.section	__DATA,__data
  43#endif /* __APPLE__ */
  44	/* 16-byte aligned, 128-bit aligned */
  45#ifndef __APPLE__
  46	.align	4
  47#else
  48	.p2align	4
  49#endif /* __APPLE__ */
  50L_SHA512_transform_len_k:
  51	.quad	0x428a2f98d728ae22,0x7137449123ef65cd
  52	.quad	0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
  53	.quad	0x3956c25bf348b538,0x59f111f1b605d019
  54	.quad	0x923f82a4af194f9b,0xab1c5ed5da6d8118
  55	.quad	0xd807aa98a3030242,0x12835b0145706fbe
  56	.quad	0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
  57	.quad	0x72be5d74f27b896f,0x80deb1fe3b1696b1
  58	.quad	0x9bdc06a725c71235,0xc19bf174cf692694
  59	.quad	0xe49b69c19ef14ad2,0xefbe4786384f25e3
  60	.quad	0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
  61	.quad	0x2de92c6f592b0275,0x4a7484aa6ea6e483
  62	.quad	0x5cb0a9dcbd41fbd4,0x76f988da831153b5
  63	.quad	0x983e5152ee66dfab,0xa831c66d2db43210
  64	.quad	0xb00327c898fb213f,0xbf597fc7beef0ee4
  65	.quad	0xc6e00bf33da88fc2,0xd5a79147930aa725
  66	.quad	0x06ca6351e003826f,0x142929670a0e6e70
  67	.quad	0x27b70a8546d22ffc,0x2e1b21385c26c926
  68	.quad	0x4d2c6dfc5ac42aed,0x53380d139d95b3df
  69	.quad	0x650a73548baf63de,0x766a0abb3c77b2a8
  70	.quad	0x81c2c92e47edaee6,0x92722c851482353b
  71	.quad	0xa2bfe8a14cf10364,0xa81a664bbc423001
  72	.quad	0xc24b8b70d0f89791,0xc76c51a30654be30
  73	.quad	0xd192e819d6ef5218,0xd69906245565a910
  74	.quad	0xf40e35855771202a,0x106aa07032bbd1b8
  75	.quad	0x19a4c116b8d2d0c8,0x1e376c085141ab53
  76	.quad	0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
  77	.quad	0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
  78	.quad	0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
  79	.quad	0x748f82ee5defb2fc,0x78a5636f43172f60
  80	.quad	0x84c87814a1f0ab72,0x8cc702081a6439ec
  81	.quad	0x90befffa23631e28,0xa4506cebde82bde9
  82	.quad	0xbef9a3f7b2c67915,0xc67178f2e372532b
  83	.quad	0xca273eceea26619c,0xd186b8c721c0c207
  84	.quad	0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
  85	.quad	0x06f067aa72176fba,0x0a637dc5a2c898a6
  86	.quad	0x113f9804bef90dae,0x1b710b35131c471b
  87	.quad	0x28db77f523047d84,0x32caab7b40c72493
  88	.quad	0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
  89	.quad	0x4cc5d4becb3e42b6,0x597f299cfc657e2a
  90	.quad	0x5fcb6fab3ad6faec,0x6c44198c4a475817
  91	.text
  92	.align	4
  93	.globl	Transform_Sha512_Len_base
  94	.type	Transform_Sha512_Len_base, %function
  95Transform_Sha512_Len_base:
  96	PUSH	{r4, r5, r6, r7, r8, r9, r10, r11, lr}
  97	SUB	sp, sp, #0xc0
  98	ADR	r3, L_SHA512_transform_len_k
  99	/* Copy digest to add in at end */
 100	LDRD	r4, r5, [r0]
 101	LDRD	r6, r7, [r0, #8]
 102	LDRD	r8, r9, [r0, #16]
 103	LDRD	r10, r11, [r0, #24]
 104	STRD	r4, r5, [sp, #128]
 105	STRD	r6, r7, [sp, #136]
 106	STRD	r8, r9, [sp, #144]
 107	STRD	r10, r11, [sp, #152]
 108	LDRD	r4, r5, [r0, #32]
 109	LDRD	r6, r7, [r0, #40]
 110	LDRD	r8, r9, [r0, #48]
 111	LDRD	r10, r11, [r0, #56]
 112	STRD	r4, r5, [sp, #160]
 113	STRD	r6, r7, [sp, #168]
 114	STRD	r8, r9, [sp, #176]
 115	STRD	r10, r11, [sp, #184]
 116	/* Start of loop processing a block */
 117L_SHA512_transform_len_begin:
 118	/* Load, Reverse and Store W */
 119	LDR	r4, [r1]
 120	LDR	r5, [r1, #4]
 121	LDR	r6, [r1, #8]
 122	LDR	r7, [r1, #12]
 123	LDR	r8, [r1, #16]
 124	LDR	r9, [r1, #20]
 125	LDR	r10, [r1, #24]
 126	LDR	r11, [r1, #28]
 127	REV	r4, r4
 128	REV	r5, r5
 129	REV	r6, r6
 130	REV	r7, r7
 131	REV	r8, r8
 132	REV	r9, r9
 133	REV	r10, r10
 134	REV	r11, r11
 135	STR	r5, [sp]
 136	STR	r4, [sp, #4]
 137	STR	r7, [sp, #8]
 138	STR	r6, [sp, #12]
 139	STR	r9, [sp, #16]
 140	STR	r8, [sp, #20]
 141	STR	r11, [sp, #24]
 142	STR	r10, [sp, #28]
 143	LDR	r4, [r1, #32]
 144	LDR	r5, [r1, #36]
 145	LDR	r6, [r1, #40]
 146	LDR	r7, [r1, #44]
 147	LDR	r8, [r1, #48]
 148	LDR	r9, [r1, #52]
 149	LDR	r10, [r1, #56]
 150	LDR	r11, [r1, #60]
 151	REV	r4, r4
 152	REV	r5, r5
 153	REV	r6, r6
 154	REV	r7, r7
 155	REV	r8, r8
 156	REV	r9, r9
 157	REV	r10, r10
 158	REV	r11, r11
 159	STR	r5, [sp, #32]
 160	STR	r4, [sp, #36]
 161	STR	r7, [sp, #40]
 162	STR	r6, [sp, #44]
 163	STR	r9, [sp, #48]
 164	STR	r8, [sp, #52]
 165	STR	r11, [sp, #56]
 166	STR	r10, [sp, #60]
 167	LDR	r4, [r1, #64]
 168	LDR	r5, [r1, #68]
 169	LDR	r6, [r1, #72]
 170	LDR	r7, [r1, #76]
 171	LDR	r8, [r1, #80]
 172	LDR	r9, [r1, #84]
 173	LDR	r10, [r1, #88]
 174	LDR	r11, [r1, #92]
 175	REV	r4, r4
 176	REV	r5, r5
 177	REV	r6, r6
 178	REV	r7, r7
 179	REV	r8, r8
 180	REV	r9, r9
 181	REV	r10, r10
 182	REV	r11, r11
 183	STR	r5, [sp, #64]
 184	STR	r4, [sp, #68]
 185	STR	r7, [sp, #72]
 186	STR	r6, [sp, #76]
 187	STR	r9, [sp, #80]
 188	STR	r8, [sp, #84]
 189	STR	r11, [sp, #88]
 190	STR	r10, [sp, #92]
 191	LDR	r4, [r1, #96]
 192	LDR	r5, [r1, #100]
 193	LDR	r6, [r1, #104]
 194	LDR	r7, [r1, #108]
 195	LDR	r8, [r1, #112]
 196	LDR	r9, [r1, #116]
 197	LDR	r10, [r1, #120]
 198	LDR	r11, [r1, #124]
 199	REV	r4, r4
 200	REV	r5, r5
 201	REV	r6, r6
 202	REV	r7, r7
 203	REV	r8, r8
 204	REV	r9, r9
 205	REV	r10, r10
 206	REV	r11, r11
 207	STR	r5, [sp, #96]
 208	STR	r4, [sp, #100]
 209	STR	r7, [sp, #104]
 210	STR	r6, [sp, #108]
 211	STR	r9, [sp, #112]
 212	STR	r8, [sp, #116]
 213	STR	r11, [sp, #120]
 214	STR	r10, [sp, #124]
 215	/* Pre-calc: b ^ c */
 216	LDRD	r10, r11, [r0, #8]
 217	LDRD	r4, r5, [r0, #16]
 218	EOR	r10, r10, r4
 219	EOR	r11, r11, r5
 220	MOV	r12, #0x4
 221	/* Start of 16 rounds */
 222L_SHA512_transform_len_start:
 223	/* Round 0 */
 224	LDRD	r4, r5, [r0, #32]
 225	LSRS	r6, r4, #14
 226	LSRS	r7, r5, #14
 227	ORR	r7, r7, r4, LSL #18
 228	ORR	r6, r6, r5, LSL #18
 229	LSRS	r8, r4, #18
 230	LSRS	r9, r5, #18
 231	ORR	r9, r9, r4, LSL #14
 232	ORR	r8, r8, r5, LSL #14
 233	EOR	r6, r6, r8
 234	EOR	r7, r7, r9
 235	LSLS	r8, r4, #23
 236	LSLS	r9, r5, #23
 237	ORR	r9, r9, r4, LSR #9
 238	ORR	r8, r8, r5, LSR #9
 239	LDRD	r4, r5, [r0, #56]
 240	EOR	r6, r6, r8
 241	EOR	r7, r7, r9
 242	ADDS	r4, r4, r6
 243	ADC	r5, r5, r7
 244	STRD	r4, r5, [r0, #56]
 245	LDRD	r4, r5, [r0, #32]
 246	LDRD	r6, r7, [r0, #40]
 247	LDRD	r8, r9, [r0, #48]
 248	EOR	r6, r6, r8
 249	EOR	r7, r7, r9
 250	AND	r6, r6, r4
 251	AND	r7, r7, r5
 252	EOR	r6, r6, r8
 253	EOR	r7, r7, r9
 254	LDRD	r4, r5, [r0, #56]
 255	LDRD	r8, r9, [sp]
 256	ADDS	r4, r4, r6
 257	ADC	r5, r5, r7
 258	LDRD	r6, r7, [r3]
 259	ADDS	r4, r4, r8
 260	ADC	r5, r5, r9
 261	LDRD	r8, r9, [r0, #24]
 262	ADDS	r4, r4, r6
 263	ADC	r5, r5, r7
 264	STRD	r4, r5, [r0, #56]
 265	ADDS	r8, r8, r4
 266	ADC	r9, r9, r5
 267	LDRD	r4, r5, [r0]
 268	STRD	r8, r9, [r0, #24]
 269	LSRS	r6, r4, #28
 270	LSRS	r7, r5, #28
 271	ORR	r7, r7, r4, LSL #4
 272	ORR	r6, r6, r5, LSL #4
 273	LSLS	r8, r4, #30
 274	LSLS	r9, r5, #30
 275	ORR	r9, r9, r4, LSR #2
 276	ORR	r8, r8, r5, LSR #2
 277	EOR	r6, r6, r8
 278	EOR	r7, r7, r9
 279	LSLS	r8, r4, #25
 280	LSLS	r9, r5, #25
 281	ORR	r9, r9, r4, LSR #7
 282	ORR	r8, r8, r5, LSR #7
 283	LDRD	r4, r5, [r0, #56]
 284	EOR	r6, r6, r8
 285	EOR	r7, r7, r9
 286	ADDS	r4, r4, r6
 287	ADC	r5, r5, r7
 288	LDRD	r8, r9, [r0]
 289	LDRD	r6, r7, [r0, #8]
 290	STRD	r4, r5, [r0, #56]
 291	EOR	r8, r8, r6
 292	EOR	r9, r9, r7
 293	AND	r10, r10, r8
 294	AND	r11, r11, r9
 295	EOR	r10, r10, r6
 296	EOR	r11, r11, r7
 297	LDRD	r6, r7, [r0, #56]
 298	ADDS	r6, r6, r10
 299	ADC	r7, r7, r11
 300	STRD	r6, r7, [r0, #56]
 301	MOV	r10, r8
 302	MOV	r11, r9
 303	/* Calc new W[0] */
 304	LDRD	r4, r5, [sp, #112]
 305	LSRS	r6, r4, #19
 306	LSRS	r7, r5, #19
 307	ORR	r7, r7, r4, LSL #13
 308	ORR	r6, r6, r5, LSL #13
 309	LSLS	r8, r4, #3
 310	LSLS	r9, r5, #3
 311	ORR	r9, r9, r4, LSR #29
 312	ORR	r8, r8, r5, LSR #29
 313	EOR	r7, r7, r9
 314	EOR	r6, r6, r8
 315	LSRS	r8, r4, #6
 316	LSRS	r9, r5, #6
 317	ORR	r8, r8, r5, LSL #26
 318	EOR	r7, r7, r9
 319	EOR	r6, r6, r8
 320	LDRD	r4, r5, [sp]
 321	LDRD	r8, r9, [sp, #72]
 322	ADDS	r4, r4, r6
 323	ADC	r5, r5, r7
 324	ADDS	r4, r4, r8
 325	ADC	r5, r5, r9
 326	STRD	r4, r5, [sp]
 327	LDRD	r4, r5, [sp, #8]
 328	LSRS	r6, r4, #1
 329	LSRS	r7, r5, #1
 330	ORR	r7, r7, r4, LSL #31
 331	ORR	r6, r6, r5, LSL #31
 332	LSRS	r8, r4, #8
 333	LSRS	r9, r5, #8
 334	ORR	r9, r9, r4, LSL #24
 335	ORR	r8, r8, r5, LSL #24
 336	EOR	r7, r7, r9
 337	EOR	r6, r6, r8
 338	LSRS	r8, r4, #7
 339	LSRS	r9, r5, #7
 340	ORR	r8, r8, r5, LSL #25
 341	EOR	r7, r7, r9
 342	EOR	r6, r6, r8
 343	LDRD	r4, r5, [sp]
 344	ADDS	r4, r4, r6
 345	ADC	r5, r5, r7
 346	STRD	r4, r5, [sp]
 347	/* Round 1 */
 348	LDRD	r4, r5, [r0, #24]
 349	LSRS	r6, r4, #14
 350	LSRS	r7, r5, #14
 351	ORR	r7, r7, r4, LSL #18
 352	ORR	r6, r6, r5, LSL #18
 353	LSRS	r8, r4, #18
 354	LSRS	r9, r5, #18
 355	ORR	r9, r9, r4, LSL #14
 356	ORR	r8, r8, r5, LSL #14
 357	EOR	r6, r6, r8
 358	EOR	r7, r7, r9
 359	LSLS	r8, r4, #23
 360	LSLS	r9, r5, #23
 361	ORR	r9, r9, r4, LSR #9
 362	ORR	r8, r8, r5, LSR #9
 363	LDRD	r4, r5, [r0, #48]
 364	EOR	r6, r6, r8
 365	EOR	r7, r7, r9
 366	ADDS	r4, r4, r6
 367	ADC	r5, r5, r7
 368	STRD	r4, r5, [r0, #48]
 369	LDRD	r4, r5, [r0, #24]
 370	LDRD	r6, r7, [r0, #32]
 371	LDRD	r8, r9, [r0, #40]
 372	EOR	r6, r6, r8
 373	EOR	r7, r7, r9
 374	AND	r6, r6, r4
 375	AND	r7, r7, r5
 376	EOR	r6, r6, r8
 377	EOR	r7, r7, r9
 378	LDRD	r4, r5, [r0, #48]
 379	LDRD	r8, r9, [sp, #8]
 380	ADDS	r4, r4, r6
 381	ADC	r5, r5, r7
 382	LDRD	r6, r7, [r3, #8]
 383	ADDS	r4, r4, r8
 384	ADC	r5, r5, r9
 385	LDRD	r8, r9, [r0, #16]
 386	ADDS	r4, r4, r6
 387	ADC	r5, r5, r7
 388	STRD	r4, r5, [r0, #48]
 389	ADDS	r8, r8, r4
 390	ADC	r9, r9, r5
 391	LDRD	r4, r5, [r0, #56]
 392	STRD	r8, r9, [r0, #16]
 393	LSRS	r6, r4, #28
 394	LSRS	r7, r5, #28
 395	ORR	r7, r7, r4, LSL #4
 396	ORR	r6, r6, r5, LSL #4
 397	LSLS	r8, r4, #30
 398	LSLS	r9, r5, #30
 399	ORR	r9, r9, r4, LSR #2
 400	ORR	r8, r8, r5, LSR #2
 401	EOR	r6, r6, r8
 402	EOR	r7, r7, r9
 403	LSLS	r8, r4, #25
 404	LSLS	r9, r5, #25
 405	ORR	r9, r9, r4, LSR #7
 406	ORR	r8, r8, r5, LSR #7
 407	LDRD	r4, r5, [r0, #48]
 408	EOR	r6, r6, r8
 409	EOR	r7, r7, r9
 410	ADDS	r4, r4, r6
 411	ADC	r5, r5, r7
 412	LDRD	r8, r9, [r0, #56]
 413	LDRD	r6, r7, [r0]
 414	STRD	r4, r5, [r0, #48]
 415	EOR	r8, r8, r6
 416	EOR	r9, r9, r7
 417	AND	r10, r10, r8
 418	AND	r11, r11, r9
 419	EOR	r10, r10, r6
 420	EOR	r11, r11, r7
 421	LDRD	r6, r7, [r0, #48]
 422	ADDS	r6, r6, r10
 423	ADC	r7, r7, r11
 424	STRD	r6, r7, [r0, #48]
 425	MOV	r10, r8
 426	MOV	r11, r9
 427	/* Calc new W[1] */
 428	LDRD	r4, r5, [sp, #120]
 429	LSRS	r6, r4, #19
 430	LSRS	r7, r5, #19
 431	ORR	r7, r7, r4, LSL #13
 432	ORR	r6, r6, r5, LSL #13
 433	LSLS	r8, r4, #3
 434	LSLS	r9, r5, #3
 435	ORR	r9, r9, r4, LSR #29
 436	ORR	r8, r8, r5, LSR #29
 437	EOR	r7, r7, r9
 438	EOR	r6, r6, r8
 439	LSRS	r8, r4, #6
 440	LSRS	r9, r5, #6
 441	ORR	r8, r8, r5, LSL #26
 442	EOR	r7, r7, r9
 443	EOR	r6, r6, r8
 444	LDRD	r4, r5, [sp, #8]
 445	LDRD	r8, r9, [sp, #80]
 446	ADDS	r4, r4, r6
 447	ADC	r5, r5, r7
 448	ADDS	r4, r4, r8
 449	ADC	r5, r5, r9
 450	STRD	r4, r5, [sp, #8]
 451	LDRD	r4, r5, [sp, #16]
 452	LSRS	r6, r4, #1
 453	LSRS	r7, r5, #1
 454	ORR	r7, r7, r4, LSL #31
 455	ORR	r6, r6, r5, LSL #31
 456	LSRS	r8, r4, #8
 457	LSRS	r9, r5, #8
 458	ORR	r9, r9, r4, LSL #24
 459	ORR	r8, r8, r5, LSL #24
 460	EOR	r7, r7, r9
 461	EOR	r6, r6, r8
 462	LSRS	r8, r4, #7
 463	LSRS	r9, r5, #7
 464	ORR	r8, r8, r5, LSL #25
 465	EOR	r7, r7, r9
 466	EOR	r6, r6, r8
 467	LDRD	r4, r5, [sp, #8]
 468	ADDS	r4, r4, r6
 469	ADC	r5, r5, r7
 470	STRD	r4, r5, [sp, #8]
 471	/* Round 2 */
 472	LDRD	r4, r5, [r0, #16]
 473	LSRS	r6, r4, #14
 474	LSRS	r7, r5, #14
 475	ORR	r7, r7, r4, LSL #18
 476	ORR	r6, r6, r5, LSL #18
 477	LSRS	r8, r4, #18
 478	LSRS	r9, r5, #18
 479	ORR	r9, r9, r4, LSL #14
 480	ORR	r8, r8, r5, LSL #14
 481	EOR	r6, r6, r8
 482	EOR	r7, r7, r9
 483	LSLS	r8, r4, #23
 484	LSLS	r9, r5, #23
 485	ORR	r9, r9, r4, LSR #9
 486	ORR	r8, r8, r5, LSR #9
 487	LDRD	r4, r5, [r0, #40]
 488	EOR	r6, r6, r8
 489	EOR	r7, r7, r9
 490	ADDS	r4, r4, r6
 491	ADC	r5, r5, r7
 492	STRD	r4, r5, [r0, #40]
 493	LDRD	r4, r5, [r0, #16]
 494	LDRD	r6, r7, [r0, #24]
 495	LDRD	r8, r9, [r0, #32]
 496	EOR	r6, r6, r8
 497	EOR	r7, r7, r9
 498	AND	r6, r6, r4
 499	AND	r7, r7, r5
 500	EOR	r6, r6, r8
 501	EOR	r7, r7, r9
 502	LDRD	r4, r5, [r0, #40]
 503	LDRD	r8, r9, [sp, #16]
 504	ADDS	r4, r4, r6
 505	ADC	r5, r5, r7
 506	LDRD	r6, r7, [r3, #16]
 507	ADDS	r4, r4, r8
 508	ADC	r5, r5, r9
 509	LDRD	r8, r9, [r0, #8]
 510	ADDS	r4, r4, r6
 511	ADC	r5, r5, r7
 512	STRD	r4, r5, [r0, #40]
 513	ADDS	r8, r8, r4
 514	ADC	r9, r9, r5
 515	LDRD	r4, r5, [r0, #48]
 516	STRD	r8, r9, [r0, #8]
 517	LSRS	r6, r4, #28
 518	LSRS	r7, r5, #28
 519	ORR	r7, r7, r4, LSL #4
 520	ORR	r6, r6, r5, LSL #4
 521	LSLS	r8, r4, #30
 522	LSLS	r9, r5, #30
 523	ORR	r9, r9, r4, LSR #2
 524	ORR	r8, r8, r5, LSR #2
 525	EOR	r6, r6, r8
 526	EOR	r7, r7, r9
 527	LSLS	r8, r4, #25
 528	LSLS	r9, r5, #25
 529	ORR	r9, r9, r4, LSR #7
 530	ORR	r8, r8, r5, LSR #7
 531	LDRD	r4, r5, [r0, #40]
 532	EOR	r6, r6, r8
 533	EOR	r7, r7, r9
 534	ADDS	r4, r4, r6
 535	ADC	r5, r5, r7
 536	LDRD	r8, r9, [r0, #48]
 537	LDRD	r6, r7, [r0, #56]
 538	STRD	r4, r5, [r0, #40]
 539	EOR	r8, r8, r6
 540	EOR	r9, r9, r7
 541	AND	r10, r10, r8
 542	AND	r11, r11, r9
 543	EOR	r10, r10, r6
 544	EOR	r11, r11, r7
 545	LDRD	r6, r7, [r0, #40]
 546	ADDS	r6, r6, r10
 547	ADC	r7, r7, r11
 548	STRD	r6, r7, [r0, #40]
 549	MOV	r10, r8
 550	MOV	r11, r9
 551	/* Calc new W[2] */
 552	LDRD	r4, r5, [sp]
 553	LSRS	r6, r4, #19
 554	LSRS	r7, r5, #19
 555	ORR	r7, r7, r4, LSL #13
 556	ORR	r6, r6, r5, LSL #13
 557	LSLS	r8, r4, #3
 558	LSLS	r9, r5, #3
 559	ORR	r9, r9, r4, LSR #29
 560	ORR	r8, r8, r5, LSR #29
 561	EOR	r7, r7, r9
 562	EOR	r6, r6, r8
 563	LSRS	r8, r4, #6
 564	LSRS	r9, r5, #6
 565	ORR	r8, r8, r5, LSL #26
 566	EOR	r7, r7, r9
 567	EOR	r6, r6, r8
 568	LDRD	r4, r5, [sp, #16]
 569	LDRD	r8, r9, [sp, #88]
 570	ADDS	r4, r4, r6
 571	ADC	r5, r5, r7
 572	ADDS	r4, r4, r8
 573	ADC	r5, r5, r9
 574	STRD	r4, r5, [sp, #16]
 575	LDRD	r4, r5, [sp, #24]
 576	LSRS	r6, r4, #1
 577	LSRS	r7, r5, #1
 578	ORR	r7, r7, r4, LSL #31
 579	ORR	r6, r6, r5, LSL #31
 580	LSRS	r8, r4, #8
 581	LSRS	r9, r5, #8
 582	ORR	r9, r9, r4, LSL #24
 583	ORR	r8, r8, r5, LSL #24
 584	EOR	r7, r7, r9
 585	EOR	r6, r6, r8
 586	LSRS	r8, r4, #7
 587	LSRS	r9, r5, #7
 588	ORR	r8, r8, r5, LSL #25
 589	EOR	r7, r7, r9
 590	EOR	r6, r6, r8
 591	LDRD	r4, r5, [sp, #16]
 592	ADDS	r4, r4, r6
 593	ADC	r5, r5, r7
 594	STRD	r4, r5, [sp, #16]
 595	/* Round 3 */
 596	LDRD	r4, r5, [r0, #8]
 597	LSRS	r6, r4, #14
 598	LSRS	r7, r5, #14
 599	ORR	r7, r7, r4, LSL #18
 600	ORR	r6, r6, r5, LSL #18
 601	LSRS	r8, r4, #18
 602	LSRS	r9, r5, #18
 603	ORR	r9, r9, r4, LSL #14
 604	ORR	r8, r8, r5, LSL #14
 605	EOR	r6, r6, r8
 606	EOR	r7, r7, r9
 607	LSLS	r8, r4, #23
 608	LSLS	r9, r5, #23
 609	ORR	r9, r9, r4, LSR #9
 610	ORR	r8, r8, r5, LSR #9
 611	LDRD	r4, r5, [r0, #32]
 612	EOR	r6, r6, r8
 613	EOR	r7, r7, r9
 614	ADDS	r4, r4, r6
 615	ADC	r5, r5, r7
 616	STRD	r4, r5, [r0, #32]
 617	LDRD	r4, r5, [r0, #8]
 618	LDRD	r6, r7, [r0, #16]
 619	LDRD	r8, r9, [r0, #24]
 620	EOR	r6, r6, r8
 621	EOR	r7, r7, r9
 622	AND	r6, r6, r4
 623	AND	r7, r7, r5
 624	EOR	r6, r6, r8
 625	EOR	r7, r7, r9
 626	LDRD	r4, r5, [r0, #32]
 627	LDRD	r8, r9, [sp, #24]
 628	ADDS	r4, r4, r6
 629	ADC	r5, r5, r7
 630	LDRD	r6, r7, [r3, #24]
 631	ADDS	r4, r4, r8
 632	ADC	r5, r5, r9
 633	LDRD	r8, r9, [r0]
 634	ADDS	r4, r4, r6
 635	ADC	r5, r5, r7
 636	STRD	r4, r5, [r0, #32]
 637	ADDS	r8, r8, r4
 638	ADC	r9, r9, r5
 639	LDRD	r4, r5, [r0, #40]
 640	STRD	r8, r9, [r0]
 641	LSRS	r6, r4, #28
 642	LSRS	r7, r5, #28
 643	ORR	r7, r7, r4, LSL #4
 644	ORR	r6, r6, r5, LSL #4
 645	LSLS	r8, r4, #30
 646	LSLS	r9, r5, #30
 647	ORR	r9, r9, r4, LSR #2
 648	ORR	r8, r8, r5, LSR #2
 649	EOR	r6, r6, r8
 650	EOR	r7, r7, r9
 651	LSLS	r8, r4, #25
 652	LSLS	r9, r5, #25
 653	ORR	r9, r9, r4, LSR #7
 654	ORR	r8, r8, r5, LSR #7
 655	LDRD	r4, r5, [r0, #32]
 656	EOR	r6, r6, r8
 657	EOR	r7, r7, r9
 658	ADDS	r4, r4, r6
 659	ADC	r5, r5, r7
 660	LDRD	r8, r9, [r0, #40]
 661	LDRD	r6, r7, [r0, #48]
 662	STRD	r4, r5, [r0, #32]
 663	EOR	r8, r8, r6
 664	EOR	r9, r9, r7
 665	AND	r10, r10, r8
 666	AND	r11, r11, r9
 667	EOR	r10, r10, r6
 668	EOR	r11, r11, r7
 669	LDRD	r6, r7, [r0, #32]
 670	ADDS	r6, r6, r10
 671	ADC	r7, r7, r11
 672	STRD	r6, r7, [r0, #32]
 673	MOV	r10, r8
 674	MOV	r11, r9
 675	/* Calc new W[3] */
 676	LDRD	r4, r5, [sp, #8]
 677	LSRS	r6, r4, #19
 678	LSRS	r7, r5, #19
 679	ORR	r7, r7, r4, LSL #13
 680	ORR	r6, r6, r5, LSL #13
 681	LSLS	r8, r4, #3
 682	LSLS	r9, r5, #3
 683	ORR	r9, r9, r4, LSR #29
 684	ORR	r8, r8, r5, LSR #29
 685	EOR	r7, r7, r9
 686	EOR	r6, r6, r8
 687	LSRS	r8, r4, #6
 688	LSRS	r9, r5, #6
 689	ORR	r8, r8, r5, LSL #26
 690	EOR	r7, r7, r9
 691	EOR	r6, r6, r8
 692	LDRD	r4, r5, [sp, #24]
 693	LDRD	r8, r9, [sp, #96]
 694	ADDS	r4, r4, r6
 695	ADC	r5, r5, r7
 696	ADDS	r4, r4, r8
 697	ADC	r5, r5, r9
 698	STRD	r4, r5, [sp, #24]
 699	LDRD	r4, r5, [sp, #32]
 700	LSRS	r6, r4, #1
 701	LSRS	r7, r5, #1
 702	ORR	r7, r7, r4, LSL #31
 703	ORR	r6, r6, r5, LSL #31
 704	LSRS	r8, r4, #8
 705	LSRS	r9, r5, #8
 706	ORR	r9, r9, r4, LSL #24
 707	ORR	r8, r8, r5, LSL #24
 708	EOR	r7, r7, r9
 709	EOR	r6, r6, r8
 710	LSRS	r8, r4, #7
 711	LSRS	r9, r5, #7
 712	ORR	r8, r8, r5, LSL #25
 713	EOR	r7, r7, r9
 714	EOR	r6, r6, r8
 715	LDRD	r4, r5, [sp, #24]
 716	ADDS	r4, r4, r6
 717	ADC	r5, r5, r7
 718	STRD	r4, r5, [sp, #24]
 719	/* Round 4 */
 720	LDRD	r4, r5, [r0]
 721	LSRS	r6, r4, #14
 722	LSRS	r7, r5, #14
 723	ORR	r7, r7, r4, LSL #18
 724	ORR	r6, r6, r5, LSL #18
 725	LSRS	r8, r4, #18
 726	LSRS	r9, r5, #18
 727	ORR	r9, r9, r4, LSL #14
 728	ORR	r8, r8, r5, LSL #14
 729	EOR	r6, r6, r8
 730	EOR	r7, r7, r9
 731	LSLS	r8, r4, #23
 732	LSLS	r9, r5, #23
 733	ORR	r9, r9, r4, LSR #9
 734	ORR	r8, r8, r5, LSR #9
 735	LDRD	r4, r5, [r0, #24]
 736	EOR	r6, r6, r8
 737	EOR	r7, r7, r9
 738	ADDS	r4, r4, r6
 739	ADC	r5, r5, r7
 740	STRD	r4, r5, [r0, #24]
 741	LDRD	r4, r5, [r0]
 742	LDRD	r6, r7, [r0, #8]
 743	LDRD	r8, r9, [r0, #16]
 744	EOR	r6, r6, r8
 745	EOR	r7, r7, r9
 746	AND	r6, r6, r4
 747	AND	r7, r7, r5
 748	EOR	r6, r6, r8
 749	EOR	r7, r7, r9
 750	LDRD	r4, r5, [r0, #24]
 751	LDRD	r8, r9, [sp, #32]
 752	ADDS	r4, r4, r6
 753	ADC	r5, r5, r7
 754	LDRD	r6, r7, [r3, #32]
 755	ADDS	r4, r4, r8
 756	ADC	r5, r5, r9
 757	LDRD	r8, r9, [r0, #56]
 758	ADDS	r4, r4, r6
 759	ADC	r5, r5, r7
 760	STRD	r4, r5, [r0, #24]
 761	ADDS	r8, r8, r4
 762	ADC	r9, r9, r5
 763	LDRD	r4, r5, [r0, #32]
 764	STRD	r8, r9, [r0, #56]
 765	LSRS	r6, r4, #28
 766	LSRS	r7, r5, #28
 767	ORR	r7, r7, r4, LSL #4
 768	ORR	r6, r6, r5, LSL #4
 769	LSLS	r8, r4, #30
 770	LSLS	r9, r5, #30
 771	ORR	r9, r9, r4, LSR #2
 772	ORR	r8, r8, r5, LSR #2
 773	EOR	r6, r6, r8
 774	EOR	r7, r7, r9
 775	LSLS	r8, r4, #25
 776	LSLS	r9, r5, #25
 777	ORR	r9, r9, r4, LSR #7
 778	ORR	r8, r8, r5, LSR #7
 779	LDRD	r4, r5, [r0, #24]
 780	EOR	r6, r6, r8
 781	EOR	r7, r7, r9
 782	ADDS	r4, r4, r6
 783	ADC	r5, r5, r7
 784	LDRD	r8, r9, [r0, #32]
 785	LDRD	r6, r7, [r0, #40]
 786	STRD	r4, r5, [r0, #24]
 787	EOR	r8, r8, r6
 788	EOR	r9, r9, r7
 789	AND	r10, r10, r8
 790	AND	r11, r11, r9
 791	EOR	r10, r10, r6
 792	EOR	r11, r11, r7
 793	LDRD	r6, r7, [r0, #24]
 794	ADDS	r6, r6, r10
 795	ADC	r7, r7, r11
 796	STRD	r6, r7, [r0, #24]
 797	MOV	r10, r8
 798	MOV	r11, r9
 799	/* Calc new W[4] */
 800	LDRD	r4, r5, [sp, #16]
 801	LSRS	r6, r4, #19
 802	LSRS	r7, r5, #19
 803	ORR	r7, r7, r4, LSL #13
 804	ORR	r6, r6, r5, LSL #13
 805	LSLS	r8, r4, #3
 806	LSLS	r9, r5, #3
 807	ORR	r9, r9, r4, LSR #29
 808	ORR	r8, r8, r5, LSR #29
 809	EOR	r7, r7, r9
 810	EOR	r6, r6, r8
 811	LSRS	r8, r4, #6
 812	LSRS	r9, r5, #6
 813	ORR	r8, r8, r5, LSL #26
 814	EOR	r7, r7, r9
 815	EOR	r6, r6, r8
 816	LDRD	r4, r5, [sp, #32]
 817	LDRD	r8, r9, [sp, #104]
 818	ADDS	r4, r4, r6
 819	ADC	r5, r5, r7
 820	ADDS	r4, r4, r8
 821	ADC	r5, r5, r9
 822	STRD	r4, r5, [sp, #32]
 823	LDRD	r4, r5, [sp, #40]
 824	LSRS	r6, r4, #1
 825	LSRS	r7, r5, #1
 826	ORR	r7, r7, r4, LSL #31
 827	ORR	r6, r6, r5, LSL #31
 828	LSRS	r8, r4, #8
 829	LSRS	r9, r5, #8
 830	ORR	r9, r9, r4, LSL #24
 831	ORR	r8, r8, r5, LSL #24
 832	EOR	r7, r7, r9
 833	EOR	r6, r6, r8
 834	LSRS	r8, r4, #7
 835	LSRS	r9, r5, #7
 836	ORR	r8, r8, r5, LSL #25
 837	EOR	r7, r7, r9
 838	EOR	r6, r6, r8
 839	LDRD	r4, r5, [sp, #32]
 840	ADDS	r4, r4, r6
 841	ADC	r5, r5, r7
 842	STRD	r4, r5, [sp, #32]
 843	/* Round 5 */
 844	LDRD	r4, r5, [r0, #56]
 845	LSRS	r6, r4, #14
 846	LSRS	r7, r5, #14
 847	ORR	r7, r7, r4, LSL #18
 848	ORR	r6, r6, r5, LSL #18
 849	LSRS	r8, r4, #18
 850	LSRS	r9, r5, #18
 851	ORR	r9, r9, r4, LSL #14
 852	ORR	r8, r8, r5, LSL #14
 853	EOR	r6, r6, r8
 854	EOR	r7, r7, r9
 855	LSLS	r8, r4, #23
 856	LSLS	r9, r5, #23
 857	ORR	r9, r9, r4, LSR #9
 858	ORR	r8, r8, r5, LSR #9
 859	LDRD	r4, r5, [r0, #16]
 860	EOR	r6, r6, r8
 861	EOR	r7, r7, r9
 862	ADDS	r4, r4, r6
 863	ADC	r5, r5, r7
 864	STRD	r4, r5, [r0, #16]
 865	LDRD	r4, r5, [r0, #56]
 866	LDRD	r6, r7, [r0]
 867	LDRD	r8, r9, [r0, #8]
 868	EOR	r6, r6, r8
 869	EOR	r7, r7, r9
 870	AND	r6, r6, r4
 871	AND	r7, r7, r5
 872	EOR	r6, r6, r8
 873	EOR	r7, r7, r9
 874	LDRD	r4, r5, [r0, #16]
 875	LDRD	r8, r9, [sp, #40]
 876	ADDS	r4, r4, r6
 877	ADC	r5, r5, r7
 878	LDRD	r6, r7, [r3, #40]
 879	ADDS	r4, r4, r8
 880	ADC	r5, r5, r9
 881	LDRD	r8, r9, [r0, #48]
 882	ADDS	r4, r4, r6
 883	ADC	r5, r5, r7
 884	STRD	r4, r5, [r0, #16]
 885	ADDS	r8, r8, r4
 886	ADC	r9, r9, r5
 887	LDRD	r4, r5, [r0, #24]
 888	STRD	r8, r9, [r0, #48]
 889	LSRS	r6, r4, #28
 890	LSRS	r7, r5, #28
 891	ORR	r7, r7, r4, LSL #4
 892	ORR	r6, r6, r5, LSL #4
 893	LSLS	r8, r4, #30
 894	LSLS	r9, r5, #30
 895	ORR	r9, r9, r4, LSR #2
 896	ORR	r8, r8, r5, LSR #2
 897	EOR	r6, r6, r8
 898	EOR	r7, r7, r9
 899	LSLS	r8, r4, #25
 900	LSLS	r9, r5, #25
 901	ORR	r9, r9, r4, LSR #7
 902	ORR	r8, r8, r5, LSR #7
 903	LDRD	r4, r5, [r0, #16]
 904	EOR	r6, r6, r8
 905	EOR	r7, r7, r9
 906	ADDS	r4, r4, r6
 907	ADC	r5, r5, r7
 908	LDRD	r8, r9, [r0, #24]
 909	LDRD	r6, r7, [r0, #32]
 910	STRD	r4, r5, [r0, #16]
 911	EOR	r8, r8, r6
 912	EOR	r9, r9, r7
 913	AND	r10, r10, r8
 914	AND	r11, r11, r9
 915	EOR	r10, r10, r6
 916	EOR	r11, r11, r7
 917	LDRD	r6, r7, [r0, #16]
 918	ADDS	r6, r6, r10
 919	ADC	r7, r7, r11
 920	STRD	r6, r7, [r0, #16]
 921	MOV	r10, r8
 922	MOV	r11, r9
 923	/* Calc new W[5] */
 924	LDRD	r4, r5, [sp, #24]
 925	LSRS	r6, r4, #19
 926	LSRS	r7, r5, #19
 927	ORR	r7, r7, r4, LSL #13
 928	ORR	r6, r6, r5, LSL #13
 929	LSLS	r8, r4, #3
 930	LSLS	r9, r5, #3
 931	ORR	r9, r9, r4, LSR #29
 932	ORR	r8, r8, r5, LSR #29
 933	EOR	r7, r7, r9
 934	EOR	r6, r6, r8
 935	LSRS	r8, r4, #6
 936	LSRS	r9, r5, #6
 937	ORR	r8, r8, r5, LSL #26
 938	EOR	r7, r7, r9
 939	EOR	r6, r6, r8
 940	LDRD	r4, r5, [sp, #40]
 941	LDRD	r8, r9, [sp, #112]
 942	ADDS	r4, r4, r6
 943	ADC	r5, r5, r7
 944	ADDS	r4, r4, r8
 945	ADC	r5, r5, r9
 946	STRD	r4, r5, [sp, #40]
 947	LDRD	r4, r5, [sp, #48]
 948	LSRS	r6, r4, #1
 949	LSRS	r7, r5, #1
 950	ORR	r7, r7, r4, LSL #31
 951	ORR	r6, r6, r5, LSL #31
 952	LSRS	r8, r4, #8
 953	LSRS	r9, r5, #8
 954	ORR	r9, r9, r4, LSL #24
 955	ORR	r8, r8, r5, LSL #24
 956	EOR	r7, r7, r9
 957	EOR	r6, r6, r8
 958	LSRS	r8, r4, #7
 959	LSRS	r9, r5, #7
 960	ORR	r8, r8, r5, LSL #25
 961	EOR	r7, r7, r9
 962	EOR	r6, r6, r8
 963	LDRD	r4, r5, [sp, #40]
 964	ADDS	r4, r4, r6
 965	ADC	r5, r5, r7
 966	STRD	r4, r5, [sp, #40]
 967	/* Round 6 */
 968	LDRD	r4, r5, [r0, #48]
 969	LSRS	r6, r4, #14
 970	LSRS	r7, r5, #14
 971	ORR	r7, r7, r4, LSL #18
 972	ORR	r6, r6, r5, LSL #18
 973	LSRS	r8, r4, #18
 974	LSRS	r9, r5, #18
 975	ORR	r9, r9, r4, LSL #14
 976	ORR	r8, r8, r5, LSL #14
 977	EOR	r6, r6, r8
 978	EOR	r7, r7, r9
 979	LSLS	r8, r4, #23
 980	LSLS	r9, r5, #23
 981	ORR	r9, r9, r4, LSR #9
 982	ORR	r8, r8, r5, LSR #9
 983	LDRD	r4, r5, [r0, #8]
 984	EOR	r6, r6, r8
 985	EOR	r7, r7, r9
 986	ADDS	r4, r4, r6
 987	ADC	r5, r5, r7
 988	STRD	r4, r5, [r0, #8]
 989	LDRD	r4, r5, [r0, #48]
 990	LDRD	r6, r7, [r0, #56]
 991	LDRD	r8, r9, [r0]
 992	EOR	r6, r6, r8
 993	EOR	r7, r7, r9
 994	AND	r6, r6, r4
 995	AND	r7, r7, r5
 996	EOR	r6, r6, r8
 997	EOR	r7, r7, r9
 998	LDRD	r4, r5, [r0, #8]
 999	LDRD	r8, r9, [sp, #48]
1000	ADDS	r4, r4, r6
1001	ADC	r5, r5, r7
1002	LDRD	r6, r7, [r3, #48]
1003	ADDS	r4, r4, r8
1004	ADC	r5, r5, r9
1005	LDRD	r8, r9, [r0, #40]
1006	ADDS	r4, r4, r6
1007	ADC	r5, r5, r7
1008	STRD	r4, r5, [r0, #8]
1009	ADDS	r8, r8, r4
1010	ADC	r9, r9, r5
1011	LDRD	r4, r5, [r0, #16]
1012	STRD	r8, r9, [r0, #40]
1013	LSRS	r6, r4, #28
1014	LSRS	r7, r5, #28
1015	ORR	r7, r7, r4, LSL #4
1016	ORR	r6, r6, r5, LSL #4
1017	LSLS	r8, r4, #30
1018	LSLS	r9, r5, #30
1019	ORR	r9, r9, r4, LSR #2
1020	ORR	r8, r8, r5, LSR #2
1021	EOR	r6, r6, r8
1022	EOR	r7, r7, r9
1023	LSLS	r8, r4, #25
1024	LSLS	r9, r5, #25
1025	ORR	r9, r9, r4, LSR #7
1026	ORR	r8, r8, r5, LSR #7
1027	LDRD	r4, r5, [r0, #8]
1028	EOR	r6, r6, r8
1029	EOR	r7, r7, r9
1030	ADDS	r4, r4, r6
1031	ADC	r5, r5, r7
1032	LDRD	r8, r9, [r0, #16]
1033	LDRD	r6, r7, [r0, #24]
1034	STRD	r4, r5, [r0, #8]
1035	EOR	r8, r8, r6
1036	EOR	r9, r9, r7
1037	AND	r10, r10, r8
1038	AND	r11, r11, r9
1039	EOR	r10, r10, r6
1040	EOR	r11, r11, r7
1041	LDRD	r6, r7, [r0, #8]
1042	ADDS	r6, r6, r10
1043	ADC	r7, r7, r11
1044	STRD	r6, r7, [r0, #8]
1045	MOV	r10, r8
1046	MOV	r11, r9
1047	/* Calc new W[6] */
1048	LDRD	r4, r5, [sp, #32]
1049	LSRS	r6, r4, #19
1050	LSRS	r7, r5, #19
1051	ORR	r7, r7, r4, LSL #13
1052	ORR	r6, r6, r5, LSL #13
1053	LSLS	r8, r4, #3
1054	LSLS	r9, r5, #3
1055	ORR	r9, r9, r4, LSR #29
1056	ORR	r8, r8, r5, LSR #29
1057	EOR	r7, r7, r9
1058	EOR	r6, r6, r8
1059	LSRS	r8, r4, #6
1060	LSRS	r9, r5, #6
1061	ORR	r8, r8, r5, LSL #26
1062	EOR	r7, r7, r9
1063	EOR	r6, r6, r8
1064	LDRD	r4, r5, [sp, #48]
1065	LDRD	r8, r9, [sp, #120]
1066	ADDS	r4, r4, r6
1067	ADC	r5, r5, r7
1068	ADDS	r4, r4, r8
1069	ADC	r5, r5, r9
1070	STRD	r4, r5, [sp, #48]
1071	LDRD	r4, r5, [sp, #56]
1072	LSRS	r6, r4, #1
1073	LSRS	r7, r5, #1
1074	ORR	r7, r7, r4, LSL #31
1075	ORR	r6, r6, r5, LSL #31
1076	LSRS	r8, r4, #8
1077	LSRS	r9, r5, #8
1078	ORR	r9, r9, r4, LSL #24
1079	ORR	r8, r8, r5, LSL #24
1080	EOR	r7, r7, r9
1081	EOR	r6, r6, r8
1082	LSRS	r8, r4, #7
1083	LSRS	r9, r5, #7
1084	ORR	r8, r8, r5, LSL #25
1085	EOR	r7, r7, r9
1086	EOR	r6, r6, r8
1087	LDRD	r4, r5, [sp, #48]
1088	ADDS	r4, r4, r6
1089	ADC	r5, r5, r7
1090	STRD	r4, r5, [sp, #48]
1091	/* Round 7 */
1092	LDRD	r4, r5, [r0, #40]
1093	LSRS	r6, r4, #14
1094	LSRS	r7, r5, #14
1095	ORR	r7, r7, r4, LSL #18
1096	ORR	r6, r6, r5, LSL #18
1097	LSRS	r8, r4, #18
1098	LSRS	r9, r5, #18
1099	ORR	r9, r9, r4, LSL #14
1100	ORR	r8, r8, r5, LSL #14
1101	EOR	r6, r6, r8
1102	EOR	r7, r7, r9
1103	LSLS	r8, r4, #23
1104	LSLS	r9, r5, #23
1105	ORR	r9, r9, r4, LSR #9
1106	ORR	r8, r8, r5, LSR #9
1107	LDRD	r4, r5, [r0]
1108	EOR	r6, r6, r8
1109	EOR	r7, r7, r9
1110	ADDS	r4, r4, r6
1111	ADC	r5, r5, r7
1112	STRD	r4, r5, [r0]
1113	LDRD	r4, r5, [r0, #40]
1114	LDRD	r6, r7, [r0, #48]
1115	LDRD	r8, r9, [r0, #56]
1116	EOR	r6, r6, r8
1117	EOR	r7, r7, r9
1118	AND	r6, r6, r4
1119	AND	r7, r7, r5
1120	EOR	r6, r6, r8
1121	EOR	r7, r7, r9
1122	LDRD	r4, r5, [r0]
1123	LDRD	r8, r9, [sp, #56]
1124	ADDS	r4, r4, r6
1125	ADC	r5, r5, r7
1126	LDRD	r6, r7, [r3, #56]
1127	ADDS	r4, r4, r8
1128	ADC	r5, r5, r9
1129	LDRD	r8, r9, [r0, #32]
1130	ADDS	r4, r4, r6
1131	ADC	r5, r5, r7
1132	STRD	r4, r5, [r0]
1133	ADDS	r8, r8, r4
1134	ADC	r9, r9, r5
1135	LDRD	r4, r5, [r0, #8]
1136	STRD	r8, r9, [r0, #32]
1137	LSRS	r6, r4, #28
1138	LSRS	r7, r5, #28
1139	ORR	r7, r7, r4, LSL #4
1140	ORR	r6, r6, r5, LSL #4
1141	LSLS	r8, r4, #30
1142	LSLS	r9, r5, #30
1143	ORR	r9, r9, r4, LSR #2
1144	ORR	r8, r8, r5, LSR #2
1145	EOR	r6, r6, r8
1146	EOR	r7, r7, r9
1147	LSLS	r8, r4, #25
1148	LSLS	r9, r5, #25
1149	ORR	r9, r9, r4, LSR #7
1150	ORR	r8, r8, r5, LSR #7
1151	LDRD	r4, r5, [r0]
1152	EOR	r6, r6, r8
1153	EOR	r7, r7, r9
1154	ADDS	r4, r4, r6
1155	ADC	r5, r5, r7
1156	LDRD	r8, r9, [r0, #8]
1157	LDRD	r6, r7, [r0, #16]
1158	STRD	r4, r5, [r0]
1159	EOR	r8, r8, r6
1160	EOR	r9, r9, r7
1161	AND	r10, r10, r8
1162	AND	r11, r11, r9
1163	EOR	r10, r10, r6
1164	EOR	r11, r11, r7
1165	LDRD	r6, r7, [r0]
1166	ADDS	r6, r6, r10
1167	ADC	r7, r7, r11
1168	STRD	r6, r7, [r0]
1169	MOV	r10, r8
1170	MOV	r11, r9
1171	/* Calc new W[7] */
1172	LDRD	r4, r5, [sp, #40]
1173	LSRS	r6, r4, #19
1174	LSRS	r7, r5, #19
1175	ORR	r7, r7, r4, LSL #13
1176	ORR	r6, r6, r5, LSL #13
1177	LSLS	r8, r4, #3
1178	LSLS	r9, r5, #3
1179	ORR	r9, r9, r4, LSR #29
1180	ORR	r8, r8, r5, LSR #29
1181	EOR	r7, r7, r9
1182	EOR	r6, r6, r8
1183	LSRS	r8, r4, #6
1184	LSRS	r9, r5, #6
1185	ORR	r8, r8, r5, LSL #26
1186	EOR	r7, r7, r9
1187	EOR	r6, r6, r8
1188	LDRD	r4, r5, [sp, #56]
1189	LDRD	r8, r9, [sp]
1190	ADDS	r4, r4, r6
1191	ADC	r5, r5, r7
1192	ADDS	r4, r4, r8
1193	ADC	r5, r5, r9
1194	STRD	r4, r5, [sp, #56]
1195	LDRD	r4, r5, [sp, #64]
1196	LSRS	r6, r4, #1
1197	LSRS	r7, r5, #1
1198	ORR	r7, r7, r4, LSL #31
1199	ORR	r6, r6, r5, LSL #31
1200	LSRS	r8, r4, #8
1201	LSRS	r9, r5, #8
1202	ORR	r9, r9, r4, LSL #24
1203	ORR	r8, r8, r5, LSL #24
1204	EOR	r7, r7, r9
1205	EOR	r6, r6, r8
1206	LSRS	r8, r4, #7
1207	LSRS	r9, r5, #7
1208	ORR	r8, r8, r5, LSL #25
1209	EOR	r7, r7, r9
1210	EOR	r6, r6, r8
1211	LDRD	r4, r5, [sp, #56]
1212	ADDS	r4, r4, r6
1213	ADC	r5, r5, r7
1214	STRD	r4, r5, [sp, #56]
1215	/* Round 8 */
1216	LDRD	r4, r5, [r0, #32]
1217	LSRS	r6, r4, #14
1218	LSRS	r7, r5, #14
1219	ORR	r7, r7, r4, LSL #18
1220	ORR	r6, r6, r5, LSL #18
1221	LSRS	r8, r4, #18
1222	LSRS	r9, r5, #18
1223	ORR	r9, r9, r4, LSL #14
1224	ORR	r8, r8, r5, LSL #14
1225	EOR	r6, r6, r8
1226	EOR	r7, r7, r9
1227	LSLS	r8, r4, #23
1228	LSLS	r9, r5, #23
1229	ORR	r9, r9, r4, LSR #9
1230	ORR	r8, r8, r5, LSR #9
1231	LDRD	r4, r5, [r0, #56]
1232	EOR	r6, r6, r8
1233	EOR	r7, r7, r9
1234	ADDS	r4, r4, r6
1235	ADC	r5, r5, r7
1236	STRD	r4, r5, [r0, #56]
1237	LDRD	r4, r5, [r0, #32]
1238	LDRD	r6, r7, [r0, #40]
1239	LDRD	r8, r9, [r0, #48]
1240	EOR	r6, r6, r8
1241	EOR	r7, r7, r9
1242	AND	r6, r6, r4
1243	AND	r7, r7, r5
1244	EOR	r6, r6, r8
1245	EOR	r7, r7, r9
1246	LDRD	r4, r5, [r0, #56]
1247	LDRD	r8, r9, [sp, #64]
1248	ADDS	r4, r4, r6
1249	ADC	r5, r5, r7
1250	LDRD	r6, r7, [r3, #64]
1251	ADDS	r4, r4, r8
1252	ADC	r5, r5, r9
1253	LDRD	r8, r9, [r0, #24]
1254	ADDS	r4, r4, r6
1255	ADC	r5, r5, r7
1256	STRD	r4, r5, [r0, #56]
1257	ADDS	r8, r8, r4
1258	ADC	r9, r9, r5
1259	LDRD	r4, r5, [r0]
1260	STRD	r8, r9, [r0, #24]
1261	LSRS	r6, r4, #28
1262	LSRS	r7, r5, #28
1263	ORR	r7, r7, r4, LSL #4
1264	ORR	r6, r6, r5, LSL #4
1265	LSLS	r8, r4, #30
1266	LSLS	r9, r5, #30
1267	ORR	r9, r9, r4, LSR #2
1268	ORR	r8, r8, r5, LSR #2
1269	EOR	r6, r6, r8
1270	EOR	r7, r7, r9
1271	LSLS	r8, r4, #25
1272	LSLS	r9, r5, #25
1273	ORR	r9, r9, r4, LSR #7
1274	ORR	r8, r8, r5, LSR #7
1275	LDRD	r4, r5, [r0, #56]
1276	EOR	r6, r6, r8
1277	EOR	r7, r7, r9
1278	ADDS	r4, r4, r6
1279	ADC	r5, r5, r7
1280	LDRD	r8, r9, [r0]
1281	LDRD	r6, r7, [r0, #8]
1282	STRD	r4, r5, [r0, #56]
1283	EOR	r8, r8, r6
1284	EOR	r9, r9, r7
1285	AND	r10, r10, r8
1286	AND	r11, r11, r9
1287	EOR	r10, r10, r6
1288	EOR	r11, r11, r7
1289	LDRD	r6, r7, [r0, #56]
1290	ADDS	r6, r6, r10
1291	ADC	r7, r7, r11
1292	STRD	r6, r7, [r0, #56]
1293	MOV	r10, r8
1294	MOV	r11, r9
1295	/* Calc new W[8] */
1296	LDRD	r4, r5, [sp, #48]
1297	LSRS	r6, r4, #19
1298	LSRS	r7, r5, #19
1299	ORR	r7, r7, r4, LSL #13
1300	ORR	r6, r6, r5, LSL #13
1301	LSLS	r8, r4, #3
1302	LSLS	r9, r5, #3
1303	ORR	r9, r9, r4, LSR #29
1304	ORR	r8, r8, r5, LSR #29
1305	EOR	r7, r7, r9
1306	EOR	r6, r6, r8
1307	LSRS	r8, r4, #6
1308	LSRS	r9, r5, #6
1309	ORR	r8, r8, r5, LSL #26
1310	EOR	r7, r7, r9
1311	EOR	r6, r6, r8
1312	LDRD	r4, r5, [sp, #64]
1313	LDRD	r8, r9, [sp, #8]
1314	ADDS	r4, r4, r6
1315	ADC	r5, r5, r7
1316	ADDS	r4, r4, r8
1317	ADC	r5, r5, r9
1318	STRD	r4, r5, [sp, #64]
1319	LDRD	r4, r5, [sp, #72]
1320	LSRS	r6, r4, #1
1321	LSRS	r7, r5, #1
1322	ORR	r7, r7, r4, LSL #31
1323	ORR	r6, r6, r5, LSL #31
1324	LSRS	r8, r4, #8
1325	LSRS	r9, r5, #8
1326	ORR	r9, r9, r4, LSL #24
1327	ORR	r8, r8, r5, LSL #24
1328	EOR	r7, r7, r9
1329	EOR	r6, r6, r8
1330	LSRS	r8, r4, #7
1331	LSRS	r9, r5, #7
1332	ORR	r8, r8, r5, LSL #25
1333	EOR	r7, r7, r9
1334	EOR	r6, r6, r8
1335	LDRD	r4, r5, [sp, #64]
1336	ADDS	r4, r4, r6
1337	ADC	r5, r5, r7
1338	STRD	r4, r5, [sp, #64]
1339	/* Round 9 */
1340	LDRD	r4, r5, [r0, #24]
1341	LSRS	r6, r4, #14
1342	LSRS	r7, r5, #14
1343	ORR	r7, r7, r4, LSL #18
1344	ORR	r6, r6, r5, LSL #18
1345	LSRS	r8, r4, #18
1346	LSRS	r9, r5, #18
1347	ORR	r9, r9, r4, LSL #14
1348	ORR	r8, r8, r5, LSL #14
1349	EOR	r6, r6, r8
1350	EOR	r7, r7, r9
1351	LSLS	r8, r4, #23
1352	LSLS	r9, r5, #23
1353	ORR	r9, r9, r4, LSR #9
1354	ORR	r8, r8, r5, LSR #9
1355	LDRD	r4, r5, [r0, #48]
1356	EOR	r6, r6, r8
1357	EOR	r7, r7, r9
1358	ADDS	r4, r4, r6
1359	ADC	r5, r5, r7
1360	STRD	r4, r5, [r0, #48]
1361	LDRD	r4, r5, [r0, #24]
1362	LDRD	r6, r7, [r0, #32]
1363	LDRD	r8, r9, [r0, #40]
1364	EOR	r6, r6, r8
1365	EOR	r7, r7, r9
1366	AND	r6, r6, r4
1367	AND	r7, r7, r5
1368	EOR	r6, r6, r8
1369	EOR	r7, r7, r9
1370	LDRD	r4, r5, [r0, #48]
1371	LDRD	r8, r9, [sp, #72]
1372	ADDS	r4, r4, r6
1373	ADC	r5, r5, r7
1374	LDRD	r6, r7, [r3, #72]
1375	ADDS	r4, r4, r8
1376	ADC	r5, r5, r9
1377	LDRD	r8, r9, [r0, #16]
1378	ADDS	r4, r4, r6
1379	ADC	r5, r5, r7
1380	STRD	r4, r5, [r0, #48]
1381	ADDS	r8, r8, r4
1382	ADC	r9, r9, r5
1383	LDRD	r4, r5, [r0, #56]
1384	STRD	r8, r9, [r0, #16]
1385	LSRS	r6, r4, #28
1386	LSRS	r7, r5, #28
1387	ORR	r7, r7, r4, LSL #4
1388	ORR	r6, r6, r5, LSL #4
1389	LSLS	r8, r4, #30
1390	LSLS	r9, r5, #30
1391	ORR	r9, r9, r4, LSR #2
1392	ORR	r8, r8, r5, LSR #2
1393	EOR	r6, r6, r8
1394	EOR	r7, r7, r9
1395	LSLS	r8, r4, #25
1396	LSLS	r9, r5, #25
1397	ORR	r9, r9, r4, LSR #7
1398	ORR	r8, r8, r5, LSR #7
1399	LDRD	r4, r5, [r0, #48]
1400	EOR	r6, r6, r8
1401	EOR	r7, r7, r9
1402	ADDS	r4, r4, r6
1403	ADC	r5, r5, r7
1404	LDRD	r8, r9, [r0, #56]
1405	LDRD	r6, r7, [r0]
1406	STRD	r4, r5, [r0, #48]
1407	EOR	r8, r8, r6
1408	EOR	r9, r9, r7
1409	AND	r10, r10, r8
1410	AND	r11, r11, r9
1411	EOR	r10, r10, r6
1412	EOR	r11, r11, r7
1413	LDRD	r6, r7, [r0, #48]
1414	ADDS	r6, r6, r10
1415	ADC	r7, r7, r11
1416	STRD	r6, r7, [r0, #48]
1417	MOV	r10, r8
1418	MOV	r11, r9
1419	/* Calc new W[9] */
1420	LDRD	r4, r5, [sp, #56]
1421	LSRS	r6, r4, #19
1422	LSRS	r7, r5, #19
1423	ORR	r7, r7, r4, LSL #13
1424	ORR	r6, r6, r5, LSL #13
1425	LSLS	r8, r4, #3
1426	LSLS	r9, r5, #3
1427	ORR	r9, r9, r4, LSR #29
1428	ORR	r8, r8, r5, LSR #29
1429	EOR	r7, r7, r9
1430	EOR	r6, r6, r8
1431	LSRS	r8, r4, #6
1432	LSRS	r9, r5, #6
1433	ORR	r8, r8, r5, LSL #26
1434	EOR	r7, r7, r9
1435	EOR	r6, r6, r8
1436	LDRD	r4, r5, [sp, #72]
1437	LDRD	r8, r9, [sp, #16]
1438	ADDS	r4, r4, r6
1439	ADC	r5, r5, r7
1440	ADDS	r4, r4, r8
1441	ADC	r5, r5, r9
1442	STRD	r4, r5, [sp, #72]
1443	LDRD	r4, r5, [sp, #80]
1444	LSRS	r6, r4, #1
1445	LSRS	r7, r5, #1
1446	ORR	r7, r7, r4, LSL #31
1447	ORR	r6, r6, r5, LSL #31
1448	LSRS	r8, r4, #8
1449	LSRS	r9, r5, #8
1450	ORR	r9, r9, r4, LSL #24
1451	ORR	r8, r8, r5, LSL #24
1452	EOR	r7, r7, r9
1453	EOR	r6, r6, r8
1454	LSRS	r8, r4, #7
1455	LSRS	r9, r5, #7
1456	ORR	r8, r8, r5, LSL #25
1457	EOR	r7, r7, r9
1458	EOR	r6, r6, r8
1459	LDRD	r4, r5, [sp, #72]
1460	ADDS	r4, r4, r6
1461	ADC	r5, r5, r7
1462	STRD	r4, r5, [sp, #72]
1463	/* Round 10 */
1464	LDRD	r4, r5, [r0, #16]
1465	LSRS	r6, r4, #14
1466	LSRS	r7, r5, #14
1467	ORR	r7, r7, r4, LSL #18
1468	ORR	r6, r6, r5, LSL #18
1469	LSRS	r8, r4, #18
1470	LSRS	r9, r5, #18
1471	ORR	r9, r9, r4, LSL #14
1472	ORR	r8, r8, r5, LSL #14
1473	EOR	r6, r6, r8
1474	EOR	r7, r7, r9
1475	LSLS	r8, r4, #23
1476	LSLS	r9, r5, #23
1477	ORR	r9, r9, r4, LSR #9
1478	ORR	r8, r8, r5, LSR #9
1479	LDRD	r4, r5, [r0, #40]
1480	EOR	r6, r6, r8
1481	EOR	r7, r7, r9
1482	ADDS	r4, r4, r6
1483	ADC	r5, r5, r7
1484	STRD	r4, r5, [r0, #40]
1485	LDRD	r4, r5, [r0, #16]
1486	LDRD	r6, r7, [r0, #24]
1487	LDRD	r8, r9, [r0, #32]
1488	EOR	r6, r6, r8
1489	EOR	r7, r7, r9
1490	AND	r6, r6, r4
1491	AND	r7, r7, r5
1492	EOR	r6, r6, r8
1493	EOR	r7, r7, r9
1494	LDRD	r4, r5, [r0, #40]
1495	LDRD	r8, r9, [sp, #80]
1496	ADDS	r4, r4, r6
1497	ADC	r5, r5, r7
1498	LDRD	r6, r7, [r3, #80]
1499	ADDS	r4, r4, r8
1500	ADC	r5, r5, r9
1501	LDRD	r8, r9, [r0, #8]
1502	ADDS	r4, r4, r6
1503	ADC	r5, r5, r7
1504	STRD	r4, r5, [r0, #40]
1505	ADDS	r8, r8, r4
1506	ADC	r9, r9, r5
1507	LDRD	r4, r5, [r0, #48]
1508	STRD	r8, r9, [r0, #8]
1509	LSRS	r6, r4, #28
1510	LSRS	r7, r5, #28
1511	ORR	r7, r7, r4, LSL #4
1512	ORR	r6, r6, r5, LSL #4
1513	LSLS	r8, r4, #30
1514	LSLS	r9, r5, #30
1515	ORR	r9, r9, r4, LSR #2
1516	ORR	r8, r8, r5, LSR #2
1517	EOR	r6, r6, r8
1518	EOR	r7, r7, r9
1519	LSLS	r8, r4, #25
1520	LSLS	r9, r5, #25
1521	ORR	r9, r9, r4, LSR #7
1522	ORR	r8, r8, r5, LSR #7
1523	LDRD	r4, r5, [r0, #40]
1524	EOR	r6, r6, r8
1525	EOR	r7, r7, r9
1526	ADDS	r4, r4, r6
1527	ADC	r5, r5, r7
1528	LDRD	r8, r9, [r0, #48]
1529	LDRD	r6, r7, [r0, #56]
1530	STRD	r4, r5, [r0, #40]
1531	EOR	r8, r8, r6
1532	EOR	r9, r9, r7
1533	AND	r10, r10, r8
1534	AND	r11, r11, r9
1535	EOR	r10, r10, r6
1536	EOR	r11, r11, r7
1537	LDRD	r6, r7, [r0, #40]
1538	ADDS	r6, r6, r10
1539	ADC	r7, r7, r11
1540	STRD	r6, r7, [r0, #40]
1541	MOV	r10, r8
1542	MOV	r11, r9
1543	/* Calc new W[10] */
1544	LDRD	r4, r5, [sp, #64]
1545	LSRS	r6, r4, #19
1546	LSRS	r7, r5, #19
1547	ORR	r7, r7, r4, LSL #13
1548	ORR	r6, r6, r5, LSL #13
1549	LSLS	r8, r4, #3
1550	LSLS	r9, r5, #3
1551	ORR	r9, r9, r4, LSR #29
1552	ORR	r8, r8, r5, LSR #29
1553	EOR	r7, r7, r9
1554	EOR	r6, r6, r8
1555	LSRS	r8, r4, #6
1556	LSRS	r9, r5, #6
1557	ORR	r8, r8, r5, LSL #26
1558	EOR	r7, r7, r9
1559	EOR	r6, r6, r8
1560	LDRD	r4, r5, [sp, #80]
1561	LDRD	r8, r9, [sp, #24]
1562	ADDS	r4, r4, r6
1563	ADC	r5, r5, r7
1564	ADDS	r4, r4, r8
1565	ADC	r5, r5, r9
1566	STRD	r4, r5, [sp, #80]
1567	LDRD	r4, r5, [sp, #88]
1568	LSRS	r6, r4, #1
1569	LSRS	r7, r5, #1
1570	ORR	r7, r7, r4, LSL #31
1571	ORR	r6, r6, r5, LSL #31
1572	LSRS	r8, r4, #8
1573	LSRS	r9, r5, #8
1574	ORR	r9, r9, r4, LSL #24
1575	ORR	r8, r8, r5, LSL #24
1576	EOR	r7, r7, r9
1577	EOR	r6, r6, r8
1578	LSRS	r8, r4, #7
1579	LSRS	r9, r5, #7
1580	ORR	r8, r8, r5, LSL #25
1581	EOR	r7, r7, r9
1582	EOR	r6, r6, r8
1583	LDRD	r4, r5, [sp, #80]
1584	ADDS	r4, r4, r6
1585	ADC	r5, r5, r7
1586	STRD	r4, r5, [sp, #80]
1587	/* Round 11 */
1588	LDRD	r4, r5, [r0, #8]
1589	LSRS	r6, r4, #14
1590	LSRS	r7, r5, #14
1591	ORR	r7, r7, r4, LSL #18
1592	ORR	r6, r6, r5, LSL #18
1593	LSRS	r8, r4, #18
1594	LSRS	r9, r5, #18
1595	ORR	r9, r9, r4, LSL #14
1596	ORR	r8, r8, r5, LSL #14
1597	EOR	r6, r6, r8
1598	EOR	r7, r7, r9
1599	LSLS	r8, r4, #23
1600	LSLS	r9, r5, #23
1601	ORR	r9, r9, r4, LSR #9
1602	ORR	r8, r8, r5, LSR #9
1603	LDRD	r4, r5, [r0, #32]
1604	EOR	r6, r6, r8
1605	EOR	r7, r7, r9
1606	ADDS	r4, r4, r6
1607	ADC	r5, r5, r7
1608	STRD	r4, r5, [r0, #32]
1609	LDRD	r4, r5, [r0, #8]
1610	LDRD	r6, r7, [r0, #16]
1611	LDRD	r8, r9, [r0, #24]
1612	EOR	r6, r6, r8
1613	EOR	r7, r7, r9
1614	AND	r6, r6, r4
1615	AND	r7, r7, r5
1616	EOR	r6, r6, r8
1617	EOR	r7, r7, r9
1618	LDRD	r4, r5, [r0, #32]
1619	LDRD	r8, r9, [sp, #88]
1620	ADDS	r4, r4, r6
1621	ADC	r5, r5, r7
1622	LDRD	r6, r7, [r3, #88]
1623	ADDS	r4, r4, r8
1624	ADC	r5, r5, r9
1625	LDRD	r8, r9, [r0]
1626	ADDS	r4, r4, r6
1627	ADC	r5, r5, r7
1628	STRD	r4, r5, [r0, #32]
1629	ADDS	r8, r8, r4
1630	ADC	r9, r9, r5
1631	LDRD	r4, r5, [r0, #40]
1632	STRD	r8, r9, [r0]
1633	LSRS	r6, r4, #28
1634	LSRS	r7, r5, #28
1635	ORR	r7, r7, r4, LSL #4
1636	ORR	r6, r6, r5, LSL #4
1637	LSLS	r8, r4, #30
1638	LSLS	r9, r5, #30
1639	ORR	r9, r9, r4, LSR #2
1640	ORR	r8, r8, r5, LSR #2
1641	EOR	r6, r6, r8
1642	EOR	r7, r7, r9
1643	LSLS	r8, r4, #25
1644	LSLS	r9, r5, #25
1645	ORR	r9, r9, r4, LSR #7
1646	ORR	r8, r8, r5, LSR #7
1647	LDRD	r4, r5, [r0, #32]
1648	EOR	r6, r6, r8
1649	EOR	r7, r7, r9
1650	ADDS	r4, r4, r6
1651	ADC	r5, r5, r7
1652	LDRD	r8, r9, [r0, #40]
1653	LDRD	r6, r7, [r0, #48]
1654	STRD	r4, r5, [r0, #32]
1655	EOR	r8, r8, r6
1656	EOR	r9, r9, r7
1657	AND	r10, r10, r8
1658	AND	r11, r11, r9
1659	EOR	r10, r10, r6
1660	EOR	r11, r11, r7
1661	LDRD	r6, r7, [r0, #32]
1662	ADDS	r6, r6, r10
1663	ADC	r7, r7, r11
1664	STRD	r6, r7, [r0, #32]
1665	MOV	r10, r8
1666	MOV	r11, r9
1667	/* Calc new W[11] */
1668	LDRD	r4, r5, [sp, #72]
1669	LSRS	r6, r4, #19
1670	LSRS	r7, r5, #19
1671	ORR	r7, r7, r4, LSL #13
1672	ORR	r6, r6, r5, LSL #13
1673	LSLS	r8, r4, #3
1674	LSLS	r9, r5, #3
1675	ORR	r9, r9, r4, LSR #29
1676	ORR	r8, r8, r5, LSR #29
1677	EOR	r7, r7, r9
1678	EOR	r6, r6, r8
1679	LSRS	r8, r4, #6
1680	LSRS	r9, r5, #6
1681	ORR	r8, r8, r5, LSL #26
1682	EOR	r7, r7, r9
1683	EOR	r6, r6, r8
1684	LDRD	r4, r5, [sp, #88]
1685	LDRD	r8, r9, [sp, #32]
1686	ADDS	r4, r4, r6
1687	ADC	r5, r5, r7
1688	ADDS	r4, r4, r8
1689	ADC	r5, r5, r9
1690	STRD	r4, r5, [sp, #88]
1691	LDRD	r4, r5, [sp, #96]
1692	LSRS	r6, r4, #1
1693	LSRS	r7, r5, #1
1694	ORR	r7, r7, r4, LSL #31
1695	ORR	r6, r6, r5, LSL #31
1696	LSRS	r8, r4, #8
1697	LSRS	r9, r5, #8
1698	ORR	r9, r9, r4, LSL #24
1699	ORR	r8, r8, r5, LSL #24
1700	EOR	r7, r7, r9
1701	EOR	r6, r6, r8
1702	LSRS	r8, r4, #7
1703	LSRS	r9, r5, #7
1704	ORR	r8, r8, r5, LSL #25
1705	EOR	r7, r7, r9
1706	EOR	r6, r6, r8
1707	LDRD	r4, r5, [sp, #88]
1708	ADDS	r4, r4, r6
1709	ADC	r5, r5, r7
1710	STRD	r4, r5, [sp, #88]
1711	/* Round 12 */
1712	LDRD	r4, r5, [r0]
1713	LSRS	r6, r4, #14
1714	LSRS	r7, r5, #14
1715	ORR	r7, r7, r4, LSL #18
1716	ORR	r6, r6, r5, LSL #18
1717	LSRS	r8, r4, #18
1718	LSRS	r9, r5, #18
1719	ORR	r9, r9, r4, LSL #14
1720	ORR	r8, r8, r5, LSL #14
1721	EOR	r6, r6, r8
1722	EOR	r7, r7, r9
1723	LSLS	r8, r4, #23
1724	LSLS	r9, r5, #23
1725	ORR	r9, r9, r4, LSR #9
1726	ORR	r8, r8, r5, LSR #9
1727	LDRD	r4, r5, [r0, #24]
1728	EOR	r6, r6, r8
1729	EOR	r7, r7, r9
1730	ADDS	r4, r4, r6
1731	ADC	r5, r5, r7
1732	STRD	r4, r5, [r0, #24]
1733	LDRD	r4, r5, [r0]
1734	LDRD	r6, r7, [r0, #8]
1735	LDRD	r8, r9, [r0, #16]
1736	EOR	r6, r6, r8
1737	EOR	r7, r7, r9
1738	AND	r6, r6, r4
1739	AND	r7, r7, r5
1740	EOR	r6, r6, r8
1741	EOR	r7, r7, r9
1742	LDRD	r4, r5, [r0, #24]
1743	LDRD	r8, r9, [sp, #96]
1744	ADDS	r4, r4, r6
1745	ADC	r5, r5, r7
1746	LDRD	r6, r7, [r3, #96]
1747	ADDS	r4, r4, r8
1748	ADC	r5, r5, r9
1749	LDRD	r8, r9, [r0, #56]
1750	ADDS	r4, r4, r6
1751	ADC	r5, r5, r7
1752	STRD	r4, r5, [r0, #24]
1753	ADDS	r8, r8, r4
1754	ADC	r9, r9, r5
1755	LDRD	r4, r5, [r0, #32]
1756	STRD	r8, r9, [r0, #56]
1757	LSRS	r6, r4, #28
1758	LSRS	r7, r5, #28
1759	ORR	r7, r7, r4, LSL #4
1760	ORR	r6, r6, r5, LSL #4
1761	LSLS	r8, r4, #30
1762	LSLS	r9, r5, #30
1763	ORR	r9, r9, r4, LSR #2
1764	ORR	r8, r8, r5, LSR #2
1765	EOR	r6, r6, r8
1766	EOR	r7, r7, r9
1767	LSLS	r8, r4, #25
1768	LSLS	r9, r5, #25
1769	ORR	r9, r9, r4, LSR #7
1770	ORR	r8, r8, r5, LSR #7
1771	LDRD	r4, r5, [r0, #24]
1772	EOR	r6, r6, r8
1773	EOR	r7, r7, r9
1774	ADDS	r4, r4, r6
1775	ADC	r5, r5, r7
1776	LDRD	r8, r9, [r0, #32]
1777	LDRD	r6, r7, [r0, #40]
1778	STRD	r4, r5, [r0, #24]
1779	EOR	r8, r8, r6
1780	EOR	r9, r9, r7
1781	AND	r10, r10, r8
1782	AND	r11, r11, r9
1783	EOR	r10, r10, r6
1784	EOR	r11, r11, r7
1785	LDRD	r6, r7, [r0, #24]
1786	ADDS	r6, r6, r10
1787	ADC	r7, r7, r11
1788	STRD	r6, r7, [r0, #24]
1789	MOV	r10, r8
1790	MOV	r11, r9
1791	/* Calc new W[12] */
1792	LDRD	r4, r5, [sp, #80]
1793	LSRS	r6, r4, #19
1794	LSRS	r7, r5, #19
1795	ORR	r7, r7, r4, LSL #13
1796	ORR	r6, r6, r5, LSL #13
1797	LSLS	r8, r4, #3
1798	LSLS	r9, r5, #3
1799	ORR	r9, r9, r4, LSR #29
1800	ORR	r8, r8, r5, LSR #29
1801	EOR	r7, r7, r9
1802	EOR	r6, r6, r8
1803	LSRS	r8, r4, #6
1804	LSRS	r9, r5, #6
1805	ORR	r8, r8, r5, LSL #26
1806	EOR	r7, r7, r9
1807	EOR	r6, r6, r8
1808	LDRD	r4, r5, [sp, #96]
1809	LDRD	r8, r9, [sp, #40]
1810	ADDS	r4, r4, r6
1811	ADC	r5, r5, r7
1812	ADDS	r4, r4, r8
1813	ADC	r5, r5, r9
1814	STRD	r4, r5, [sp, #96]
1815	LDRD	r4, r5, [sp, #104]
1816	LSRS	r6, r4, #1
1817	LSRS	r7, r5, #1
1818	ORR	r7, r7, r4, LSL #31
1819	ORR	r6, r6, r5, LSL #31
1820	LSRS	r8, r4, #8
1821	LSRS	r9, r5, #8
1822	ORR	r9, r9, r4, LSL #24
1823	ORR	r8, r8, r5, LSL #24
1824	EOR	r7, r7, r9
1825	EOR	r6, r6, r8
1826	LSRS	r8, r4, #7
1827	LSRS	r9, r5, #7
1828	ORR	r8, r8, r5, LSL #25
1829	EOR	r7, r7, r9
1830	EOR	r6, r6, r8
1831	LDRD	r4, r5, [sp, #96]
1832	ADDS	r4, r4, r6
1833	ADC	r5, r5, r7
1834	STRD	r4, r5, [sp, #96]
1835	/* Round 13 */
1836	LDRD	r4, r5, [r0, #56]
1837	LSRS	r6, r4, #14
1838	LSRS	r7, r5, #14
1839	ORR	r7, r7, r4, LSL #18
1840	ORR	r6, r6, r5, LSL #18
1841	LSRS	r8, r4, #18
1842	LSRS	r9, r5, #18
1843	ORR	r9, r9, r4, LSL #14
1844	ORR	r8, r8, r5, LSL #14
1845	EOR	r6, r6, r8
1846	EOR	r7, r7, r9
1847	LSLS	r8, r4, #23
1848	LSLS	r9, r5, #23
1849	ORR	r9, r9, r4, LSR #9
1850	ORR	r8, r8, r5, LSR #9
1851	LDRD	r4, r5, [r0, #16]
1852	EOR	r6, r6, r8
1853	EOR	r7, r7, r9
1854	ADDS	r4, r4, r6
1855	ADC	r5, r5, r7
1856	STRD	r4, r5, [r0, #16]
1857	LDRD	r4, r5, [r0, #56]
1858	LDRD	r6, r7, [r0]
1859	LDRD	r8, r9, [r0, #8]
1860	EOR	r6, r6, r8
1861	EOR	r7, r7, r9
1862	AND	r6, r6, r4
1863	AND	r7, r7, r5
1864	EOR	r6, r6, r8
1865	EOR	r7, r7, r9
1866	LDRD	r4, r5, [r0, #16]
1867	LDRD	r8, r9, [sp, #104]
1868	ADDS	r4, r4, r6
1869	ADC	r5, r5, r7
1870	LDRD	r6, r7, [r3, #104]
1871	ADDS	r4, r4, r8
1872	ADC	r5, r5, r9
1873	LDRD	r8, r9, [r0, #48]
1874	ADDS	r4, r4, r6
1875	ADC	r5, r5, r7
1876	STRD	r4, r5, [r0, #16]
1877	ADDS	r8, r8, r4
1878	ADC	r9, r9, r5
1879	LDRD	r4, r5, [r0, #24]
1880	STRD	r8, r9, [r0, #48]
1881	LSRS	r6, r4, #28
1882	LSRS	r7, r5, #28
1883	ORR	r7, r7, r4, LSL #4
1884	ORR	r6, r6, r5, LSL #4
1885	LSLS	r8, r4, #30
1886	LSLS	r9, r5, #30
1887	ORR	r9, r9, r4, LSR #2
1888	ORR	r8, r8, r5, LSR #2
1889	EOR	r6, r6, r8
1890	EOR	r7, r7, r9
1891	LSLS	r8, r4, #25
1892	LSLS	r9, r5, #25
1893	ORR	r9, r9, r4, LSR #7
1894	ORR	r8, r8, r5, LSR #7
1895	LDRD	r4, r5, [r0, #16]
1896	EOR	r6, r6, r8
1897	EOR	r7, r7, r9
1898	ADDS	r4, r4, r6
1899	ADC	r5, r5, r7
1900	LDRD	r8, r9, [r0, #24]
1901	LDRD	r6, r7, [r0, #32]
1902	STRD	r4, r5, [r0, #16]
1903	EOR	r8, r8, r6
1904	EOR	r9, r9, r7
1905	AND	r10, r10, r8
1906	AND	r11, r11, r9
1907	EOR	r10, r10, r6
1908	EOR	r11, r11, r7
1909	LDRD	r6, r7, [r0, #16]
1910	ADDS	r6, r6, r10
1911	ADC	r7, r7, r11
1912	STRD	r6, r7, [r0, #16]
1913	MOV	r10, r8
1914	MOV	r11, r9
1915	/* Calc new W[13] */
1916	LDRD	r4, r5, [sp, #88]
1917	LSRS	r6, r4, #19
1918	LSRS	r7, r5, #19
1919	ORR	r7, r7, r4, LSL #13
1920	ORR	r6, r6, r5, LSL #13
1921	LSLS	r8, r4, #3
1922	LSLS	r9, r5, #3
1923	ORR	r9, r9, r4, LSR #29
1924	ORR	r8, r8, r5, LSR #29
1925	EOR	r7, r7, r9
1926	EOR	r6, r6, r8
1927	LSRS	r8, r4, #6
1928	LSRS	r9, r5, #6
1929	ORR	r8, r8, r5, LSL #26
1930	EOR	r7, r7, r9
1931	EOR	r6, r6, r8
1932	LDRD	r4, r5, [sp, #104]
1933	LDRD	r8, r9, [sp, #48]
1934	ADDS	r4, r4, r6
1935	ADC	r5, r5, r7
1936	ADDS	r4, r4, r8
1937	ADC	r5, r5, r9
1938	STRD	r4, r5, [sp, #104]
1939	LDRD	r4, r5, [sp, #112]
1940	LSRS	r6, r4, #1
1941	LSRS	r7, r5, #1
1942	ORR	r7, r7, r4, LSL #31
1943	ORR	r6, r6, r5, LSL #31
1944	LSRS	r8, r4, #8
1945	LSRS	r9, r5, #8
1946	ORR	r9, r9, r4, LSL #24
1947	ORR	r8, r8, r5, LSL #24
1948	EOR	r7, r7, r9
1949	EOR	r6, r6, r8
1950	LSRS	r8, r4, #7
1951	LSRS	r9, r5, #7
1952	ORR	r8, r8, r5, LSL #25
1953	EOR	r7, r7, r9
1954	EOR	r6, r6, r8
1955	LDRD	r4, r5, [sp, #104]
1956	ADDS	r4, r4, r6
1957	ADC	r5, r5, r7
1958	STRD	r4, r5, [sp, #104]
1959	/* Round 14 */
1960	LDRD	r4, r5, [r0, #48]
1961	LSRS	r6, r4, #14
1962	LSRS	r7, r5, #14
1963	ORR	r7, r7, r4, LSL #18
1964	ORR	r6, r6, r5, LSL #18
1965	LSRS	r8, r4, #18
1966	LSRS	r9, r5, #18
1967	ORR	r9, r9, r4, LSL #14
1968	ORR	r8, r8, r5, LSL #14
1969	EOR	r6, r6, r8
1970	EOR	r7, r7, r9
1971	LSLS	r8, r4, #23
1972	LSLS	r9, r5, #23
1973	ORR	r9, r9, r4, LSR #9
1974	ORR	r8, r8, r5, LSR #9
1975	LDRD	r4, r5, [r0, #8]
1976	EOR	r6, r6, r8
1977	EOR	r7, r7, r9
1978	ADDS	r4, r4, r6
1979	ADC	r5, r5, r7
1980	STRD	r4, r5, [r0, #8]
1981	LDRD	r4, r5, [r0, #48]
1982	LDRD	r6, r7, [r0, #56]
1983	LDRD	r8, r9, [r0]
1984	EOR	r6, r6, r8
1985	EOR	r7, r7, r9
1986	AND	r6, r6, r4
1987	AND	r7, r7, r5
1988	EOR	r6, r6, r8
1989	EOR	r7, r7, r9
1990	LDRD	r4, r5, [r0, #8]
1991	LDRD	r8, r9, [sp, #112]
1992	ADDS	r4, r4, r6
1993	ADC	r5, r5, r7
1994	LDRD	r6, r7, [r3, #112]
1995	ADDS	r4, r4, r8
1996	ADC	r5, r5, r9
1997	LDRD	r8, r9, [r0, #40]
1998	ADDS	r4, r4, r6
1999	ADC	r5, r5, r7
2000	STRD	r4, r5, [r0, #8]
2001	ADDS	r8, r8, r4
2002	ADC	r9, r9, r5
2003	LDRD	r4, r5, [r0, #16]
2004	STRD	r8, r9, [r0, #40]
2005	LSRS	r6, r4, #28
2006	LSRS	r7, r5, #28
2007	ORR	r7, r7, r4, LSL #4
2008	ORR	r6, r6, r5, LSL #4
2009	LSLS	r8, r4, #30
2010	LSLS	r9, r5, #30
2011	ORR	r9, r9, r4, LSR #2
2012	ORR	r8, r8, r5, LSR #2
2013	EOR	r6, r6, r8
2014	EOR	r7, r7, r9
2015	LSLS	r8, r4, #25
2016	LSLS	r9, r5, #25
2017	ORR	r9, r9, r4, LSR #7
2018	ORR	r8, r8, r5, LSR #7
2019	LDRD	r4, r5, [r0, #8]
2020	EOR	r6, r6, r8
2021	EOR	r7, r7, r9
2022	ADDS	r4, r4, r6
2023	ADC	r5, r5, r7
2024	LDRD	r8, r9, [r0, #16]
2025	LDRD	r6, r7, [r0, #24]
2026	STRD	r4, r5, [r0, #8]
2027	EOR	r8, r8, r6
2028	EOR	r9, r9, r7
2029	AND	r10, r10, r8
2030	AND	r11, r11, r9
2031	EOR	r10, r10, r6
2032	EOR	r11, r11, r7
2033	LDRD	r6, r7, [r0, #8]
2034	ADDS	r6, r6, r10
2035	ADC	r7, r7, r11
2036	STRD	r6, r7, [r0, #8]
2037	MOV	r10, r8
2038	MOV	r11, r9
2039	/* Calc new W[14] */
2040	LDRD	r4, r5, [sp, #96]
2041	LSRS	r6, r4, #19
2042	LSRS	r7, r5, #19
2043	ORR	r7, r7, r4, LSL #13
2044	ORR	r6, r6, r5, LSL #13
2045	LSLS	r8, r4, #3
2046	LSLS	r9, r5, #3
2047	ORR	r9, r9, r4, LSR #29
2048	ORR	r8, r8, r5, LSR #29
2049	EOR	r7, r7, r9
2050	EOR	r6, r6, r8
2051	LSRS	r8, r4, #6
2052	LSRS	r9, r5, #6
2053	ORR	r8, r8, r5, LSL #26
2054	EOR	r7, r7, r9
2055	EOR	r6, r6, r8
2056	LDRD	r4, r5, [sp, #112]
2057	LDRD	r8, r9, [sp, #56]
2058	ADDS	r4, r4, r6
2059	ADC	r5, r5, r7
2060	ADDS	r4, r4, r8
2061	ADC	r5, r5, r9
2062	STRD	r4, r5, [sp, #112]
2063	LDRD	r4, r5, [sp, #120]
2064	LSRS	r6, r4, #1
2065	LSRS	r7, r5, #1
2066	ORR	r7, r7, r4, LSL #31
2067	ORR	r6, r6, r5, LSL #31
2068	LSRS	r8, r4, #8
2069	LSRS	r9, r5, #8
2070	ORR	r9, r9, r4, LSL #24
2071	ORR	r8, r8, r5, LSL #24
2072	EOR	r7, r7, r9
2073	EOR	r6, r6, r8
2074	LSRS	r8, r4, #7
2075	LSRS	r9, r5, #7
2076	ORR	r8, r8, r5, LSL #25
2077	EOR	r7, r7, r9
2078	EOR	r6, r6, r8
2079	LDRD	r4, r5, [sp, #112]
2080	ADDS	r4, r4, r6
2081	ADC	r5, r5, r7
2082	STRD	r4, r5, [sp, #112]
2083	/* Round 15 */
2084	LDRD	r4, r5, [r0, #40]
2085	LSRS	r6, r4, #14
2086	LSRS	r7, r5, #14
2087	ORR	r7, r7, r4, LSL #18
2088	ORR	r6, r6, r5, LSL #18
2089	LSRS	r8, r4, #18
2090	LSRS	r9, r5, #18
2091	ORR	r9, r9, r4, LSL #14
2092	ORR	r8, r8, r5, LSL #14
2093	EOR	r6, r6, r8
2094	EOR	r7, r7, r9
2095	LSLS	r8, r4, #23
2096	LSLS	r9, r5, #23
2097	ORR	r9, r9, r4, LSR #9
2098	ORR	r8, r8, r5, LSR #9
2099	LDRD	r4, r5, [r0]
2100	EOR	r6, r6, r8
2101	EOR	r7, r7, r9
2102	ADDS	r4, r4, r6
2103	ADC	r5, r5, r7
2104	STRD	r4, r5, [r0]
2105	LDRD	r4, r5, [r0, #40]
2106	LDRD	r6, r7, [r0, #48]
2107	LDRD	r8, r9, [r0, #56]
2108	EOR	r6, r6, r8
2109	EOR	r7, r7, r9
2110	AND	r6, r6, r4
2111	AND	r7, r7, r5
2112	EOR	r6, r6, r8
2113	EOR	r7, r7, r9
2114	LDRD	r4, r5, [r0]
2115	LDRD	r8, r9, [sp, #120]
2116	ADDS	r4, r4, r6
2117	ADC	r5, r5, r7
2118	LDRD	r6, r7, [r3, #120]
2119	ADDS	r4, r4, r8
2120	ADC	r5, r5, r9
2121	LDRD	r8, r9, [r0, #32]
2122	ADDS	r4, r4, r6
2123	ADC	r5, r5, r7
2124	STRD	r4, r5, [r0]
2125	ADDS	r8, r8, r4
2126	ADC	r9, r9, r5
2127	LDRD	r4, r5, [r0, #8]
2128	STRD	r8, r9, [r0, #32]
2129	LSRS	r6, r4, #28
2130	LSRS	r7, r5, #28
2131	ORR	r7, r7, r4, LSL #4
2132	ORR	r6, r6, r5, LSL #4
2133	LSLS	r8, r4, #30
2134	LSLS	r9, r5, #30
2135	ORR	r9, r9, r4, LSR #2
2136	ORR	r8, r8, r5, LSR #2
2137	EOR	r6, r6, r8
2138	EOR	r7, r7, r9
2139	LSLS	r8, r4, #25
2140	LSLS	r9, r5, #25
2141	ORR	r9, r9, r4, LSR #7
2142	ORR	r8, r8, r5, LSR #7
2143	LDRD	r4, r5, [r0]
2144	EOR	r6, r6, r8
2145	EOR	r7, r7, r9
2146	ADDS	r4, r4, r6
2147	ADC	r5, r5, r7
2148	LDRD	r8, r9, [r0, #8]
2149	LDRD	r6, r7, [r0, #16]
2150	STRD	r4, r5, [r0]
2151	EOR	r8, r8, r6
2152	EOR	r9, r9, r7
2153	AND	r10, r10, r8
2154	AND	r11, r11, r9
2155	EOR	r10, r10, r6
2156	EOR	r11, r11, r7
2157	LDRD	r6, r7, [r0]
2158	ADDS	r6, r6, r10
2159	ADC	r7, r7, r11
2160	STRD	r6, r7, [r0]
2161	MOV	r10, r8
2162	MOV	r11, r9
2163	/* Calc new W[15] */
2164	LDRD	r4, r5, [sp, #104]
2165	LSRS	r6, r4, #19
2166	LSRS	r7, r5, #19
2167	ORR	r7, r7, r4, LSL #13
2168	ORR	r6, r6, r5, LSL #13
2169	LSLS	r8, r4, #3
2170	LSLS	r9, r5, #3
2171	ORR	r9, r9, r4, LSR #29
2172	ORR	r8, r8, r5, LSR #29
2173	EOR	r7, r7, r9
2174	EOR	r6, r6, r8
2175	LSRS	r8, r4, #6
2176	LSRS	r9, r5, #6
2177	ORR	r8, r8, r5, LSL #26
2178	EOR	r7, r7, r9
2179	EOR	r6, r6, r8
2180	LDRD	r4, r5, [sp, #120]
2181	LDRD	r8, r9, [sp, #64]
2182	ADDS	r4, r4, r6
2183	ADC	r5, r5, r7
2184	ADDS	r4, r4, r8
2185	ADC	r5, r5, r9
2186	STRD	r4, r5, [sp, #120]
2187	LDRD	r4, r5, [sp]
2188	LSRS	r6, r4, #1
2189	LSRS	r7, r5, #1
2190	ORR	r7, r7, r4, LSL #31
2191	ORR	r6, r6, r5, LSL #31
2192	LSRS	r8, r4, #8
2193	LSRS	r9, r5, #8
2194	ORR	r9, r9, r4, LSL #24
2195	ORR	r8, r8, r5, LSL #24
2196	EOR	r7, r7, r9
2197	EOR	r6, r6, r8
2198	LSRS	r8, r4, #7
2199	LSRS	r9, r5, #7
2200	ORR	r8, r8, r5, LSL #25
2201	EOR	r7, r7, r9
2202	EOR	r6, r6, r8
2203	LDRD	r4, r5, [sp, #120]
2204	ADDS	r4, r4, r6
2205	ADC	r5, r5, r7
2206	STRD	r4, r5, [sp, #120]
2207	ADD	r3, r3, #0x80
2208	SUBS	r12, r12, #0x1
2209#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
2210	BNE	L_SHA512_transform_len_start
2211#else
2212	BNE.W	L_SHA512_transform_len_start
2213#endif
2214	/* Round 0 */
2215	LDRD	r4, r5, [r0, #32]
2216	LSRS	r6, r4, #14
2217	LSRS	r7, r5, #14
2218	ORR	r7, r7, r4, LSL #18
2219	ORR	r6, r6, r5, LSL #18
2220	LSRS	r8, r4, #18
2221	LSRS	r9, r5, #18
2222	ORR	r9, r9, r4, LSL #14
2223	ORR	r8, r8, r5, LSL #14
2224	EOR	r6, r6, r8
2225	EOR	r7, r7, r9
2226	LSLS	r8, r4, #23
2227	LSLS	r9, r5, #23
2228	ORR	r9, r9, r4, LSR #9
2229	ORR	r8, r8, r5, LSR #9
2230	LDRD	r4, r5, [r0, #56]
2231	EOR	r6, r6, r8
2232	EOR	r7, r7, r9
2233	ADDS	r4, r4, r6
2234	ADC	r5, r5, r7
2235	STRD	r4, r5, [r0, #56]
2236	LDRD	r4, r5, [r0, #32]
2237	LDRD	r6, r7, [r0, #40]
2238	LDRD	r8, r9, [r0, #48]
2239	EOR	r6, r6, r8
2240	EOR	r7, r7, r9
2241	AND	r6, r6, r4
2242	AND	r7, r7, r5
2243	EOR	r6, r6, r8
2244	EOR	r7, r7, r9
2245	LDRD	r4, r5, [r0, #56]
2246	LDRD	r8, r9, [sp]
2247	ADDS	r4, r4, r6
2248	ADC	r5, r5, r7
2249	LDRD	r6, r7, [r3]
2250	ADDS	r4, r4, r8
2251	ADC	r5, r5, r9
2252	LDRD	r8, r9, [r0, #24]
2253	ADDS	r4, r4, r6
2254	ADC	r5, r5, r7
2255	STRD	r4, r5, [r0, #56]
2256	ADDS	r8, r8, r4
2257	ADC	r9, r9, r5
2258	LDRD	r4, r5, [r0]
2259	STRD	r8, r9, [r0, #24]
2260	LSRS	r6, r4, #28
2261	LSRS	r7, r5, #28
2262	ORR	r7, r7, r4, LSL #4
2263	ORR	r6, r6, r5, LSL #4
2264	LSLS	r8, r4, #30
2265	LSLS	r9, r5, #30
2266	ORR	r9, r9, r4, LSR #2
2267	ORR	r8, r8, r5, LSR #2
2268	EOR	r6, r6, r8
2269	EOR	r7, r7, r9
2270	LSLS	r8, r4, #25
2271	LSLS	r9, r5, #25
2272	ORR	r9, r9, r4, LSR #7
2273	ORR	r8, r8, r5, LSR #7
2274	LDRD	r4, r5, [r0, #56]
2275	EOR	r6, r6, r8
2276	EOR	r7, r7, r9
2277	ADDS	r4, r4, r6
2278	ADC	r5, r5, r7
2279	LDRD	r8, r9, [r0]
2280	LDRD	r6, r7, [r0, #8]
2281	STRD	r4, r5, [r0, #56]
2282	EOR	r8, r8, r6
2283	EOR	r9, r9, r7
2284	AND	r10, r10, r8
2285	AND	r11, r11, r9
2286	EOR	r10, r10, r6
2287	EOR	r11, r11, r7
2288	LDRD	r6, r7, [r0, #56]
2289	ADDS	r6, r6, r10
2290	ADC	r7, r7, r11
2291	STRD	r6, r7, [r0, #56]
2292	MOV	r10, r8
2293	MOV	r11, r9
2294	/* Round 1 */
2295	LDRD	r4, r5, [r0, #24]
2296	LSRS	r6, r4, #14
2297	LSRS	r7, r5, #14
2298	ORR	r7, r7, r4, LSL #18
2299	ORR	r6, r6, r5, LSL #18
2300	LSRS	r8, r4, #18
2301	LSRS	r9, r5, #18
2302	ORR	r9, r9, r4, LSL #14
2303	ORR	r8, r8, r5, LSL #14
2304	EOR	r6, r6, r8
2305	EOR	r7, r7, r9
2306	LSLS	r8, r4, #23
2307	LSLS	r9, r5, #23
2308	ORR	r9, r9, r4, LSR #9
2309	ORR	r8, r8, r5, LSR #9
2310	LDRD	r4, r5, [r0, #48]
2311	EOR	r6, r6, r8
2312	EOR	r7, r7, r9
2313	ADDS	r4, r4, r6
2314	ADC	r5, r5, r7
2315	STRD	r4, r5, [r0, #48]
2316	LDRD	r4, r5, [r0, #24]
2317	LDRD	r6, r7, [r0, #32]
2318	LDRD	r8, r9, [r0, #40]
2319	EOR	r6, r6, r8
2320	EOR	r7, r7, r9
2321	AND	r6, r6, r4
2322	AND	r7, r7, r5
2323	EOR	r6, r6, r8
2324	EOR	r7, r7, r9
2325	LDRD	r4, r5, [r0, #48]
2326	LDRD	r8, r9, [sp, #8]
2327	ADDS	r4, r4, r6
2328	ADC	r5, r5, r7
2329	LDRD	r6, r7, [r3, #8]
2330	ADDS	r4, r4, r8
2331	ADC	r5, r5, r9
2332	LDRD	r8, r9, [r0, #16]
2333	ADDS	r4, r4, r6
2334	ADC	r5, r5, r7
2335	STRD	r4, r5, [r0, #48]
2336	ADDS	r8, r8, r4
2337	ADC	r9, r9, r5
2338	LDRD	r4, r5, [r0, #56]
2339	STRD	r8, r9, [r0, #16]
2340	LSRS	r6, r4, #28
2341	LSRS	r7, r5, #28
2342	ORR	r7, r7, r4, LSL #4
2343	ORR	r6, r6, r5, LSL #4
2344	LSLS	r8, r4, #30
2345	LSLS	r9, r5, #30
2346	ORR	r9, r9, r4, LSR #2
2347	ORR	r8, r8, r5, LSR #2
2348	EOR	r6, r6, r8
2349	EOR	r7, r7, r9
2350	LSLS	r8, r4, #25
2351	LSLS	r9, r5, #25
2352	ORR	r9, r9, r4, LSR #7
2353	ORR	r8, r8, r5, LSR #7
2354	LDRD	r4, r5, [r0, #48]
2355	EOR	r6, r6, r8
2356	EOR	r7, r7, r9
2357	ADDS	r4, r4, r6
2358	ADC	r5, r5, r7
2359	LDRD	r8, r9, [r0, #56]
2360	LDRD	r6, r7, [r0]
2361	STRD	r4, r5, [r0, #48]
2362	EOR	r8, r8, r6
2363	EOR	r9, r9, r7
2364	AND	r10, r10, r8
2365	AND	r11, r11, r9
2366	EOR	r10, r10, r6
2367	EOR	r11, r11, r7
2368	LDRD	r6, r7, [r0, #48]
2369	ADDS	r6, r6, r10
2370	ADC	r7, r7, r11
2371	STRD	r6, r7, [r0, #48]
2372	MOV	r10, r8
2373	MOV	r11, r9
2374	/* Round 2 */
2375	LDRD	r4, r5, [r0, #16]
2376	LSRS	r6, r4, #14
2377	LSRS	r7, r5, #14
2378	ORR	r7, r7, r4, LSL #18
2379	ORR	r6, r6, r5, LSL #18
2380	LSRS	r8, r4, #18
2381	LSRS	r9, r5, #18
2382	ORR	r9, r9, r4, LSL #14
2383	ORR	r8, r8, r5, LSL #14
2384	EOR	r6, r6, r8
2385	EOR	r7, r7, r9
2386	LSLS	r8, r4, #23
2387	LSLS	r9, r5, #23
2388	ORR	r9, r9, r4, LSR #9
2389	ORR	r8, r8, r5, LSR #9
2390	LDRD	r4, r5, [r0, #40]
2391	EOR	r6, r6, r8
2392	EOR	r7, r7, r9
2393	ADDS	r4, r4, r6
2394	ADC	r5, r5, r7
2395	STRD	r4, r5, [r0, #40]
2396	LDRD	r4, r5, [r0, #16]
2397	LDRD	r6, r7, [r0, #24]
2398	LDRD	r8, r9, [r0, #32]
2399	EOR	r6, r6, r8
2400	EOR	r7, r7, r9
2401	AND	r6, r6, r4
2402	AND	r7, r7, r5
2403	EOR	r6, r6, r8
2404	EOR	r7, r7, r9
2405	LDRD	r4, r5, [r0, #40]
2406	LDRD	r8, r9, [sp, #16]
2407	ADDS	r4, r4, r6
2408	ADC	r5, r5, r7
2409	LDRD	r6, r7, [r3, #16]
2410	ADDS	r4, r4, r8
2411	ADC	r5, r5, r9
2412	LDRD	r8, r9, [r0, #8]
2413	ADDS	r4, r4, r6
2414	ADC	r5, r5, r7
2415	STRD	r4, r5, [r0, #40]
2416	ADDS	r8, r8, r4
2417	ADC	r9, r9, r5
2418	LDRD	r4, r5, [r0, #48]
2419	STRD	r8, r9, [r0, #8]
2420	LSRS	r6, r4, #28
2421	LSRS	r7, r5, #28
2422	ORR	r7, r7, r4, LSL #4
2423	ORR	r6, r6, r5, LSL #4
2424	LSLS	r8, r4, #30
2425	LSLS	r9, r5, #30
2426	ORR	r9, r9, r4, LSR #2
2427	ORR	r8, r8, r5, LSR #2
2428	EOR	r6, r6, r8
2429	EOR	r7, r7, r9
2430	LSLS	r8, r4, #25
2431	LSLS	r9, r5, #25
2432	ORR	r9, r9, r4, LSR #7
2433	ORR	r8, r8, r5, LSR #7
2434	LDRD	r4, r5, [r0, #40]
2435	EOR	r6, r6, r8
2436	EOR	r7, r7, r9
2437	ADDS	r4, r4, r6
2438	ADC	r5, r5, r7
2439	LDRD	r8, r9, [r0, #48]
2440	LDRD	r6, r7, [r0, #56]
2441	STRD	r4, r5, [r0, #40]
2442	EOR	r8, r8, r6
2443	EOR	r9, r9, r7
2444	AND	r10, r10, r8
2445	AND	r11, r11, r9
2446	EOR	r10, r10, r6
2447	EOR	r11, r11, r7
2448	LDRD	r6, r7, [r0, #40]
2449	ADDS	r6, r6, r10
2450	ADC	r7, r7, r11
2451	STRD	r6, r7, [r0, #40]
2452	MOV	r10, r8
2453	MOV	r11, r9
2454	/* Round 3 */
2455	LDRD	r4, r5, [r0, #8]
2456	LSRS	r6, r4, #14
2457	LSRS	r7, r5, #14
2458	ORR	r7, r7, r4, LSL #18
2459	ORR	r6, r6, r5, LSL #18
2460	LSRS	r8, r4, #18
2461	LSRS	r9, r5, #18
2462	ORR	r9, r9, r4, LSL #14
2463	ORR	r8, r8, r5, LSL #14
2464	EOR	r6, r6, r8
2465	EOR	r7, r7, r9
2466	LSLS	r8, r4, #23
2467	LSLS	r9, r5, #23
2468	ORR	r9, r9, r4, LSR #9
2469	ORR	r8, r8, r5, LSR #9
2470	LDRD	r4, r5, [r0, #32]
2471	EOR	r6, r6, r8
2472	EOR	r7, r7, r9
2473	ADDS	r4, r4, r6
2474	ADC	r5, r5, r7
2475	STRD	r4, r5, [r0, #32]
2476	LDRD	r4, r5, [r0, #8]
2477	LDRD	r6, r7, [r0, #16]
2478	LDRD	r8, r9, [r0, #24]
2479	EOR	r6, r6, r8
2480	EOR	r7, r7, r9
2481	AND	r6, r6, r4
2482	AND	r7, r7, r5
2483	EOR	r6, r6, r8
2484	EOR	r7, r7, r9
2485	LDRD	r4, r5, [r0, #32]
2486	LDRD	r8, r9, [sp, #24]
2487	ADDS	r4, r4, r6
2488	ADC	r5, r5, r7
2489	LDRD	r6, r7, [r3, #24]
2490	ADDS	r4, r4, r8
2491	ADC	r5, r5, r9
2492	LDRD	r8, r9, [r0]
2493	ADDS	r4, r4, r6
2494	ADC	r5, r5, r7
2495	STRD	r4, r5, [r0, #32]
2496	ADDS	r8, r8, r4
2497	ADC	r9, r9, r5
2498	LDRD	r4, r5, [r0, #40]
2499	STRD	r8, r9, [r0]
2500	LSRS	r6, r4, #28
2501	LSRS	r7, r5, #28
2502	ORR	r7, r7, r4, LSL #4
2503	ORR	r6, r6, r5, LSL #4
2504	LSLS	r8, r4, #30
2505	LSLS	r9, r5, #30
2506	ORR	r9, r9, r4, LSR #2
2507	ORR	r8, r8, r5, LSR #2
2508	EOR	r6, r6, r8
2509	EOR	r7, r7, r9
2510	LSLS	r8, r4, #25
2511	LSLS	r9, r5, #25
2512	ORR	r9, r9, r4, LSR #7
2513	ORR	r8, r8, r5, LSR #7
2514	LDRD	r4, r5, [r0, #32]
2515	EOR	r6, r6, r8
2516	EOR	r7, r7, r9
2517	ADDS	r4, r4, r6
2518	ADC	r5, r5, r7
2519	LDRD	r8, r9, [r0, #40]
2520	LDRD	r6, r7, [r0, #48]
2521	STRD	r4, r5, [r0, #32]
2522	EOR	r8, r8, r6
2523	EOR	r9, r9, r7
2524	AND	r10, r10, r8
2525	AND	r11, r11, r9
2526	EOR	r10, r10, r6
2527	EOR	r11, r11, r7
2528	LDRD	r6, r7, [r0, #32]
2529	ADDS	r6, r6, r10
2530	ADC	r7, r7, r11
2531	STRD	r6, r7, [r0, #32]
2532	MOV	r10, r8
2533	MOV	r11, r9
2534	/* Round 4 */
2535	LDRD	r4, r5, [r0]
2536	LSRS	r6, r4, #14
2537	LSRS	r7, r5, #14
2538	ORR	r7, r7, r4, LSL #18
2539	ORR	r6, r6, r5, LSL #18
2540	LSRS	r8, r4, #18
2541	LSRS	r9, r5, #18
2542	ORR	r9, r9, r4, LSL #14
2543	ORR	r8, r8, r5, LSL #14
2544	EOR	r6, r6, r8
2545	EOR	r7, r7, r9
2546	LSLS	r8, r4, #23
2547	LSLS	r9, r5, #23
2548	ORR	r9, r9, r4, LSR #9
2549	ORR	r8, r8, r5, LSR #9
2550	LDRD	r4, r5, [r0, #24]
2551	EOR	r6, r6, r8
2552	EOR	r7, r7, r9
2553	ADDS	r4, r4, r6
2554	ADC	r5, r5, r7
2555	STRD	r4, r5, [r0, #24]
2556	LDRD	r4, r5, [r0]
2557	LDRD	r6, r7, [r0, #8]
2558	LDRD	r8, r9, [r0, #16]
2559	EOR	r6, r6, r8
2560	EOR	r7, r7, r9
2561	AND	r6, r6, r4
2562	AND	r7, r7, r5
2563	EOR	r6, r6, r8
2564	EOR	r7, r7, r9
2565	LDRD	r4, r5, [r0, #24]
2566	LDRD	r8, r9, [sp, #32]
2567	ADDS	r4, r4, r6
2568	ADC	r5, r5, r7
2569	LDRD	r6, r7, [r3, #32]
2570	ADDS	r4, r4, r8
2571	ADC	r5, r5, r9
2572	LDRD	r8, r9, [r0, #56]
2573	ADDS	r4, r4, r6
2574	ADC	r5, r5, r7
2575	STRD	r4, r5, [r0, #24]
2576	ADDS	r8, r8, r4
2577	ADC	r9, r9, r5
2578	LDRD	r4, r5, [r0, #32]
2579	STRD	r8, r9, [r0, #56]
2580	LSRS	r6, r4, #28
2581	LSRS	r7, r5, #28
2582	ORR	r7, r7, r4, LSL #4
2583	ORR	r6, r6, r5, LSL #4
2584	LSLS	r8, r4, #30
2585	LSLS	r9, r5, #30
2586	ORR	r9, r9, r4, LSR #2
2587	ORR	r8, r8, r5, LSR #2
2588	EOR	r6, r6, r8
2589	EOR	r7, r7, r9
2590	LSLS	r8, r4, #25
2591	LSLS	r9, r5, #25
2592	ORR	r9, r9, r4, LSR #7
2593	ORR	r8, r8, r5, LSR #7
2594	LDRD	r4, r5, [r0, #24]
2595	EOR	r6, r6, r8
2596	EOR	r7, r7, r9
2597	ADDS	r4, r4, r6
2598	ADC	r5, r5, r7
2599	LDRD	r8, r9, [r0, #32]
2600	LDRD	r6, r7, [r0, #40]
2601	STRD	r4, r5, [r0, #24]
2602	EOR	r8, r8, r6
2603	EOR	r9, r9, r7
2604	AND	r10, r10, r8
2605	AND	r11, r11, r9
2606	EOR	r10, r10, r6
2607	EOR	r11, r11, r7
2608	LDRD	r6, r7, [r0, #24]
2609	ADDS	r6, r6, r10
2610	ADC	r7, r7, r11
2611	STRD	r6, r7, [r0, #24]
2612	MOV	r10, r8
2613	MOV	r11, r9
2614	/* Round 5 */
2615	LDRD	r4, r5, [r0, #56]
2616	LSRS	r6, r4, #14
2617	LSRS	r7, r5, #14
2618	ORR	r7, r7, r4, LSL #18
2619	ORR	r6, r6, r5, LSL #18
2620	LSRS	r8, r4, #18
2621	LSRS	r9, r5, #18
2622	ORR	r9, r9, r4, LSL #14
2623	ORR	r8, r8, r5, LSL #14
2624	EOR	r6, r6, r8
2625	EOR	r7, r7, r9
2626	LSLS	r8, r4, #23
2627	LSLS	r9, r5, #23
2628	ORR	r9, r9, r4, LSR #9
2629	ORR	r8, r8, r5, LSR #9
2630	LDRD	r4, r5, [r0, #16]
2631	EOR	r6, r6, r8
2632	EOR	r7, r7, r9
2633	ADDS	r4, r4, r6
2634	ADC	r5, r5, r7
2635	STRD	r4, r5, [r0, #16]
2636	LDRD	r4, r5, [r0, #56]
2637	LDRD	r6, r7, [r0]
2638	LDRD	r8, r9, [r0, #8]
2639	EOR	r6, r6, r8
2640	EOR	r7, r7, r9
2641	AND	r6, r6, r4
2642	AND	r7, r7, r5
2643	EOR	r6, r6, r8
2644	EOR	r7, r7, r9
2645	LDRD	r4, r5, [r0, #16]
2646	LDRD	r8, r9, [sp, #40]
2647	ADDS	r4, r4, r6
2648	ADC	r5, r5, r7
2649	LDRD	r6, r7, [r3, #40]
2650	ADDS	r4, r4, r8
2651	ADC	r5, r5, r9
2652	LDRD	r8, r9, [r0, #48]
2653	ADDS	r4, r4, r6
2654	ADC	r5, r5, r7
2655	STRD	r4, r5, [r0, #16]
2656	ADDS	r8, r8, r4
2657	ADC	r9, r9, r5
2658	LDRD	r4, r5, [r0, #24]
2659	STRD	r8, r9, [r0, #48]
2660	LSRS	r6, r4, #28
2661	LSRS	r7, r5, #28
2662	ORR	r7, r7, r4, LSL #4
2663	ORR	r6, r6, r5, LSL #4
2664	LSLS	r8, r4, #30
2665	LSLS	r9, r5, #30
2666	ORR	r9, r9, r4, LSR #2
2667	ORR	r8, r8, r5, LSR #2
2668	EOR	r6, r6, r8
2669	EOR	r7, r7, r9
2670	LSLS	r8, r4, #25
2671	LSLS	r9, r5, #25
2672	ORR	r9, r9, r4, LSR #7
2673	ORR	r8, r8, r5, LSR #7
2674	LDRD	r4, r5, [r0, #16]
2675	EOR	r6, r6, r8
2676	EOR	r7, r7, r9
2677	ADDS	r4, r4, r6
2678	ADC	r5, r5, r7
2679	LDRD	r8, r9, [r0, #24]
2680	LDRD	r6, r7, [r0, #32]
2681	STRD	r4, r5, [r0, #16]
2682	EOR	r8, r8, r6
2683	EOR	r9, r9, r7
2684	AND	r10, r10, r8
2685	AND	r11, r11, r9
2686	EOR	r10, r10, r6
2687	EOR	r11, r11, r7
2688	LDRD	r6, r7, [r0, #16]
2689	ADDS	r6, r6, r10
2690	ADC	r7, r7, r11
2691	STRD	r6, r7, [r0, #16]
2692	MOV	r10, r8
2693	MOV	r11, r9
2694	/* Round 6 */
2695	LDRD	r4, r5, [r0, #48]
2696	LSRS	r6, r4, #14
2697	LSRS	r7, r5, #14
2698	ORR	r7, r7, r4, LSL #18
2699	ORR	r6, r6, r5, LSL #18
2700	LSRS	r8, r4, #18
2701	LSRS	r9, r5, #18
2702	ORR	r9, r9, r4, LSL #14
2703	ORR	r8, r8, r5, LSL #14
2704	EOR	r6, r6, r8
2705	EOR	r7, r7, r9
2706	LSLS	r8, r4, #23
2707	LSLS	r9, r5, #23
2708	ORR	r9, r9, r4, LSR #9
2709	ORR	r8, r8, r5, LSR #9
2710	LDRD	r4, r5, [r0, #8]
2711	EOR	r6, r6, r8
2712	EOR	r7, r7, r9
2713	ADDS	r4, r4, r6
2714	ADC	r5, r5, r7
2715	STRD	r4, r5, [r0, #8]
2716	LDRD	r4, r5, [r0, #48]
2717	LDRD	r6, r7, [r0, #56]
2718	LDRD	r8, r9, [r0]
2719	EOR	r6, r6, r8
2720	EOR	r7, r7, r9
2721	AND	r6, r6, r4
2722	AND	r7, r7, r5
2723	EOR	r6, r6, r8
2724	EOR	r7, r7, r9
2725	LDRD	r4, r5, [r0, #8]
2726	LDRD	r8, r9, [sp, #48]
2727	ADDS	r4, r4, r6
2728	ADC	r5, r5, r7
2729	LDRD	r6, r7, [r3, #48]
2730	ADDS	r4, r4, r8
2731	ADC	r5, r5, r9
2732	LDRD	r8, r9, [r0, #40]
2733	ADDS	r4, r4, r6
2734	ADC	r5, r5, r7
2735	STRD	r4, r5, [r0, #8]
2736	ADDS	r8, r8, r4
2737	ADC	r9, r9, r5
2738	LDRD	r4, r5, [r0, #16]
2739	STRD	r8, r9, [r0, #40]
2740	LSRS	r6, r4, #28
2741	LSRS	r7, r5, #28
2742	ORR	r7, r7, r4, LSL #4
2743	ORR	r6, r6, r5, LSL #4
2744	LSLS	r8, r4, #30
2745	LSLS	r9, r5, #30
2746	ORR	r9, r9, r4, LSR #2
2747	ORR	r8, r8, r5, LSR #2
2748	EOR	r6, r6, r8
2749	EOR	r7, r7, r9
2750	LSLS	r8, r4, #25
2751	LSLS	r9, r5, #25
2752	ORR	r9, r9, r4, LSR #7
2753	ORR	r8, r8, r5, LSR #7
2754	LDRD	r4, r5, [r0, #8]
2755	EOR	r6, r6, r8
2756	EOR	r7, r7, r9
2757	ADDS	r4, r4, r6
2758	ADC	r5, r5, r7
2759	LDRD	r8, r9, [r0, #16]
2760	LDRD	r6, r7, [r0, #24]
2761	STRD	r4, r5, [r0, #8]
2762	EOR	r8, r8, r6
2763	EOR	r9, r9, r7
2764	AND	r10, r10, r8
2765	AND	r11, r11, r9
2766	EOR	r10, r10, r6
2767	EOR	r11, r11, r7
2768	LDRD	r6, r7, [r0, #8]
2769	ADDS	r6, r6, r10
2770	ADC	r7, r7, r11
2771	STRD	r6, r7, [r0, #8]
2772	MOV	r10, r8
2773	MOV	r11, r9
2774	/* Round 7 */
2775	LDRD	r4, r5, [r0, #40]
2776	LSRS	r6, r4, #14
2777	LSRS	r7, r5, #14
2778	ORR	r7, r7, r4, LSL #18
2779	ORR	r6, r6, r5, LSL #18
2780	LSRS	r8, r4, #18
2781	LSRS	r9, r5, #18
2782	ORR	r9, r9, r4, LSL #14
2783	ORR	r8, r8, r5, LSL #14
2784	EOR	r6, r6, r8
2785	EOR	r7, r7, r9
2786	LSLS	r8, r4, #23
2787	LSLS	r9, r5, #23
2788	ORR	r9, r9, r4, LSR #9
2789	ORR	r8, r8, r5, LSR #9
2790	LDRD	r4, r5, [r0]
2791	EOR	r6, r6, r8
2792	EOR	r7, r7, r9
2793	ADDS	r4, r4, r6
2794	ADC	r5, r5, r7
2795	STRD	r4, r5, [r0]
2796	LDRD	r4, r5, [r0, #40]
2797	LDRD	r6, r7, [r0, #48]
2798	LDRD	r8, r9, [r0, #56]
2799	EOR	r6, r6, r8
2800	EOR	r7, r7, r9
2801	AND	r6, r6, r4
2802	AND	r7, r7, r5
2803	EOR	r6, r6, r8
2804	EOR	r7, r7, r9
2805	LDRD	r4, r5, [r0]
2806	LDRD	r8, r9, [sp, #56]
2807	ADDS	r4, r4, r6
2808	ADC	r5, r5, r7
2809	LDRD	r6, r7, [r3, #56]
2810	ADDS	r4, r4, r8
2811	ADC	r5, r5, r9
2812	LDRD	r8, r9, [r0, #32]
2813	ADDS	r4, r4, r6
2814	ADC	r5, r5, r7
2815	STRD	r4, r5, [r0]
2816	ADDS	r8, r8, r4
2817	ADC	r9, r9, r5
2818	LDRD	r4, r5, [r0, #8]
2819	STRD	r8, r9, [r0, #32]
2820	LSRS	r6, r4, #28
2821	LSRS	r7, r5, #28
2822	ORR	r7, r7, r4, LSL #4
2823	ORR	r6, r6, r5, LSL #4
2824	LSLS	r8, r4, #30
2825	LSLS	r9, r5, #30
2826	ORR	r9, r9, r4, LSR #2
2827	ORR	r8, r8, r5, LSR #2
2828	EOR	r6, r6, r8
2829	EOR	r7, r7, r9
2830	LSLS	r8, r4, #25
2831	LSLS	r9, r5, #25
2832	ORR	r9, r9, r4, LSR #7
2833	ORR	r8, r8, r5, LSR #7
2834	LDRD	r4, r5, [r0]
2835	EOR	r6, r6, r8
2836	EOR	r7, r7, r9
2837	ADDS	r4, r4, r6
2838	ADC	r5, r5, r7
2839	LDRD	r8, r9, [r0, #8]
2840	LDRD	r6, r7, [r0, #16]
2841	STRD	r4, r5, [r0]
2842	EOR	r8, r8, r6
2843	EOR	r9, r9, r7
2844	AND	r10, r10, r8
2845	AND	r11, r11, r9
2846	EOR	r10, r10, r6
2847	EOR	r11, r11, r7
2848	LDRD	r6, r7, [r0]
2849	ADDS	r6, r6, r10
2850	ADC	r7, r7, r11
2851	STRD	r6, r7, [r0]
2852	MOV	r10, r8
2853	MOV	r11, r9
2854	/* Round 8 */
2855	LDRD	r4, r5, [r0, #32]
2856	LSRS	r6, r4, #14
2857	LSRS	r7, r5, #14
2858	ORR	r7, r7, r4, LSL #18
2859	ORR	r6, r6, r5, LSL #18
2860	LSRS	r8, r4, #18
2861	LSRS	r9, r5, #18
2862	ORR	r9, r9, r4, LSL #14
2863	ORR	r8, r8, r5, LSL #14
2864	EOR	r6, r6, r8
2865	EOR	r7, r7, r9
2866	LSLS	r8, r4, #23
2867	LSLS	r9, r5, #23
2868	ORR	r9, r9, r4, LSR #9
2869	ORR	r8, r8, r5, LSR #9
2870	LDRD	r4, r5, [r0, #56]
2871	EOR	r6, r6, r8
2872	EOR	r7, r7, r9
2873	ADDS	r4, r4, r6
2874	ADC	r5, r5, r7
2875	STRD	r4, r5, [r0, #56]
2876	LDRD	r4, r5, [r0, #32]
2877	LDRD	r6, r7, [r0, #40]
2878	LDRD	r8, r9, [r0, #48]
2879	EOR	r6, r6, r8
2880	EOR	r7, r7, r9
2881	AND	r6, r6, r4
2882	AND	r7, r7, r5
2883	EOR	r6, r6, r8
2884	EOR	r7, r7, r9
2885	LDRD	r4, r5, [r0, #56]
2886	LDRD	r8, r9, [sp, #64]
2887	ADDS	r4, r4, r6
2888	ADC	r5, r5, r7
2889	LDRD	r6, r7, [r3, #64]
2890	ADDS	r4, r4, r8
2891	ADC	r5, r5, r9
2892	LDRD	r8, r9, [r0, #24]
2893	ADDS	r4, r4, r6
2894	ADC	r5, r5, r7
2895	STRD	r4, r5, [r0, #56]
2896	ADDS	r8, r8, r4
2897	ADC	r9, r9, r5
2898	LDRD	r4, r5, [r0]
2899	STRD	r8, r9, [r0, #24]
2900	LSRS	r6, r4, #28
2901	LSRS	r7, r5, #28
2902	ORR	r7, r7, r4, LSL #4
2903	ORR	r6, r6, r5, LSL #4
2904	LSLS	r8, r4, #30
2905	LSLS	r9, r5, #30
2906	ORR	r9, r9, r4, LSR #2
2907	ORR	r8, r8, r5, LSR #2
2908	EOR	r6, r6, r8
2909	EOR	r7, r7, r9
2910	LSLS	r8, r4, #25
2911	LSLS	r9, r5, #25
2912	ORR	r9, r9, r4, LSR #7
2913	ORR	r8, r8, r5, LSR #7
2914	LDRD	r4, r5, [r0, #56]
2915	EOR	r6, r6, r8
2916	EOR	r7, r7, r9
2917	ADDS	r4, r4, r6
2918	ADC	r5, r5, r7
2919	LDRD	r8, r9, [r0]
2920	LDRD	r6, r7, [r0, #8]
2921	STRD	r4, r5, [r0, #56]
2922	EOR	r8, r8, r6
2923	EOR	r9, r9, r7
2924	AND	r10, r10, r8
2925	AND	r11, r11, r9
2926	EOR	r10, r10, r6
2927	EOR	r11, r11, r7
2928	LDRD	r6, r7, [r0, #56]
2929	ADDS	r6, r6, r10
2930	ADC	r7, r7, r11
2931	STRD	r6, r7, [r0, #56]
2932	MOV	r10, r8
2933	MOV	r11, r9
2934	/* Round 9 */
2935	LDRD	r4, r5, [r0, #24]
2936	LSRS	r6, r4, #14
2937	LSRS	r7, r5, #14
2938	ORR	r7, r7, r4, LSL #18
2939	ORR	r6, r6, r5, LSL #18
2940	LSRS	r8, r4, #18
2941	LSRS	r9, r5, #18
2942	ORR	r9, r9, r4, LSL #14
2943	ORR	r8, r8, r5, LSL #14
2944	EOR	r6, r6, r8
2945	EOR	r7, r7, r9
2946	LSLS	r8, r4, #23
2947	LSLS	r9, r5, #23
2948	ORR	r9, r9, r4, LSR #9
2949	ORR	r8, r8, r5, LSR #9
2950	LDRD	r4, r5, [r0, #48]
2951	EOR	r6, r6, r8
2952	EOR	r7, r7, r9
2953	ADDS	r4, r4, r6
2954	ADC	r5, r5, r7
2955	STRD	r4, r5, [r0, #48]
2956	LDRD	r4, r5, [r0, #24]
2957	LDRD	r6, r7, [r0, #32]
2958	LDRD	r8, r9, [r0, #40]
2959	EOR	r6, r6, r8
2960	EOR	r7, r7, r9
2961	AND	r6, r6, r4
2962	AND	r7, r7, r5
2963	EOR	r6, r6, r8
2964	EOR	r7, r7, r9
2965	LDRD	r4, r5, [r0, #48]
2966	LDRD	r8, r9, [sp, #72]
2967	ADDS	r4, r4, r6
2968	ADC	r5, r5, r7
2969	LDRD	r6, r7, [r3, #72]
2970	ADDS	r4, r4, r8
2971	ADC	r5, r5, r9
2972	LDRD	r8, r9, [r0, #16]
2973	ADDS	r4, r4, r6
2974	ADC	r5, r5, r7
2975	STRD	r4, r5, [r0, #48]
2976	ADDS	r8, r8, r4
2977	ADC	r9, r9, r5
2978	LDRD	r4, r5, [r0, #56]
2979	STRD	r8, r9, [r0, #16]
2980	LSRS	r6, r4, #28
2981	LSRS	r7, r5, #28
2982	ORR	r7, r7, r4, LSL #4
2983	ORR	r6, r6, r5, LSL #4
2984	LSLS	r8, r4, #30
2985	LSLS	r9, r5, #30
2986	ORR	r9, r9, r4, LSR #2
2987	ORR	r8, r8, r5, LSR #2
2988	EOR	r6, r6, r8
2989	EOR	r7, r7, r9
2990	LSLS	r8, r4, #25
2991	LSLS	r9, r5, #25
2992	ORR	r9, r9, r4, LSR #7
2993	ORR	r8, r8, r5, LSR #7
2994	LDRD	r4, r5, [r0, #48]
2995	EOR	r6, r6, r8
2996	EOR	r7, r7, r9
2997	ADDS	r4, r4, r6
2998	ADC	r5, r5, r7
2999	LDRD	r8, r9, [r0, #56]
3000	LDRD	r6, r7, [r0]
3001	STRD	r4, r5, [r0, #48]
3002	EOR	r8, r8, r6
3003	EOR	r9, r9, r7
3004	AND	r10, r10, r8
3005	AND	r11, r11, r9
3006	EOR	r10, r10, r6
3007	EOR	r11, r11, r7
3008	LDRD	r6, r7, [r0, #48]
3009	ADDS	r6, r6, r10
3010	ADC	r7, r7, r11
3011	STRD	r6, r7, [r0, #48]
3012	MOV	r10, r8
3013	MOV	r11, r9
3014	/* Round 10 */
3015	LDRD	r4, r5, [r0, #16]
3016	LSRS	r6, r4, #14
3017	LSRS	r7, r5, #14
3018	ORR	r7, r7, r4, LSL #18
3019	ORR	r6, r6, r5, LSL #18
3020	LSRS	r8, r4, #18
3021	LSRS	r9, r5, #18
3022	ORR	r9, r9, r4, LSL #14
3023	ORR	r8, r8, r5, LSL #14
3024	EOR	r6, r6, r8
3025	EOR	r7, r7, r9
3026	LSLS	r8, r4, #23
3027	LSLS	r9, r5, #23
3028	ORR	r9, r9, r4, LSR #9
3029	ORR	r8, r8, r5, LSR #9
3030	LDRD	r4, r5, [r0, #40]
3031	EOR	r6, r6, r8
3032	EOR	r7, r7, r9
3033	ADDS	r4, r4, r6
3034	ADC	r5, r5, r7
3035	STRD	r4, r5, [r0, #40]
3036	LDRD	r4, r5, [r0, #16]
3037	LDRD	r6, r7, [r0, #24]
3038	LDRD	r8, r9, [r0, #32]
3039	EOR	r6, r6, r8
3040	EOR	r7, r7, r9
3041	AND	r6, r6, r4
3042	AND	r7, r7, r5
3043	EOR	r6, r6, r8
3044	EOR	r7, r7, r9
3045	LDRD	r4, r5, [r0, #40]
3046	LDRD	r8, r9, [sp, #80]
3047	ADDS	r4, r4, r6
3048	ADC	r5, r5, r7
3049	LDRD	r6, r7, [r3, #80]
3050	ADDS	r4, r4, r8
3051	ADC	r5, r5, r9
3052	LDRD	r8, r9, [r0, #8]
3053	ADDS	r4, r4, r6
3054	ADC	r5, r5, r7
3055	STRD	r4, r5, [r0, #40]
3056	ADDS	r8, r8, r4
3057	ADC	r9, r9, r5
3058	LDRD	r4, r5, [r0, #48]
3059	STRD	r8, r9, [r0, #8]
3060	LSRS	r6, r4, #28
3061	LSRS	r7, r5, #28
3062	ORR	r7, r7, r4, LSL #4
3063	ORR	r6, r6, r5, LSL #4
3064	LSLS	r8, r4, #30
3065	LSLS	r9, r5, #30
3066	ORR	r9, r9, r4, LSR #2
3067	ORR	r8, r8, r5, LSR #2
3068	EOR	r6, r6, r8
3069	EOR	r7, r7, r9
3070	LSLS	r8, r4, #25
3071	LSLS	r9, r5, #25
3072	ORR	r9, r9, r4, LSR #7
3073	ORR	r8, r8, r5, LSR #7
3074	LDRD	r4, r5, [r0, #40]
3075	EOR	r6, r6, r8
3076	EOR	r7, r7, r9
3077	ADDS	r4, r4, r6
3078	ADC	r5, r5, r7
3079	LDRD	r8, r9, [r0, #48]
3080	LDRD	r6, r7, [r0, #56]
3081	STRD	r4, r5, [r0, #40]
3082	EOR	r8, r8, r6
3083	EOR	r9, r9, r7
3084	AND	r10, r10, r8
3085	AND	r11, r11, r9
3086	EOR	r10, r10, r6
3087	EOR	r11, r11, r7
3088	LDRD	r6, r7, [r0, #40]
3089	ADDS	r6, r6, r10
3090	ADC	r7, r7, r11
3091	STRD	r6, r7, [r0, #40]
3092	MOV	r10, r8
3093	MOV	r11, r9
3094	/* Round 11 */
3095	LDRD	r4, r5, [r0, #8]
3096	LSRS	r6, r4, #14
3097	LSRS	r7, r5, #14
3098	ORR	r7, r7, r4, LSL #18
3099	ORR	r6, r6, r5, LSL #18
3100	LSRS	r8, r4, #18
3101	LSRS	r9, r5, #18
3102	ORR	r9, r9, r4, LSL #14
3103	ORR	r8, r8, r5, LSL #14
3104	EOR	r6, r6, r8
3105	EOR	r7, r7, r9
3106	LSLS	r8, r4, #23
3107	LSLS	r9, r5, #23
3108	ORR	r9, r9, r4, LSR #9
3109	ORR	r8, r8, r5, LSR #9
3110	LDRD	r4, r5, [r0, #32]
3111	EOR	r6, r6, r8
3112	EOR	r7, r7, r9
3113	ADDS	r4, r4, r6
3114	ADC	r5, r5, r7
3115	STRD	r4, r5, [r0, #32]
3116	LDRD	r4, r5, [r0, #8]
3117	LDRD	r6, r7, [r0, #16]
3118	LDRD	r8, r9, [r0, #24]
3119	EOR	r6, r6, r8
3120	EOR	r7, r7, r9
3121	AND	r6, r6, r4
3122	AND	r7, r7, r5
3123	EOR	r6, r6, r8
3124	EOR	r7, r7, r9
3125	LDRD	r4, r5, [r0, #32]
3126	LDRD	r8, r9, [sp, #88]
3127	ADDS	r4, r4, r6
3128	ADC	r5, r5, r7
3129	LDRD	r6, r7, [r3, #88]
3130	ADDS	r4, r4, r8
3131	ADC	r5, r5, r9
3132	LDRD	r8, r9, [r0]
3133	ADDS	r4, r4, r6
3134	ADC	r5, r5, r7
3135	STRD	r4, r5, [r0, #32]
3136	ADDS	r8, r8, r4
3137	ADC	r9, r9, r5
3138	LDRD	r4, r5, [r0, #40]
3139	STRD	r8, r9, [r0]
3140	LSRS	r6, r4, #28
3141	LSRS	r7, r5, #28
3142	ORR	r7, r7, r4, LSL #4
3143	ORR	r6, r6, r5, LSL #4
3144	LSLS	r8, r4, #30
3145	LSLS	r9, r5, #30
3146	ORR	r9, r9, r4, LSR #2
3147	ORR	r8, r8, r5, LSR #2
3148	EOR	r6, r6, r8
3149	EOR	r7, r7, r9
3150	LSLS	r8, r4, #25
3151	LSLS	r9, r5, #25
3152	ORR	r9, r9, r4, LSR #7
3153	ORR	r8, r8, r5, LSR #7
3154	LDRD	r4, r5, [r0, #32]
3155	EOR	r6, r6, r8
3156	EOR	r7, r7, r9
3157	ADDS	r4, r4, r6
3158	ADC	r5, r5, r7
3159	LDRD	r8, r9, [r0, #40]
3160	LDRD	r6, r7, [r0, #48]
3161	STRD	r4, r5, [r0, #32]
3162	EOR	r8, r8, r6
3163	EOR	r9, r9, r7
3164	AND	r10, r10, r8
3165	AND	r11, r11, r9
3166	EOR	r10, r10, r6
3167	EOR	r11, r11, r7
3168	LDRD	r6, r7, [r0, #32]
3169	ADDS	r6, r6, r10
3170	ADC	r7, r7, r11
3171	STRD	r6, r7, [r0, #32]
3172	MOV	r10, r8
3173	MOV	r11, r9
3174	/* Round 12 */
3175	LDRD	r4, r5, [r0]
3176	LSRS	r6, r4, #14
3177	LSRS	r7, r5, #14
3178	ORR	r7, r7, r4, LSL #18
3179	ORR	r6, r6, r5, LSL #18
3180	LSRS	r8, r4, #18
3181	LSRS	r9, r5, #18
3182	ORR	r9, r9, r4, LSL #14
3183	ORR	r8, r8, r5, LSL #14
3184	EOR	r6, r6, r8
3185	EOR	r7, r7, r9
3186	LSLS	r8, r4, #23
3187	LSLS	r9, r5, #23
3188	ORR	r9, r9, r4, LSR #9
3189	ORR	r8, r8, r5, LSR #9
3190	LDRD	r4, r5, [r0, #24]
3191	EOR	r6, r6, r8
3192	EOR	r7, r7, r9
3193	ADDS	r4, r4, r6
3194	ADC	r5, r5, r7
3195	STRD	r4, r5, [r0, #24]
3196	LDRD	r4, r5, [r0]
3197	LDRD	r6, r7, [r0, #8]
3198	LDRD	r8, r9, [r0, #16]
3199	EOR	r6, r6, r8
3200	EOR	r7, r7, r9
3201	AND	r6, r6, r4
3202	AND	r7, r7, r5
3203	EOR	r6, r6, r8
3204	EOR	r7, r7, r9
3205	LDRD	r4, r5, [r0, #24]
3206	LDRD	r8, r9, [sp, #96]
3207	ADDS	r4, r4, r6
3208	ADC	r5, r5, r7
3209	LDRD	r6, r7, [r3, #96]
3210	ADDS	r4, r4, r8
3211	ADC	r5, r5, r9
3212	LDRD	r8, r9, [r0, #56]
3213	ADDS	r4, r4, r6
3214	ADC	r5, r5, r7
3215	STRD	r4, r5, [r0, #24]
3216	ADDS	r8, r8, r4
3217	ADC	r9, r9, r5
3218	LDRD	r4, r5, [r0, #32]
3219	STRD	r8, r9, [r0, #56]
3220	LSRS	r6, r4, #28
3221	LSRS	r7, r5, #28
3222	ORR	r7, r7, r4, LSL #4
3223	ORR	r6, r6, r5, LSL #4
3224	LSLS	r8, r4, #30
3225	LSLS	r9, r5, #30
3226	ORR	r9, r9, r4, LSR #2
3227	ORR	r8, r8, r5, LSR #2
3228	EOR	r6, r6, r8
3229	EOR	r7, r7, r9
3230	LSLS	r8, r4, #25
3231	LSLS	r9, r5, #25
3232	ORR	r9, r9, r4, LSR #7
3233	ORR	r8, r8, r5, LSR #7
3234	LDRD	r4, r5, [r0, #24]
3235	EOR	r6, r6, r8
3236	EOR	r7, r7, r9
3237	ADDS	r4, r4, r6
3238	ADC	r5, r5, r7
3239	LDRD	r8, r9, [r0, #32]
3240	LDRD	r6, r7, [r0, #40]
3241	STRD	r4, r5, [r0, #24]
3242	EOR	r8, r8, r6
3243	EOR	r9, r9, r7
3244	AND	r10, r10, r8
3245	AND	r11, r11, r9
3246	EOR	r10, r10, r6
3247	EOR	r11, r11, r7
3248	LDRD	r6, r7, [r0, #24]
3249	ADDS	r6, r6, r10
3250	ADC	r7, r7, r11
3251	STRD	r6, r7, [r0, #24]
3252	MOV	r10, r8
3253	MOV	r11, r9
3254	/* Round 13 */
3255	LDRD	r4, r5, [r0, #56]
3256	LSRS	r6, r4, #14
3257	LSRS	r7, r5, #14
3258	ORR	r7, r7, r4, LSL #18
3259	ORR	r6, r6, r5, LSL #18
3260	LSRS	r8, r4, #18
3261	LSRS	r9, r5, #18
3262	ORR	r9, r9, r4, LSL #14
3263	ORR	r8, r8, r5, LSL #14
3264	EOR	r6, r6, r8
3265	EOR	r7, r7, r9
3266	LSLS	r8, r4, #23
3267	LSLS	r9, r5, #23
3268	ORR	r9, r9, r4, LSR #9
3269	ORR	r8, r8, r5, LSR #9
3270	LDRD	r4, r5, [r0, #16]
3271	EOR	r6, r6, r8
3272	EOR	r7, r7, r9
3273	ADDS	r4, r4, r6
3274	ADC	r5, r5, r7
3275	STRD	r4, r5, [r0, #16]
3276	LDRD	r4, r5, [r0, #56]
3277	LDRD	r6, r7, [r0]
3278	LDRD	r8, r9, [r0, #8]
3279	EOR	r6, r6, r8
3280	EOR	r7, r7, r9
3281	AND	r6, r6, r4
3282	AND	r7, r7, r5
3283	EOR	r6, r6, r8
3284	EOR	r7, r7, r9
3285	LDRD	r4, r5, [r0, #16]
3286	LDRD	r8, r9, [sp, #104]
3287	ADDS	r4, r4, r6
3288	ADC	r5, r5, r7
3289	LDRD	r6, r7, [r3, #104]
3290	ADDS	r4, r4, r8
3291	ADC	r5, r5, r9
3292	LDRD	r8, r9, [r0, #48]
3293	ADDS	r4, r4, r6
3294	ADC	r5, r5, r7
3295	STRD	r4, r5, [r0, #16]
3296	ADDS	r8, r8, r4
3297	ADC	r9, r9, r5
3298	LDRD	r4, r5, [r0, #24]
3299	STRD	r8, r9, [r0, #48]
3300	LSRS	r6, r4, #28
3301	LSRS	r7, r5, #28
3302	ORR	r7, r7, r4, LSL #4
3303	ORR	r6, r6, r5, LSL #4
3304	LSLS	r8, r4, #30
3305	LSLS	r9, r5, #30
3306	ORR	r9, r9, r4, LSR #2
3307	ORR	r8, r8, r5, LSR #2
3308	EOR	r6, r6, r8
3309	EOR	r7, r7, r9
3310	LSLS	r8, r4, #25
3311	LSLS	r9, r5, #25
3312	ORR	r9, r9, r4, LSR #7
3313	ORR	r8, r8, r5, LSR #7
3314	LDRD	r4, r5, [r0, #16]
3315	EOR	r6, r6, r8
3316	EOR	r7, r7, r9
3317	ADDS	r4, r4, r6
3318	ADC	r5, r5, r7
3319	LDRD	r8, r9, [r0, #24]
3320	LDRD	r6, r7, [r0, #32]
3321	STRD	r4, r5, [r0, #16]
3322	EOR	r8, r8, r6
3323	EOR	r9, r9, r7
3324	AND	r10, r10, r8
3325	AND	r11, r11, r9
3326	EOR	r10, r10, r6
3327	EOR	r11, r11, r7
3328	LDRD	r6, r7, [r0, #16]
3329	ADDS	r6, r6, r10
3330	ADC	r7, r7, r11
3331	STRD	r6, r7, [r0, #16]
3332	MOV	r10, r8
3333	MOV	r11, r9
3334	/* Round 14 */
3335	LDRD	r4, r5, [r0, #48]
3336	LSRS	r6, r4, #14
3337	LSRS	r7, r5, #14
3338	ORR	r7, r7, r4, LSL #18
3339	ORR	r6, r6, r5, LSL #18
3340	LSRS	r8, r4, #18
3341	LSRS	r9, r5, #18
3342	ORR	r9, r9, r4, LSL #14
3343	ORR	r8, r8, r5, LSL #14
3344	EOR	r6, r6, r8
3345	EOR	r7, r7, r9
3346	LSLS	r8, r4, #23
3347	LSLS	r9, r5, #23
3348	ORR	r9, r9, r4, LSR #9
3349	ORR	r8, r8, r5, LSR #9
3350	LDRD	r4, r5, [r0, #8]
3351	EOR	r6, r6, r8
3352	EOR	r7, r7, r9
3353	ADDS	r4, r4, r6
3354	ADC	r5, r5, r7
3355	STRD	r4, r5, [r0, #8]
3356	LDRD	r4, r5, [r0, #48]
3357	LDRD	r6, r7, [r0, #56]
3358	LDRD	r8, r9, [r0]
3359	EOR	r6, r6, r8
3360	EOR	r7, r7, r9
3361	AND	r6, r6, r4
3362	AND	r7, r7, r5
3363	EOR	r6, r6, r8
3364	EOR	r7, r7, r9
3365	LDRD	r4, r5, [r0, #8]
3366	LDRD	r8, r9, [sp, #112]
3367	ADDS	r4, r4, r6
3368	ADC	r5, r5, r7
3369	LDRD	r6, r7, [r3, #112]
3370	ADDS	r4, r4, r8
3371	ADC	r5, r5, r9
3372	LDRD	r8, r9, [r0, #40]
3373	ADDS	r4, r4, r6
3374	ADC	r5, r5, r7
3375	STRD	r4, r5, [r0, #8]
3376	ADDS	r8, r8, r4
3377	ADC	r9, r9, r5
3378	LDRD	r4, r5, [r0, #16]
3379	STRD	r8, r9, [r0, #40]
3380	LSRS	r6, r4, #28
3381	LSRS	r7, r5, #28
3382	ORR	r7, r7, r4, LSL #4
3383	ORR	r6, r6, r5, LSL #4
3384	LSLS	r8, r4, #30
3385	LSLS	r9, r5, #30
3386	ORR	r9, r9, r4, LSR #2
3387	ORR	r8, r8, r5, LSR #2
3388	EOR	r6, r6, r8
3389	EOR	r7, r7, r9
3390	LSLS	r8, r4, #25
3391	LSLS	r9, r5, #25
3392	ORR	r9, r9, r4, LSR #7
3393	ORR	r8, r8, r5, LSR #7
3394	LDRD	r4, r5, [r0, #8]
3395	EOR	r6, r6, r8
3396	EOR	r7, r7, r9
3397	ADDS	r4, r4, r6
3398	ADC	r5, r5, r7
3399	LDRD	r8, r9, [r0, #16]
3400	LDRD	r6, r7, [r0, #24]
3401	STRD	r4, r5, [r0, #8]
3402	EOR	r8, r8, r6
3403	EOR	r9, r9, r7
3404	AND	r10, r10, r8
3405	AND	r11, r11, r9
3406	EOR	r10, r10, r6
3407	EOR	r11, r11, r7
3408	LDRD	r6, r7, [r0, #8]
3409	ADDS	r6, r6, r10
3410	ADC	r7, r7, r11
3411	STRD	r6, r7, [r0, #8]
3412	MOV	r10, r8
3413	MOV	r11, r9
3414	/* Round 15 */
3415	LDRD	r4, r5, [r0, #40]
3416	LSRS	r6, r4, #14
3417	LSRS	r7, r5, #14
3418	ORR	r7, r7, r4, LSL #18
3419	ORR	r6, r6, r5, LSL #18
3420	LSRS	r8, r4, #18
3421	LSRS	r9, r5, #18
3422	ORR	r9, r9, r4, LSL #14
3423	ORR	r8, r8, r5, LSL #14
3424	EOR	r6, r6, r8
3425	EOR	r7, r7, r9
3426	LSLS	r8, r4, #23
3427	LSLS	r9, r5, #23
3428	ORR	r9, r9, r4, LSR #9
3429	ORR	r8, r8, r5, LSR #9
3430	LDRD	r4, r5, [r0]
3431	EOR	r6, r6, r8
3432	EOR	r7, r7, r9
3433	ADDS	r4, r4, r6
3434	ADC	r5, r5, r7
3435	STRD	r4, r5, [r0]
3436	LDRD	r4, r5, [r0, #40]
3437	LDRD	r6, r7, [r0, #48]
3438	LDRD	r8, r9, [r0, #56]
3439	EOR	r6, r6, r8
3440	EOR	r7, r7, r9
3441	AND	r6, r6, r4
3442	AND	r7, r7, r5
3443	EOR	r6, r6, r8
3444	EOR	r7, r7, r9
3445	LDRD	r4, r5, [r0]
3446	LDRD	r8, r9, [sp, #120]
3447	ADDS	r4, r4, r6
3448	ADC	r5, r5, r7
3449	LDRD	r6, r7, [r3, #120]
3450	ADDS	r4, r4, r8
3451	ADC	r5, r5, r9
3452	LDRD	r8, r9, [r0, #32]
3453	ADDS	r4, r4, r6
3454	ADC	r5, r5, r7
3455	STRD	r4, r5, [r0]
3456	ADDS	r8, r8, r4
3457	ADC	r9, r9, r5
3458	LDRD	r4, r5, [r0, #8]
3459	STRD	r8, r9, [r0, #32]
3460	LSRS	r6, r4, #28
3461	LSRS	r7, r5, #28
3462	ORR	r7, r7, r4, LSL #4
3463	ORR	r6, r6, r5, LSL #4
3464	LSLS	r8, r4, #30
3465	LSLS	r9, r5, #30
3466	ORR	r9, r9, r4, LSR #2
3467	ORR	r8, r8, r5, LSR #2
3468	EOR	r6, r6, r8
3469	EOR	r7, r7, r9
3470	LSLS	r8, r4, #25
3471	LSLS	r9, r5, #25
3472	ORR	r9, r9, r4, LSR #7
3473	ORR	r8, r8, r5, LSR #7
3474	LDRD	r4, r5, [r0]
3475	EOR	r6, r6, r8
3476	EOR	r7, r7, r9
3477	ADDS	r4, r4, r6
3478	ADC	r5, r5, r7
3479	LDRD	r8, r9, [r0, #8]
3480	LDRD	r6, r7, [r0, #16]
3481	STRD	r4, r5, [r0]
3482	EOR	r8, r8, r6
3483	EOR	r9, r9, r7
3484	AND	r10, r10, r8
3485	AND	r11, r11, r9
3486	EOR	r10, r10, r6
3487	EOR	r11, r11, r7
3488	LDRD	r6, r7, [r0]
3489	ADDS	r6, r6, r10
3490	ADC	r7, r7, r11
3491	STRD	r6, r7, [r0]
3492	MOV	r10, r8
3493	MOV	r11, r9
3494	/* Add in digest from start */
3495	LDRD	r4, r5, [r0]
3496	LDRD	r6, r7, [r0, #8]
3497	LDRD	r8, r9, [sp, #128]
3498	LDRD	r10, r11, [sp, #136]
3499	ADDS	r4, r4, r8
3500	ADC	r5, r5, r9
3501	ADDS	r6, r6, r10
3502	ADC	r7, r7, r11
3503	STRD	r4, r5, [r0]
3504	STRD	r6, r7, [r0, #8]
3505	STRD	r4, r5, [sp, #128]
3506	STRD	r6, r7, [sp, #136]
3507	LDRD	r4, r5, [r0, #16]
3508	LDRD	r6, r7, [r0, #24]
3509	LDRD	r8, r9, [sp, #144]
3510	LDRD	r10, r11, [sp, #152]
3511	ADDS	r4, r4, r8
3512	ADC	r5, r5, r9
3513	ADDS	r6, r6, r10
3514	ADC	r7, r7, r11
3515	STRD	r4, r5, [r0, #16]
3516	STRD	r6, r7, [r0, #24]
3517	STRD	r4, r5, [sp, #144]
3518	STRD	r6, r7, [sp, #152]
3519	LDRD	r4, r5, [r0, #32]
3520	LDRD	r6, r7, [r0, #40]
3521	LDRD	r8, r9, [sp, #160]
3522	LDRD	r10, r11, [sp, #168]
3523	ADDS	r4, r4, r8
3524	ADC	r5, r5, r9
3525	ADDS	r6, r6, r10
3526	ADC	r7, r7, r11
3527	STRD	r4, r5, [r0, #32]
3528	STRD	r6, r7, [r0, #40]
3529	STRD	r4, r5, [sp, #160]
3530	STRD	r6, r7, [sp, #168]
3531	LDRD	r4, r5, [r0, #48]
3532	LDRD	r6, r7, [r0, #56]
3533	LDRD	r8, r9, [sp, #176]
3534	LDRD	r10, r11, [sp, #184]
3535	ADDS	r4, r4, r8
3536	ADC	r5, r5, r9
3537	ADDS	r6, r6, r10
3538	ADC	r7, r7, r11
3539	STRD	r4, r5, [r0, #48]
3540	STRD	r6, r7, [r0, #56]
3541	STRD	r4, r5, [sp, #176]
3542	STRD	r6, r7, [sp, #184]
3543	SUBS	r2, r2, #0x80
3544	SUB	r3, r3, #0x200
3545	ADD	r1, r1, #0x80
3546#if defined(__GNUC__) || defined(__ICCARM__) || defined(__IAR_SYSTEMS_ICC__)
3547	BNE	L_SHA512_transform_len_begin
3548#else
3549	BNE.W	L_SHA512_transform_len_begin
3550#endif
3551	EOR	r0, r0, r0
3552	ADD	sp, sp, #0xc0
3553	POP	{r4, r5, r6, r7, r8, r9, r10, r11, pc}
3554	/* Cycle Count = 5021 */
3555	.size	Transform_Sha512_Len_base,.-Transform_Sha512_Len_base
3556#endif /* WOLFSSL_ARMASM_NO_NEON */
3557#endif /* WOLFSSL_SHA512 || WOLFSSL_SHA384 */
3558#endif /* WOLFSSL_ARMASM_THUMB2 */
3559#endif /* WOLFSSL_ARMASM */
3560
3561#if defined(__linux__) && defined(__ELF__)
3562.section	.note.GNU-stack,"",%progbits
3563#endif
3564#endif /* !WOLFSSL_ARMASM_INLINE */